PI6C210 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Differential Clock Generator Features Description Eight copies of Differential CPU Clock Output at 100 MHz Pericoms PI6C210 is produced using the Companys advanced submicron technology. One copy of CLK33 The clocks for the CPU are provided by HCLK and HCLK_bar [0:7] outputs. These eight differential CPU clock pairs run at 100 MHz. The VOH swing amplitude is configured by the MultSel0 and MultSel1 pins. One copy of 14.31818 MHz Reference Clock One copy of Differential 48 MHz Clock External Resistor for Current Reference Selection Logic for Differential Swing Control, Test Mode, HI-Z, Power-Down, Spread Spectrum Available Packaging: 48-pin TSSOP (A package) 48-pin SSOP (V package) Pin Configuration CLK33 VDD 48 MHz/SELA 48 MHz_bar/SELB GND VDD HCLK0 HCLK0_bar GND HCLK1 HCLK1_bar VDD HCLK2 HCLK2_bar GND HCLK3 HCLK3_bar VDD REFCLK SPREAD# VSS XTALI XTALO VDD Block Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin A, V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL100/133 GND VDDA GNDA PWRDN# VDD HCLK4 HCLK4_bar GND HCLK5 HCLK5_bar VDD HCLK6 HCLK6_bar GND HCLK7 HCLK7_bar VDD MULTSEL0 MULTSEL1 GND GNDA IREF VDDA XTAL_IN XTAL_OUT 1 REF OSC REFCLK 8 Spread# PLL1 MultSel0 HCLK [0:7] 8 MultSel1 PWRDWN# Control Register /3, /4, /6 HCLK_bar [0:7] 1 Sel100/133 SelA SelB CLK33 PLL2 1 48 MHz 1 48 MHz_bar 1 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Name Pin Type Pin D e s cription HCLK , HCLK _bar O Host Clock O utputs. these eight Differential CPU clock pairs run at 100 MHz. The VOH swing amplitude is configured by the Multsel0, Multsel1 pins. CLK 33 O 33 MHz Reference Clock. Host clock divided by 3, 4, or 6. 48 MHz, 48 MHz_bar I/O REFCLK O 14.318 MHz Reference Clock O utput. 3.3V copies of the 14.318 MHz reference clock. XTALI I Crystal connection or External Reference Frequency Input. Connect to either a 14.318 MHz crystal or an external reference signal. XTALO O Crystal Connection. An output connection for an external 14.318 MHz crystal. If using an external reference, this pin must be left unconnected. SPREAD# I Spread Spectrum Enable. 3.3V LVTTL compatible input that enables spread spectrum mode when held LO W. PWRDN# I Power Down Input. 3.3V LVTTL compatible asynchronous input that requests the device to enter power- down mode when it is held low. SELA, SELB I/O MultSel0, MultSel1 I Select Pins for VOH swing amplitude of HCLK and HCLK _bar VCC P Power Supply IREF I Current Reference. This pin establishes the reference current for the host clock pairs. 48 MHz Differential Clocks. Logic Select Pins. Select the mode of operation Group Skew and Jitter Specification Output Group Pin-to-pin Ske w, Pair-to-pair Ske w Cycle -cycle Jitte r Duty Cycle Type M e as ure d @ Host Clock 100ps 150ps 45/55 Differential Crossing CLK33 500ps 45/55 Single ended 3.3V 1.5V REFCLK 1000ps 45/55 Single ended 3.3V 1.5V 48 MHz 350ps 45/55 Single ended 3.3V 1.5V Group Offset Specification Group Offs e t Host to CLK 33 No requirement Host to REF No requirement Comme nts 2 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Select Signal Configurations SEL100/133 SELA SELB HCLK CLK33 48 M Hz, 48 M Hz_bar REF 0 0 0 100 MHz 33 MHz 48 MHz 14.318 Normal O peration 0 0 1 100 MHz 33 MHz Disable 14.318 Test Mode (recommended) 0 1 0 100 MHz Disable Disable 14.318 Test Mode (optional) 0 1 1 Hi- Z Hi- Z Hi- Z Hi- Z 1 0 0 133 MHz 33 MHz 48 MHz 14.318 O ptional 1 0 1 133 MHz 33 MHz Disable 14.318 O ptional 1 1 0 200 MHz 33 MHz 48 MHz 14.318 O ptional 1 1 1 TCLK /2 TCLK /8 TCLK /2 TCLK RESERVED Note s Hi- Z All O utputs Absolute Maximum DC Power Supply Symbol Parame te r M in. M ax. Units Note s VDD3 3.3V Core Supply Voltage 0.5 4.6 V VDDQ3 3.3V I/O Supply Voltage 0.5 4.6 V TS Storage Temperature 65 150 °C 2 Note: Maximum VIH not to exceed VDD3 +0.7V Absolute Maximum DC I/O Symbol Parame te r M in. M ax. Units Note s VIH3 3.3V Input High Voltage 0.5 4.6 V 1 VIL3 3.3V Input Low Voltage 0.5 V ESD prot. Input ESD Protection 2000 V 2 Notes: 1. Maximum VIH is not to exceed maximum 0.7V above VDD 2. Human body model 3 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Operating Requirements Symbol Parame te r VDD3 3.3V Supply Voltage VIH3 3.3V Input High Voltage VIL3 3.3V Input Low Voltage IIL Input Leakage Current Condition M in. M ax. Units Note s 3.3V ±5% 3.135 3.465 V 4 VDD3 2.0 VDD +0.3 V 7 VSS 0.3 0.8 V 7 0 < VIN < VDDQ3 5 +5 µA 3, 7 2.4 V 1 V 1 V 1 0.55 V 1, 5 5 pF 2 13.5 22.5 pF 6 0 70 °C VOH3 3.3V Output High Voltage IOH = 1mA VOL3 3.3V Output Low Voltage IOL = 1mA VPOH PCI Bus Output High Voltage IOH = 1mA VPOL PCI Bus Output Low Voltage IOL = 1mA CIN Input Pin Capacitance CXTAL Xtal Pin Capacitance TA Ambient Temperature No Airflow 0.4 2.4 Notes: 1. Signal edge is required to be monotonic when transitioning through this region. 2. This is a recommendation, not an absolute requirement. 3. Input Leakage Current does not include inputs with Pull-up or Pull-down resistors. Inputs with resistors should state current requirements. 4. No power sequencing is implied or allowed to be required in the system. 5. Conforms to 5V PCI signaling specification. 6. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal. 7. All inputs referenced to 3.3V power supply. Maximum Current Draw During PWRDWN# Parame te r M in. M ax. Units Note Current from 3.3V supply N/A 120 mA Configured w/475 Ohm current reference resistor Maximum Current Draw Parame te r M in. M ax. Units Current from 3.3V supply N/A 400 mA 4 Note Max. power supply (3.465V), all active, 475 Ohm current reference resistor, Host = 133 MHz PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Buffer Types Buffe r Name VCC Range (V) Impe dance (Ohms ) Buffe r Type 48 MHz, REF 3.135- 3.465 20- 60 Type 3 CLK 33 3.135- 3.465 12- 55 Type 5 Host/Host_bar Type X1 48 MHz, REF Operating Requirements Symbol Parame te r Condition M in. 29 IOHMIN Pull- up Current VOUT = 1.0V IOHMAX Pull- up Current VOUT = 3.135V IOLMIN Pull- down Current VOUT = 1.95V IOLMAX Pull- down Current VOUT = 0.4V M ax. Units mA 23 mA 29 mA 27 mA tRH 3.3V Type 3 O utput Rise Edge Rate 3.3V ±5% @ 0.4V 2.4V 0.5 2.0 V/nS tFH 3.3V Type 3 O utput Rise Fall Rate 3.3V ±5% @ 2.4V 0.4V 0.5 2.0 V/nS Condition M in. M ax. Units 33 CLK33 Operating Requirements Symbol Parame te r IOHMIN Pull- up Current VOUT = 1.0V IOHMAX Pull- up Current VOUT = 3.135V IOLMIN Pull- down Current VOUT = 1.95V IOLMAX Pull- down Current VOUT = 0.4V mA 33 mA 30 mA 38 mA tRH 3.3V Type 4 Output Rise Edge Rate 3.3V ±5% @ 0.4V 2.4V 1/1 4/1 V/ns tFH 3.3V Type 4 Output Rise Fall Rate 3.3V ±5% @ 2.4V 0.4V 1/1 4/1 V/ns 5 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Current-Mode Output Buffer Characteristics HCLK, HCLK_bar [0:7] VDD3 (3.3V –5%) Slope ~ 1/RO RO IOUT ROS IOUT 0V 1.2V VOUT VOUT = 1.2V max. Host Clock (HCSL) Buffer Characteristics M inimum M aximum RO 3000 O hms (recommended) N/A ROS unspecified unspecified VOUT N/A 1.2V Note: IOUT is selectable depending on implementation. The parameters above, however, apply to all configurations. VOUT is the voltage at the pin of the device. Current Accuracy Conditions Load M in. M ax. IOUT VDD = nominal (3.30V) Nominal test load for given configuration 7% INOMINAL +7% INOMINAL IOUT VDD = 3.30 ±5% Nominal test load for given configuration 12% INOMINAL +12% INOMINAL Note: INOMINAL refers to the expected current based on the configuration of the device. 6 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Timing Requirements Symbol Parame te r TPeriod 133 M Hz Hos t 100 M Hz Hos t Units Note s 10.2 nS 11,14 9.85 N/A nS 11,14 14.9 (0.74) 12.9 (0.65) 14.9 (0.74) mA (V) 11, 13,17 VSS = 0.0 0.05 VSS = 0.0 0.05 V 11 45% VOH 55% VOH 45% VOH 55% VOH V 11,14 M in. M ax. M in. M ax. Host CLK period - average 7.5 7.65 10.0 AbsMinPeriod Absolute minimum Host CLK Period 7.35 N/A IOH (VOH) O utput Current (Voltage at given load) 12.9 (0.65) VOL Vcrossover TRISE Host/CPU CLK Rise Time 175 700 175 700 pS 11,15 TFALL Host/CPU CLK Fall Time 175 700 175 700 pS 11,15 Rise/Fall Matching Rise Time and Fall Time Matching O vershoot 20% 20% 11,16 VOH +0.2V VOH +0.2V 11,16 Undershoot 0.2V 0.2V 11 Duty Cycle 45% 55% 45% 55% 11,14 TPeriod CLK 33 period 30.0 N/A 30.0 N/A nS 2,3,9 THIGH CLK 33 high time 12.0 N/A 12.0 N/A nS 5,10 TLO W CLK 33 low time 12.0 N/A 12.0 N/A nS 6,10 TRISE CLK 33 rise time 0.5 2.0 0.5 2.0 nS 8 TFALL CLK 33 fall time 0.5 2.0 0.5 2.0 nS 8 tPZL, tPZH O utput enable delay (all outputs) 1.0 10.0 1.0 10.0 nS tPLZ, tPZH O utput disable delay (all outputs) 1.0 10.0 1.0 10.0 nS tstable All clock stabilization from power- up 3 mS 3 7 Notes: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, Jitter, Offset, and Skew measured on rising edge @1.25V for 2.5V clocks and 1.5V for 3.3V clocks. 3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz. 4. PCI clock id the Host clock divided by six at Host = 200 MHz. 5. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 6. TLOW is measured at 0.4V for all outputs. 7. The time specified is measured from when VDDQ achieves its nominal operating level (typical condition VDDQ=3.3V) till the frequency output is stable and operating within specification. 8. TRISE and TFALL are measured as a transition through the threshold region VOL=0.4V, and VOH=2.4V (1mA) JEDEC Specification 9. The average period over any 1uS period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle. Pulsewidth is required to be wider at faster edge-rate to ensure dutycycle specification is met. 11. Test load is RS=33.2 Ohms, RP=49.9. 12. Must be guaranteed in realistic system environment. 13. Configured for IOH=6* IREF. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Determined as a fraction of 2* (TrpTrn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 17. These Min. and Max. voltages and currents assume a power supply of 3.30V. For system considerations, the voltages will need to be degraded to account for the ±5% variation in the 3.3V supply. 7 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Lumped Capacitive Test Loads for Single ended Outputs Clock M in. Load M ax. Load Units Note s 3V66 10 30 pF 1 device load, possible 2 loads 48 MHz Clock 10 20 pF 1 device load REF 10 20 pF 1 device load Notes: 1. Maximum rise/fall times are to be guaranteed at a maximum specified load for each type of output buffer. 2. Minimum rise/fall times are to be guaranteed at a minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. testing may be done with an additional 500 ohm resistor in parallel if properly correlated with the capacitie load. RP RS Test nodes RS RP Lumped Test Load Configurations for the Differential Host Clock Outputs Minimum and Maximum Lumped Resistive Test Loads Clock Host Clocks M in. Load M ax. Load Units 20 105 O hms 8 Note s PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Resistive Lumped Test Loads for Differential Host Clock Clock RS RP Units Note s Host Clocks 60 ohm configurations 33.2 1% 61.9 1% Ohms 2, 3, 5 Host Clocks 50 ohm configurations 33.2 1% 49.9 1% Ohms 1, 2, 3, 5 Host Clocks Double terminated Configuration 0 24.9 1% Ohms 4 Notes: 1. Expected test load configuration unless otherwise noted. This is a 50 ohm environment test load. This assumes device is configured for 50 ohm environment. 2. Test load for 60 ohm environment. This assumes device is configured for a 60 ohm environment. 3. Suppliers must correlate parameters measured in 50 ohm environment to a 60 ohm environment with the appropriate configurations of the device for each load. 4. Test load for dual terminated (ie both source and load) 50 ohm environment. 5. For configurations of the device intended to create output current greater than 14mA these test loads may not be appropriate. For such configurations, a value of RS = 0 should be used. 3.3 Volt Measure Points VDD3 Host Host_bar VOH = 2.4V VIH = 2.0V Tperiod 1.5V VIH = 0.8V VOH = 0.4V Component vs. System Measure Points for Single Ended Clocks Host Waveforms PWRDWN# Mode PWRDWN# Hos t/Hos t_bar CLK33 48 M Hz 14.318, REF Asserted = 0 = low Host = 2* Iref Host_bar = undriven Low Low Low (if applicable) Notes: 1. When PWRDWN# is asserted, a voltage must be held across the differential outputs. 2. There are no specific timing requirements for entering or exiting PWRDWN# mode. 9 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Host Swing Select Functions M ultSe l0 M ultSe l1 Board targe t Trace /Te rm Z Re fe re nce R, Ire f = VDD/3(3*Rr) Output Curre nt VOH @ Z, Ire f = 2.32mA 0 0 60 ohms Rr = 475 1%, Ire f = 2.32mA IOH = 5*Ire f 0.71V @ 60 0 0 50 ohms Rr = 475 1%, Iref = 2.32mA IOH = 5* Iref 0.59V @ 50 0 1 60 ohms Rr = 475 1%, Iref = 2.32mA IOH = 6* Iref 0.85V @ 60 0 1 50 ohms Rr = 475 1%, Ire f = 2.32mA IOH = 6*Ire f 0.71V @ 50 1 0 60 ohms Rr = 475 1%, Iref = 2.32mA IOH = 4* Iref 0.56V @ 60 1 0 50 ohms Rr = 475 1%, Iref = 2.32mA IOH = 4* Iref 0.47V @ 50 1 1 60 ohms Rr = 475 1%, Iref = 2.32mA IOH = 7* Iref 0.99V @ 60 1 1 50 ohms Rr = 475 1%, Iref = 2.32mA IOH = 7* Iref 0.82V @ 50 0 0 30 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 5* Iref 0.75V @ 30 0 0 25 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 5* Iref 0.62V @ 20 0 1 30 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 6* Iref 0.90V @ 30 0 1 25 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 6* Iref 0.75V @ 20 1 0 30 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 4* Iref 0.60V @ 30 1 0 25 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 4* Iref 0.5V @ 20 1 1 30 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 7* Iref 1.05V @ 30 1 1 25 (DC equiv) Rr = 221 1%, Iref = 5mA IOH = 7* Iref 0.84V @ 20 Notes: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations. 10 PS8599 01/29/02 PI6C210 Differential Clock Generator 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-pin TSSOP Packaging Mechanical (A) 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 0.45 .018 0.75 .030 .002 .006 0.05 0.15 .007 .010 0.17 0.27 .319 BSC 8.1 48-pin SSOP Packaging Mechanical (V) 48 .291 .299 7.39 7.59 .395 .420 10.03 10.67 Gauge Plane .010 0.25 .02 0.51 .04 1.01 1 .620 .630 15.75 16.00 .015 0.381 x 45˚ .025 0.635 .008 0.20 Nom. .110 2.79 Max .025 BSC 0.635 .008 0.20 .0135 0.34 .008 0.20 .016 0.40 0-8˚ X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information P/N De s cription PI6C210A 48- pin TSSO P PI6C210V 48- pin SSO P Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 11 PS8599 01/29/02