ETC PI74ALVTC16260A

ADVANCE INFORMATION
PI74ALVTC16260
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2.5V 12-Bit to 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Product Features
Product Description
• PI74ALVTC16260 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A56)
– 56-pin 173-mil wide plastic TVSOP (K56)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 1.65V to 3.6 VDD operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-plexing
address and data information in microprocessor or bus-interface
applications. This device is also useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the
A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
Logic Block Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
2
27
30
55
To ensure the high-impedance state during power up or power
down, OE should be tied to VDD through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
56
29
OE1B
OEA
SEL
1
G1
A1
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data
input’s last state preventing “floating” inputs and eliminating the
need for pullup/down resistors.
28
8
C1
23
1
1
1D
1B1
C1
6
1D
2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
1
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type
Latch with 3-State Outputs
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Truth Tables(1)
Product Pin Description
Pin Name
OE
SEL
LE
A,1B,2B
A,1B,2B
GND
VDD
Description
Output Enable Input (Active LOW)
Select
Latch Enable
Data Inputs
3-State Outputs
Ground
Power
B to A (OEB = H)
Inputs
1B
H
L
X
X
X
X
X
Product Pin Configuration
OEA
LE1B
2B3
GND
2B2
2B1
VDD
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VDD
1B1
1B2
GND
1B3
LE2B
SEL
1
2
56
55
3
4
5
54
53
52
6
7
8
51
50
49
9
10
48
47
11
12
13
56-Pin 46
A, K 45
44
14
15
16
43
42
41
17
18
40
19
20
38
37
21
36
22
23
35
24
39
34
33
26
32
31
27
28
30
29
25
OE2B
LEA2B
2B4
GND
2B5
2B6
VDD
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VDD
1B6
1B5
GND
1B4
LEA1B
OE1B
2B
X
X
X
H
L
X
X
Output
A
SEL LE1B LE2B OEA
H
H
X
L
H
H
X
L
H
L
X
L
L
X
H
L
L
X
H
L
L
X
L
L
X
X
X
H
H
L
A0
H
L
A0
Z
A to B (OEA = H)
INPUTS
OUTPUTS
A
LEA1B
LEA2B
O E1B
O E2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
2B0
L
H
L
L
L
L
2B0
H
L
H
L
L
1B0
H
L
L
H
L
L
1B0
L
X
L
L
L
L
1B0
2B0
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
Note:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
2
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................ –0.5V to 4.6V
Output Voltage Range, VO (3-Stated) .............................. –0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ........................................ –50mA
DC Output Diode Current (IOK)
VO < 0V ................................................................................... –50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) ........................... –4/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
Operating
1.65
3.6
Data Retention Only
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
Output voltage
Output current in IOH/IOL
∆t/∆v
TA
0.8
–0.3
3.6
Active State
0
VDD
Off State
0
3.6
VDD =
VDD =
VDD =
VDD =
Operating free- air temperature
V
–32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
Units
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type
Latch with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VO H
Input Clamp Diode
HIGH Level Output Voltage
Conditions
VD D
IIK = −18mA
3.0
2.7 - 3.6
VDD – 0.2
IO H = −12mA
2.7
2.2
IO H = −18mA
M ax.
3.0
2.2
2.0
IO L = 100µA
2.7 - 3.6
0.2
IO L = 12mA
2.7
0.4
IO L = 18mA
IO L = 24mA
0.45
3.0
0.5
IO L = 64mA
0.55
II
Input Leakage Current
VI = VDD, or GND
3.6
±5.0
IO Z
3- State Output Leakage
VO = 3.6V
2.7
±10
IO FF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
IDD
∆IDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IO L = 32mA
IHO LD
Units
2.4
IO H = −32mA
LOW Level Output Voltage
Typ.
–1.2
IO H = −100µA
IO H = −24mA
VO L
M in.
3.6
VI = VDD or GND
75
–75
µA
±500
50
VDD ≤ (VI,VO ) ≤ 3.6V
VIH = VDD –0.6V,
Other inputs at VDD or Gnd
4
2.7 - 3.6
±50
400
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100µA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100µA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
2.3
0.5
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
2.5
VI = 1.7V
VI = VDD or GND
VDD ≤ (VI,VO) ≤ 3.6V
VIH = VDD –0.6V,
Inputs at VDD or Gnd
90
–90
40
2.3 - 2.7
µA
µA
±40
400
Note:
1. Not Guaranteed
5
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type
Latch with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (1.65V ≤ VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
IIK = –18mA
VDD
M in.
Typ.
1.65
IOH = –100µA
1.65- 1.95
IOH = –6mA
M ax.
–1.2
VDD –0.2
1.4
IOL = 100µA
V
1.65
0.2
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
Units
1.65
VI = 1.3
VI = VDD or GND
50
µA
–50
20
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
6
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
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Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figure 1 thru 4
VDD = 1.8V ± 0.15V
M in.
VDD = 2.5V ± 0.2V
M ax.
M in.
M ax.
VDD = 3.3V ± 0.3V
M in.
tw
Pulse duration, LE1B, LE2B,
LEA1B, or LEA2B High
3.3
3.3
tsu
Setup time, data before LE1B,
LE2B, LEA1B, or LEA2B
1.0
1.0
th
Hold time, data after LE1B,
LE2B, LEA1B, or LEA2B
1.0
1.0
M ax.
Units
ns
Switching Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figure 1 thru 4
Parame te r
From
(Input)
To
(Output)
A or B
VDD = 1.8V ±0.15V
M ax.
VDD = 3.3V ±0.3V
M in.
M ax.
M in.
M ax.
B or A
1.0
5.3
1.0
4.6
LE
A or B
1.1
6.0
1.1
4.6
SEL
A
1.6
4.5
1.6
3.4
ten
OE
A or B
1.6
5.0
1.6
4.0
tdis
OE
A or B
2.2
6.5
2.2
5.0
tpd
M in.
VDD = 2.5V ±0.2V
Units
ns
Operating Characteristics, TA = 25ºC
Parame te r
VDD = 2.5V
±0.2V
Te s t Conditions
VDD = 3.3V
±0.3V
Units
Typical
Cpd Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
CL = 50pF,
f = 10 MHz
7
TBD
TBD
TBD
TBD
pF
PXXXX
04/11/00
ADVANCE INFORMATION
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type
Latch with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Open
30pF
CL
RL
500Ω
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
GND
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
1.8V VDD
2 x VDD
VDD
High-Low-High
Pulse
R1
1kΩ
From Output
Under Test
VDD/2
0V
Open
30pF
CL
RL
1kΩ
GND
Propagation Delay
(See Note A)
VDD
VDD/2
0V
Input
tPLH
Setup, Hold, and Release Timing
Data
Input
tSU
Timing
Input
tH
tPHL
VDD
VDD/2
VOL
Output
tPHL
VDD
VDD/2
0V
tPLH
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
Enable Disable Timing
VDD
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one transition per
measurement.
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
VOL
tPHZ
-0.15V
VOH
VDD/2
0V
(see Note B)
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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