PI74ALVCT16260 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs Product Features Product Description • • • • • Pericom Semiconductor’s PI74ALVCT series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. PI74ALVCT16260 is designed for low voltage operation VCC = 2.3V to 3.6V 5V tolerant inputs and outputs Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C • Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C • Industrial operation at 40°C to +85°C • Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCT16260 is a 12-bit to 24-bit multiplexed D-type latch designed for 2.3V to 3.6 Vcc operation. It is used in applications where two separate datapaths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demulti-plexing address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is HIGH, the latch is transparent. When the latch-enable input goes LOW, the data present at the inputs is latched and remains latched until the latch-enable input is returned HIGH. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram LE1B LE2B LEA1B LEA2B OE2B 2 27 30 55 The ALVCT16260 can be driven from either 3.3V or 5V devices allowing it to be used in mixed 3V/5V systems. 56 29 OE1B OEA SEL 1 28 G1 A1 8 C1 23 1 1 1D 1B1 C1 6 1D 2B1 C1 1D C1 1D TO 11 OTHER CHANNELS 1 PS8131A 03/17/98 PI74ALVCT16260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Name OE SEL LE A,1B,2B A,1B,2B GND VCC Truth Tables(1) Description Output Enable Input (Active LOW) Select Latch Enable Data Inputs 3-State Outputs Ground Power B to A (OEB = H) Inputs Product Pin Configuration OEA LE1B 1 2 56 55 OE2B 2B3 3 4 2B2 5 54 53 52 2B4 GND 2B1 6 VCC A1 7 8 56-PIN 51 V56 50 A56 49 2B6 VCC 48 47 2B8 A3 9 10 GND 11 A4 12 13 46 45 GND 2B10 A2 LEA2B 2B12 41 1B11 17 18 40 39 1B10 GND 19 20 21 38 37 36 1B9 1B2 22 23 24 35 34 33 VCC 1B6 1B5 GND 1B3 25 26 32 31 GND LE2B 27 28 30 29 LEA1B GND A10 A11 A12 VCC 1B1 SEL LE1B LE2B OEA H X H H X L H L X H H X L L X X H L X L A0 X H L X H L H X L L X H L L X X L X L L A0 X X X X X H Z Inputs A 2B9 2B11 A9 SEL A to B (OEA = H) 2B7 43 42 A8 2B 2B5 44 A7 1B GND 14 15 16 A5 A6 Output A 1B12 1B8 1B7 1B4 2 LEA1B LEA2B OE1B OE2B 1B 2B H H H L L H H L H H L L L L H H L L L H 2B0 L H L L L L 2B0 H L H L L 1B0 H L L H L L 1B0 L X L L L L 1B0 2B0 X X X H H Z Z X X X L H Active Z X X X H L Z Active X X X L L Active Active Note: 1. H = L = X = Z = OE1B Outputs High Signal Level Low Signal Level Irrelevant High Impedance PS8131A 03/17/98 PI74ALVCT16260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65°C to +150°C Ambient Temperature with Power Applied ........................ 40°C to +85°C Input Voltage Range, VIN ...................................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... 0.5V to VCC +0.5V DC Input Voltage .................................................................... 0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%) Te s t Conditions (1) D e s cription VCC Supply Voltage VIH(3) Input HIGH Voltage VIL(3) Input LO W Voltage VIN(3) Input Voltage 0 5.5 VOUT(3) O utput Voltage 0 5.5 VOH VOL IOH(3) IOL(3) O utput HIGH Voltage O utput LO W Voltage O utput HIGH Current O utput LO W Current M in. Typ.(2) Parame te rs M ax. 2.3 3.6 VCC = 2.3V to 2.7V 1.7 5.5 VCC = 2.7V to 3.6V 2.0 5.5 VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 IOH = - 100mA, VCC = Min. to Max. VCC - 0.2 VIH = 1.7V, IOH = - 6mA, VCC = 2.3V 2.0 VIH = 1.7V, IOH = - 12mA, VCC = 2.3V 1.7 VIH = 2.0V, IOH = - 12mA, VCC = 2.7V 2.2 VIH = 2.0V, IOH = - 12mA, VCC = 3.0V 2.4 VIH = 2.0V, IOH = - 24mA, VCC = 3.0V 2.0 V IOL = 100mA, VIL = Min. to Max. 0.2 VIL = 0.7V, IOL = 6mA, VCC = 2.3V 0.4 VIL = 0.7V, IOL = 12mA, VCC = 2.3V 0.7 VIL = 0.8V, IOL = 12mA, VCC = 2.7V 0.4 VIL = 0.8V, IOL = 24mA, VCC = 3.0V 0.55 VCC = 2.3V - 12 VCC = 2.7V - 12 VCC = 3.0V - 24 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 3 Units mA PS8131A 03/17/98 PI74ALVCT16260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics-Continued (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%) Te s t Conditions (1) Parame te rs De s cription M in. Typ.(2) M ax. IIN Input Current VIN = VCC or GND, VCC = 3.6V 5 IOZ Output Current (3- STATE Outputs) VOUT = 5.5V or GND ±10 ICC Supply Current VCC = 3.6V, IOUT = 0mA, VIN = GND or VCC 40 DICC Supply Current per Input @ TTL HIGH VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND 750 CI Control Inputs VIN = VCC or GND, VCC = 3.3V 3.5 CIO Outputs VO = VCC or GND, VCC = 3.3V 9 Units mA pF Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. Timing Requirements over Operating Range Parame te rs De s cription VCC = 2.5V ± 0.2V M in. M ax. VCC = 2.7V M in. M ax. VCC = 3.3V ± 0.3V M in. tW Pulse duration, LE1B, LE2B, LEA1B, or LEA2B HIGH 3.3 3.3 3.3 tSU Setup time data before LE1B, LE2B, LEA1B, or LEA2B 1.4 1.1 1.1 tH Hold time data after LE1B, LE2B, LEA1B, or LEA2B 1.6 1.9 1.5 Dt/Dv(1) Input Transition Rise or Fall 0 10 0 10 0 M ax. Units ns 10 ns/v Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 4 PS8131A 03/17/98 PI74ALVCT16260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics Over Operating Range(1) Parame te rs tPD VCC = 2.7V VCC = 2.5V ± 0.2V From To (INPUT) (OUTPUT) M in.(2) M ax. M in.(2) M ax. VCC = 3.3V ± 0.3V M in.(2) M ax. A or B B or A 1.2 6.0 5.1 1.2 4.9 LE A or B 1.0 6.2 5.2 1.0 5.0 SEL A 1.2 7.5 6.6 1.1 5.6 1.0 7.2 6.4 1.0 5.4 1.7 5.9 5.0 1.3 4.6 tEN OE tDIS OE A or B Units ns Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25ºC Parame te r CPD Power Dissipation Capacitance O utputs Enabled O utputs Disabled VCC = 2.5V ± 0.2V Te s t Conditions VCC = 3.3V ± 0.3V Typical CL = 50pF, f = 10 MHz 5 87 120 80.5 118 Units pF PS8131A 03/17/98