(Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO FEATURES 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GNDBUF SEL2^ 4 13 QBAR OE_CTRL 5 12 VDDBUF DNC 6 11 Q GNDANA 7 10 GNDBUF LP 8 9 LM SEL2^ 14 OE_CTRL 15 DNC 16 SEL0^ SEL1^ 11 10 9 PL680-3X 1 2 3 4 LM The PL680-3X is a monolithic low jitter and low phase noise high performance clock, capable of maintaining 0.4ps RMS phase jitter and CMOS, LVDS or PECL outputs, covering a wide frequency output range up to 640MHz. It allows high performance and high frequency output, using a low cost fundamental crystal of between 19-40MHz.. The frequency selector pads of PL680-3X enable output frequencies of (2, 4, 8, or 16) * F XIN . The PL680-3X is designed to address the demanding requirements of high performance applications such Fiber Channel, serial ATA, Ethernet, SAN, etc. 12 13 GNDBUF DESCRIPTION XOUT VDDANA 16-pin TSSOP XIN • • • • • • 1 PL680-3X • VDDANA LP • Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies . Less than 25ps peak to peak jitter for all frequencies. Low phase noise output (@ 1MHz frequency offset ∗ -144dBc/Hz for 106.25MHz ∗ -144dBc/Hz for 156.25MHz ∗ -144dBc/Hz for 212.5MHz ∗ -140dBc/Hz for 312.5MHz, ∗ -131dBC/Hz for 622.08MHz 19MHz-40MHz crystal input. 38MHz-640MHz output. Available in PECL, LVDS, or CMOS outputs. Output Enable selector. 2.5V & 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages. GNDANA • PACKAGE PIN ASSIGNMENT 8 GNDBUF 7 QBAR 6 VDDBUF 5 Q 3x3 QFN Note1: QBAR is used for single ended CMOS output. Note2: ^ Denotes internal pull up resistor. BLOCK DIAGRAM VCO Divider XIN XOUT XTAL OSC Phase Detector Charge Pump + Loop Filter VCO (F XiN x16) Performance Tuner Output Divider (1,2,4,8) QBAR Q OE 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO OUTPUT ENABLE LOGICAL LEVELS Part # PL680-38 (PECL) PL680-37 & 39 (CMOS or LVDS) OE State 0 (Default) Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled PIN DESCRIPTIONS TSSOP Pin number 3x3mm QFN Pin number Type VDDANA 1 11 P VDD for analog Circuitry. XIN 2 12 I Crystal input pin. (See Crystal Specifications on page 3). XOUT 3 13 O Crystal output pin. (See Crystal Specifications on page 3). SEL2 4 14 I Output frequency Selector pin. OE_CTRL 5 15 I Output enable control pin. (See OE_CTRL Logic Levels on page 1). DNC 6 16 - Do Not Connect GNDANA 7 1 P Ground for analog circuitry. LP 8 2 - LM 9 3 - GNDBUF 10 4 P GND connection for output buffer circuitry. Q 11 5 O PECL or LVDS output. VDDBUF 12 6 P VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. QBAR 13 7 O Complementary PECL, LVDS output; Or single ended CMOS output. GNDBUF 14 8 P GND connection for output buffer circuitry. SEL1 15 9 I Output frequency Selector pin. SEL0 16 10 I Output frequency Selector pin. Name Description Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency 0 0 0 VCO Max* 0 0 1 VCO Min* 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Fin x 2 1 0 1 Fin x 8 1 1 0 Fin x 16 1 1 1 Fin x 4 All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values. In addition, the chart below could be used as a reference for quick inductor value selection. Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Shunt Capacitance Recommended ESR SYMBOL CONDITIONS MIN. F XIN C L (xtal) C 0 (xtal) RE Parallel Fundamental Mode 19 TYP. MAX. UNITS 40 MHz pF pF 17.7 5 30 AT cut Ω Note: Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain. 3. General Electrical Specifications PARAMETERS Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle SYMBOL I DD CONDITIONS MIN. TYP. MAX. PECL/LVDS/CMOS 38MHz<Fout<320MHz 65/45/30 PECL/LVDS 320MHz<Fout<640MHz 90/70 V DD @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Short Circuit Current 2.25 45 45 45 50 50 50 ±50 3.63 55 55 55 UNITS mA V % mA Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO 4. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY Integrated jitter RMS Integrated 12 kHz to 20 MHz Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Period jitter Peak-toPeak MIN. TYP. MAX. 106.25MHz 156.25MHz 212.5MHz 312.5MHz 622.08MHz 106.25MHz 156.25MHz 0.4 0.4 0.4 0.4 0.4 3 3 0.5 0.5 0.5 0.5 0.5 5 5 212.5MHz 3 5 312.5MHz 3 5 622.08MHz 106.25MHz 156.25MHz 212.5MHz 6 20 20 20 8 30 30 30 312.5MHz 20 30 622.08MHz 40 50 UNITS ps ps ps 5. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier (typical) FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M 106.25MHz -66 -96 -122 -132 -126 -144 -150 156.25MHz -62 -92 -120 -132 -128 -140 -150 212.5MHz -62 -92 -118 -126 -120 -140 -150 312.5MHz -59 -85 -117 -128 -125 -139 -148 622.08MHz -49 -84 -111 -120 -118 -128 -138 MIN. TYP. MAX. UNITS dBc/Hz 6. CMOS Electrical Characteristics PARAMETERS Output drive current SYMBOL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V 30 30 UNITS mA mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 0.7 ns Output Clock Rise/Fall Time 20%-80% with 50Ω Load 0.3 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL FREQ. Clock Rise & Fall Times tr & tf Clock Rise & Fall Times CONDITIONS MIN. TYP. MAX. <150MHz 0.2 0.5 0.7 >150MHz <320MHz 0.2 0.4 0.55 0.2 0.3 0.45 Clock Rise & Fall Times PECL Levels Test Circuit OUT ns PECL Output Skew OUT VDD 50Ω UNITS 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO LAYOUT RECOMMENDATIONS PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL680 as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL680 layout. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO PACKAGE INFORMATION 16-PIN SSOP 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 16-PIN 3x3 QFN 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 9 (Preliminary) PL680-37/38/39 38-640MHz Low Phase Noise XO ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL680-3X X C L R PART NUMBER R= TAPE & REEL NONE= TUBE L= GREEN PACKAGE NONE= REGULAR PACKAGE PACKAGE TYPE O=TSSOP Q= QFN 4x4 Order Number PL680-37OC PL680-37OC-R PL680-37OCL PL680-37OCL-R PL680-37QC PL680-37QC-R PL680-37QCL PL680-37QCL-R PL680-38OC PL680-38OC-R PL680-38OCL PL680-38OCL-R PL680-38QC PL680-38QC-R PL680-38QCL PL680-38QCL-R PL680-39OC PL680-39OC-R PL680-39OCL PL680-39OCL-R PL680-39QC PL680-39QC-R PL680-39QCL PL680-39QCL-R TEMPERATURE C=COMMERCIAL I=INDUSTRAL Marking Marking P680-37OC P680-37OC P680-37OCL P680-37OCL P680-37QC P680-37QC P680-37QCL P680-37QCL P680-38OC P680-38OC P680-38OCL P680-38OCL P680-38QC P680-38QC P680-38QCL P680-38QCL P680-39OC P680-39OC P680-39OCL P680-39OCL P680-39QC P680-39QC P680-39QCL P680-39QCL TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) TSSOP - Tube TSSOP - Tape & Reel TSSOP - Tube (GREEN Package) TSSOP - Tape & Reel (GREEN Package) QFN - Tube QFN - Tape & Reel QFN - Tube (GREEN Package) QFN - Tape & Reel (GREEN Package) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 10