PLL PLL502

Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
FEATURES
•
•
•
•
•
Low phase noise output for the 384MHz to
768MHz range (-130 dBc at 10kHz offset).
PECL output.
12 to 24MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
Wide pull range (+/-180 ppm)
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-21 is a monolithic low jitter and low
phase noise (-130dBc/Hz @ 10kHz offset) VCXO IC
with PECL output, for 384MHz to 768MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
F XIN x 32. This makes the PLL502-21 ideal for a wide
range of applications, including 622.08MHz for
SONET.
VDD
1
16
VDD
VDD
2
15
GND_BUF
XIN
3
14
CLKBAR
XOUT
4
13
VDD_BUF
OE
5
12
CLK
VIN
6
11
GND_BUF
GND
7
10
GND
GND
8
9
GND
PLL 502-21
•
•
•
PIN CONFIGURATION
F OUT = F XIN x 32
OE (Pin 5)
0 (Default)
1
Output State
Output enabled
Tri-state
Pin 5: Logical states are defined at PECL levels.
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
XIN
XOUT
XTAL
OSC
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
OE
VARICAP
VIN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/10/01 Page 1
Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD
1,2,16
P
+3.3V Power supply connectors.
XIN
3
I
Crystal input pin.
XOUT
4
I
Crystal output pin.
OE
5
I
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
VIN
6
I
Frequency control voltage input pin.
GND
7,8,9,10
P
GND Power connectors.
GND_BUF
11,15
P
GND connector for output buffers.
CLK
12
O
True clock output pin.
VDD_BUF
13
P
+3.3V Power supply connector for output buffers.
CLKB
14
O
Complementary clock output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
SYMBOL
MIN.
V DD
MAX.
UNITS
7
V
Input Voltage, dc
VI
V SS - 0.5
V DD + 0.5
V
Output Voltage, dc
VO
V SS - 0.5
V DD + 0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature
TA
0
70
°C
Junction Temperature
TJ
125
°C
260
°C
2
kV
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/10/01 Page 2
Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
2. Crystal Specifications
PARAMETERS
SYMBOL
Crystal Resonator
Frequency
Crystal Loading Rating
Crystal Pullability
CONDITIONS
MIN.
Parallel Fundamental
Mode
F XIN
TYP.
12
MAX.
UNITS
24
MHz
TBD
C L (xtal)
pF
C 0 /C 1 (xtal)
AT cut
250
-
RE
AT cut
30
Ω
Recommended ESR
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
SYMBOL
T VCXOSTB
Output Frequency Synthesis
Error
CONDITIONS
MIN.
From power valid
TYP.
10
(Unless otherwise noted in
Frequency Table)
F XIN = 12 - 24MHz;
VCXO Tuning Range
XTAL C 0 /C 1 < 250
CLK output pullability
0V ≤ VCON ≤ 3.3V
MAX.
UNITS
ms
±30
ppm
380
ppm
±190
ppm
Linearity
5
VCXO Tuning Characteristic
10
115
%
ppm/V
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current, Dynamic
(with Loaded Outputs)
I DD
Operating Voltage
V DD
Output Clock Duty Cycle
CONDITIONS
MIN.
TYP.
PECL
3.13
@ Vdd – 1.3V (PECL)
Short Circuit Current
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
45
50
±50
MAX.
UNITS
80
mA
3.47
V
55
%
mA
Rev 08/10/01 Page 3
Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
5. Jitter and Phase Noise specification
PARAMETERS
CONDITIONS
Phase Noise relative to carrier
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
622MHz @100Hz offset
Phase Noise relative to carrier
Period jitter RMS
MIN.
TYP.
MAX.
UNITS
7
ps
11
ps
-80
dBc/Hz
622MHz @1kHz offset
-109
dBc/Hz
Phase Noise relative to carrier
622MHz @10kHz offset
-130
dBc/Hz
Phase Noise relative to carrier
622MHz @100kHz offset
-132
dBc/Hz
Accumulated jitter RMS
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/10/01 Page 4
Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
6. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
Output High Voltage
V OH
V DD – 1.025
Output Low Voltage
V OL
R L = 50 Ω to (V DD – 2V)
(see figure)
MAX.
UNITS
V
V DD – 1.620
V
7. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
tr
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
tf
@80/20% - PECL
0.5
1.5
ns
PECL Levels Test Circuit
OUT
PECL Output Skew
VDD
50Ω
OUT
2.0V
50%
50Ω
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/10/01 Page 5
Preliminary
PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC
TSSOP
Symbol
Min.
Max.
Min.
Max.
A
1.35
1.75
-
1.20
A1
0.10
0.25
0.05
0.15
B
0.33
0.51
0.19
0.30
C
0.19
0.25
0.09
0.20
D
9.80
10.00
4.90
5.10
E
3.80
4.00
4.30
H
5.80
6.20
L
0.40
e
E
H
D
4.50
6.40 BSC
1.27
0.45
1.27 BSC
0.75
A
A1
C
0.65 BSC
L
B
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-21 S C XX
PART NUMBER
REVISION CODE
(when applicable)
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/10/01 Page 6