PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s FEATURES 1 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GND SEL3^ 4 13 CLKC SEL2^ 5 12 VDD OE 6 11 CLKT VCON 7 10 GND GND 8 9 GND VDD / GND* SEL0^ / VDD* SEL1^ 12 11 10 9 DESCRIPTION ^: *: BLOCK DIAGRAM X+ X- 14 SEL2^ 15 OE 16 P502-3x 1 2 3 4 GND SEL3^ GND 13 8 GND 7 CLKC 6 VDD 5 CLKT Internal pull-up On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin 10), and pin11 is VDD. See pin assignment table for details. OUTPUT ENABLE LOGICAL LEVELS SEL Vin XOUT VCON The PLL502-35 (PECL with inverted OE), PLL502-37 (CMOS), PLL502-38 (PECL), and PLL502-39 (LVDS) are high performance and low phase noise VCXO IC chips. They provide phase noise performance as low as –125dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The wide pull range (+/- 200 ppm) and very low jitter make them ideal for a wide range of applications, including SONET/SDH and FEC. They accept fundamental parallel resonant mode crystals from 12 to 25MHz. GND • • • • • • • VDD PLL 502-3x • Selectable 750kHz to 800MHz range. Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). CMOS (PLL502-37), PECL (PLL502-35 and PLL502-38) or LVDS (PLL502-39) output. 12 to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (+/-200 ppm) Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN). XIN • • PIN CONFIGURATION (Top View) Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) OE Part # Q PLL502-38 Q PLL by-pass PLL502-3x PLL502-35 PLL502-37 PLL502-39 OE 0 (Default) State Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL502-38 Logical states defined by CMOS levels for PLL502-37/-39 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 1 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always “1”) for PLL502-35 and PLL502-38 in 3x3mm package PIN DESCRIPTIONS PLL502-35 and PLL502-38 (see next page of PLL502-37/-39) Name XIN XOUT OE VCON GND CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD TSSOP Pin number 2 3 6 7 8,9,10,14 11 13 16 15 5 4 1, 12 3x3mm QFN Pin number 12 13 16 1 2,3,4,8,11 5 7 Not available 9 15 14 6,10 Type I I I I P O O I I I I P Description Crystal input. See Crystal Specification on page 4. Crystal output. See Crystal Specification on page 4. Output enable pin (see OE logic state table on page 1). Voltage Control input. Ground. True output PECL Complementary output PECL. Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 2 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s PIN DESCRIPTIONS PLL502-37/-39 (see previous page of PLL502-35/-38) Name TSSOP Pin number 3x3mm QFN Pin number Type XIN XOUT OE VCON GND 2 3 6 7 8,9,10,14 12 13 16 1 2,3,4,8 I I I I P CLKT 11 5 O CLKC 13 7 O SEL0 SEL1 SEL2 SEL3 VDD 16 15 5 4 1, 12 10 9 15 14 6,11 I I I I P Description Crystal input. See Crystal Specification on page 4. Crystal output. See Crystal Specification on page 4. Output enable pin (see OE logic state table on page 1). Voltage Control input. Ground. True output LVDS (PLL502-39) (N/C for PLL502-37) Complementary output LVDS (PLL502-39) (CMOS out for PLL502-37). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 3 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. F XIN C L (xtal) C 0 /C 1 (xtal) RE Parallel Fundamental Mode At VCON = 1.65V AT cut AT cut 12 TYP. MAX. UNITS 25 MHz pF - 9.5 250 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL VCXO Stabilization Time * T VCXOSTB VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW CONDITIONS From power valid F XIN = 12 – 25MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V MIN. TYP. MAX. UNITS 10 ms 500 ppm 150 ppm ppm/V % ±200 10 0V ≤ VCON ≤ 3.3V, -3dB 2000 25 kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD Output Clock Duty Cycle Short Circuit Current CONDITIONS PECL/LVDS/CMOS MIN. TYP. MAX. 50 50 50 60/28/15 65/45/30 100/80/40 3.63 55 55 55 Fout<24MHz 24MHz<Fout<96MHz 96MHz<Fout<800MHz 2.97 @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) 45 45 45 ±50 UNITS mA V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 4 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 5. Jitter Specifications PARAMETERS Period jitter RMS Period jitter Peak-toPeak 1 Integrated jitter RMS 2 CONDITIONS FREQUENCY With capacitive decoupling between VDD and GND. Over 10,000 cycles. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz MIN. TYP. 19.44MHz 77.76MHz 2.2 4.5 155.52MHz 4.5 622.08MHz 5.0 19.44MHz 77.76MHz 17 25 155.52MHz 27 622.08MHz 35 155.52MHz 622.08MHz 2.5 2.5 MAX. UNITS ps ps 4 4 ps 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 19.44MHz 77.76MHz 155.52MHz 622.08MHz -80 -72 -65 -55 -108 -103 -95 -85 -132 -122 -120 -109 -142 -130 -125 -115 -150 -125 -121 -110 dBc/Hz Phase Noise relative to carrier (typical) Note: Phase Noise measured at VCON = 0V 7. CMOS Electrical Characteristics PARAMETERS Output drive current Output Clock Rise/Fall Time SYMBOL CONDITIONS MIN. I OH I OL V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V 0.3V ~ 3.0V with 15 pF load 10 10 TYP. 2.4 MAX. UNITS mA mA ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 5 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage V OS CONDITIONS 1.4 R L = 100 Ω (see figure) ∆V OS Offset Magnitude Change Power-off Leakage I OXD Output Short Circuit Current I OSD 0.9 1.1 1.125 1.2 1.375 V 0 3 25 mV ±1 ±10 uA -5.7 -8 mA V out = V DD or GND V DD = 0V V 9. LVDS Switching Characteristics PARAMETERS SYMBOL Differential Clock Rise Time tr Differential Clock Fall Time tf CONDITIONS MIN. TYP. MAX. UNITS R L = 100 Ω 0.2 0.7 1.0 ns 0.2 0.7 1.0 ns C L = 10 pF (see figure) LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 6 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr 20%~80% of Waveform 0.6 1.5 ns Clock Fall Time tf 20%~80% of Waveform 0.6 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew OUT VDD 50Ω 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 7 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s PACKAGE INFORMATION 16 Pin TSSOP Dimensions in ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e L B 16 Pin 3x3 QFN D A AA E e L b Symbol A A1 b D E e L Dimension in MM Min. Max. 0.70 0.80 0.203 REF 0.18 0.30 2.90 3.10 2.90 3.10 0.50 BSC 0.30 0.50 Dimension in inch Min. Max. 0.028 0.032 0.008 REF 0.007 0.012 0.114 0.122 0.114 0.122 0.020 BSC 0.012 0.020 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 8 PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type, Operating temperature range, shipping method PLL502-3x X X X -R NONE= TUBE -R=TAPE AND REEL PART NUMBER NONE=NORMAL PACKAGE L=GREEN PACKAGE TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE O=TSSOP Q=QFN Order Number Marking Package Option PLL502-35OC PLL502-35OC-R PLL502-35QC PLL502-35QC-R PLL502-35OCL PLL502-35OCL-R PLL502-35QCL PLL502-35QCL-R P502-35OC P502-35OC P502-35QC P502-35QC P502-35OCL P502-35OCL P502-35QCL P502-35QCL 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PLL502-37OC PLL502-37OC-R PLL502-37QC PLL502-37QC-R PLL502-37OCL PLL502-37OCL-R PLL502-37QCL PLL502-37QCL-R P502-37OC P502-37OC P502-37QC P502-37QC P502-37OCL P502-37OCL P502-37QCL P502-37QCL 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PLL502-38OC PLL502-38OC-R PLL502-38QC PLL502-38QC-R PLL502-38OCL PLL502-38OCL-R PLL502-38QCL PLL502-38QCL-R P502-38OC P502-38OC P502-38QC P502-38QC P502-38OCL P502-38OCL P502-38QCL P502-38QCL 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PLL502-39OC PLL502-39OC-R PLL502-39QC PLL502-39QC-R PLL502-39OCL PLL502-39OCL-R PLL502-39QCL PLL502-39QCL-R P502-39OC P502-39OC P502-39QC P502-39QC P502-39OCL P502-39OCL P502-39QCL P502-39QCL 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 9