RF1K49221
Data Sheet
January 2002
2.5A, 60V, 0.130 Ohm, ESD Rated, Dual
N-Channel LittleFET™ Power MOSFET
Features
• 2.5A, 60V
The RF1K49221 Dual N-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.
• rDS(ON) = 0.130Ω
• 2kV ESD Protected
• Temperature Compensating PSPICE® Model
• Thermal Impedance PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
The RF1K49221 incorporates ESD protection and is
designed to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49221.
Symbol
Ordering Information
PART NUMBER
RF1K49221
PACKAGE
MS-012AA
D1(8)
D1(7)
BRAND
RF1K49221
S1(1)
G1(2)
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922196.
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
©2002 Fairchild Semiconductor Corporation
4
RF1K49221 Rev. B
RF1K49221
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . ESD
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RF1K49221
60
60
±20
UNITS
V
V
V
2.5
Refer to Peak Current Curve
Refer to UIS Curve
2
0.016
2
-55 to 150
A
W
W/oC
kV
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, (Figure 12)
60
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, (Figure 11)
1
-
3
V
VDS = 60V,
TA = 25oC
VGS = 0V
TA = 150oC
VGS = ±20V, TA = 25oC
VGS = ±10V, TA = 85oC
-
-
1
µA
-
-
50
µA
-
-
10
µA
-
-
25
µA
ID = 2.5A,
(Figures 9, 10)
VGS = 10V
-
-
0.130
Ω
VGS = 4.5V
-
-
0.350
Ω
-
-
50
ns
-
10
-
ns
-
25
-
ns
td(OFF)
-
68
-
ns
tf
-
32
-
ns
tOFF
-
-
150
ns
-
24
29
nC
-
13
16
nC
-
0.8
1.0
nC
-
365
-
pF
-
140
-
pF
-
40
-
pF
62.5
oC/W
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
VDD = 30V, ID ≅ 2.5A,
RL = 12Ω, VGS = 10V,
RGS = 25Ω,
(Figure 14)
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDD = 48V, ID ≅ 2.5A,
RL = 19.2Ω
Ig(REF) = 1.0mA
(Figure 14)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Pulse Width = 1s
Device mounted on FR-4 material
-
-
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
©2002 Fairchild Semiconductor Corporation
SYMBOL
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 2.5A
-
-
1.25
V
ISD = 2.5A, dISD/dt = 100A/µs
-
-
58
ns
RF1K49221 Rev. B
RF1K49221
1.2
3.0
1.0
2.5
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
2.0
1.5
1.0
0.5
0
0
0
25
125
50
75
100
TA , AMBIENT TEMPERATURE (oC)
75
50
25
150
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
t, RECTANGULAR PULSE DURATION (s)
101
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
10
1
5ms
10ms
100ms
0.1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
0.01
0.1
100
TJ = MAX RATED
TA = 25oC
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
50
VGS = 20V
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
VGS = 10V
= I25
150 - TA
125
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1s
VDSS(MAX) = 60V
1
10
DC
100 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2002 Fairchild Semiconductor Corporation
1
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
RF1K49221 Rev. B
RF1K49221
Typical Performance Curves
(Continued)
20
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
16
VGS = 7V
12
VGS = 6V
8
VGS = 5V
4
VGS = 4.5V
STARTING TJ = 150oC
1
0.1
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
VGS = 8V
VGS = 20V
VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
15
0
1
10
tAV, TIME IN AVALANCHE (ms)
100
0
1.5
3.0
4.5
6.0
7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
25oC
16
-55oC
500
VDD = 15V
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID(ON), ON-STATE DRAIN CURRENT (A)
20
FIGURE 7. SATURATION CHARACTERISTICS
150oC
12
8
4
400
ID = 5.0A
ID = 2.5A
300
ID = 1.25A
ID = 0.625A
200
100
0
0
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
3
10
NORMALIZED GATE
THRESHOLD VOLTAGE
1.0
0.5
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
7
8
9
10
VGS = VDS, ID = 250µA
1.5
0
6
1.2
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 2.5A
-40
5
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
0
-80
4
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 250µs, VDD = 15V
DUTY CYCLE = 0.5% MAX
160
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
RF1K49221 Rev. B
RF1K49221
Typical Performance Curves
(Continued)
500
ID = 250µA
CISS
400
C, CAPACITANCE (pF)
1.1
1.0
0.9
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
300
COSS
200
100
CRSS
0.8
-80
0
-40
0
40
80
120
0
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
5
10
15
20
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
60
10.0
VDD = BVDSS
VDD = BVDSS
45
7.5
RL = 24W
Ig(REF) = 0.30mA
VGS = 10V
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
30
15
5.0
2.5
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
0
0
I g ( REF )
20 -----------------------I g ( ACT )
t, TIME (ms)
I g ( REF )
80 -----------------------I g ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
RF1K49221 Rev. B
RF1K49221
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
10%
0
10%
0V
90%
DUT
RGS
VGS
0
FIGURE 17. SWITCHING TIME TEST CIRCUIT
50%
50%
PULSE WIDTH
10%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
VGS = 10V
VGS
VGS = 2V
IG(REF)
Qg(TH)
Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering
should always be less than 100oC. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
©2002 Fairchild Semiconductor Corporation
3. The maximum temperature gradient should be less than 5oC
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
at least 30 oC higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
RF1K49221 Rev. B
RF1K49221
PSPICE Electrical Model
SUBCKT RF1K49221 2 1 3 ;rev 4/8/97
CA 12 8 5.60e-10
CB 15 14 5.30e-10
CIN 6 8 3.40e-10
LDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
DPLCAP
10
RLDRAIN
DBREAK
11
50
ESG
IT 8 17 1
GATE
1
LGATE
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
EBREAK 17
18
RDRAIN
16
6
8
+
EVTHRES
+ 19
8
EVTEMP
RGATE +
18
9
20 22
21
6
DBODY
MWEAK
MMED
MSTRO
DESD1
91
DESD2
RIN
LSOURCE
CIN
RSOURCE
8
SOURCE
3
7
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 28.58e-3
RGATE 9 20 15.34
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RLDRAIN 2 5 10
RLGATE 1 9 11.2
RLSOURCE 3 7 4.5
RSOURCE 8 7 RSOURCEMOD 28.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
RSLC1
51
+
5
ESLC
51
RSLC2
EBREAK 11 7 17 18 67.29
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 4.50e-10
DRAIN
2
5
S1A
12
13
8
S2A
15
14
13
S1B
RBREAK
18
17
S2B
13
CA
RVTEMP
CB
+
EGS
EDS
IT
14
+
6
8
VBAT
5
8
+
8
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
19
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),2.5))}
.MODEL DBODYMOD D (IS = 1.95e-13 RS = 2.58e-2 TRS1 = 2.00e-3 TRS2 =-4.39e-7 CJO = 5.15e-10 TT = 5.23e-8 M=0.5)
.MODEL DBREAKMOD D (RS = 6.24e- 1TRS1 =-3.03e- 4TRS2 = 4.27e-6
.MODEL DESD1MOD D (BV=32.3 TBV1=0 TBV2=0 RS=0 TRS1=0 TRS2=0
.MODEL DESD2MOD D (BV=32.5 TBV1=0 TBV2=0 RS=25 TRS1=5.18e-4 TRS2=-1.52e-6)
.MODEL DPLCAPMOD D (CJO = 1.80e-1 0IS = 1e-3 0N = 10 M=0.5)
.MODEL MMEDMOD NMOS (VTO=2.755 KP=0.21 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15.34)
.MODEL MSTROMOD NMOS (VTO=3.165 KP=3.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.520 KP=0.040 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=153.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 1.10e- 3TC2 = -1.09e-6)
.MODEL RDRAINMOD RES (TC1 = 1.15e-2 TC2 = 4.09e-5
.MODEL RSLCMOD RES (TC1=3.03e-3 TC2=4.52e-6)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RVTHRESMOD RES (TC=-7.20e-4 TC2=-7.11e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.01e- 3TC2 = 1.81e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.80 VOFF= -4.80)
VON = -4.80 VOFF= -7.80)
VON = 1.10 VOFF= 4.10)
VON = 4.10 VOFF= 1.10)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RF1K49221 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4