INTEGRATED CIRCUITS DATA SHEET SAA9750H Camera Digital Signal Processor (CAMDSP) Preliminary specification File under Integrated Circuits, IC02 1996 Feb 16 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H • Sync Signal Generator (SSG) to generate all necessary timing signals FEATURES • Y/C separator for mosaic filter colour CCD which can be used with PAL or NTSC CCDs with horizontal resolution of 510, 670, 720 or 768 pixels • Serial interface for microprocessor control of CAMDSP settings • Y and C signals accessible to incorporate digital features • Line sequential colour processing (R−Y) and (B−Y) • 9 bit input signal (the internal processing is 10-bit) • Including digital feature functions (mosaic, sepia, solarization, slice and negative/positive inversion). • Digital feedback clamp control for Y/C separation • Two 768 × 9 line memories for Y/C separation • Aperture correction using phase linear filters GENERAL DESCRIPTION • Coring of LOW level signals to reduce noise The Camera Digital Signal Processor (CAMDSP) is intended for use with a mosaic filter colour CCD. The IC generates luminance and chrominance signals from the CCD signal. The device consists of a luminance and colour separator employing two 768 × 9 line memories, a PAL/NTSC encoder, a dual 8-bit video DAC, a Sync Signal Generator (SSG) and a simple serial interface to control many settings. • Colour encoder in accordance with the PAL or NTSC system. Colour subcarrier is made by a discrete time oscillator (DTO) operating on system clock • Slew rate controlled outputs for reduction of digital noise • RGB inputs for title mix • High accuracy 8 bit DAC outputs for luminance and chrominance signals QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA1 Y-DAC analog supply voltage (pin 1) 2.7 3.0 3.3 V VDDA2 C-DAC analog supply voltage (pin 2) 2.7 3.0 3.3 V VDDD1 digital supply voltage (pin 41) 2.7 3.0 3.3 V VDDD2 digital supply voltage (pin 53) 2.7 3.0 3.3 V VDDD3 digital supply voltage (pin 65) 2.7 3.0 3.3 V VIH HIGH level digital input voltage 0.7VDDD − VDDD V VIL LOW level digital input voltage 0 − 0.3VDDD V VOH HIGH level digital output voltage VDDD − 0.5 − − V VOL LOW level digital output voltage − − 0.5 V Tamb operating ambient temperature −20 − +70 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA9750H LQFP80 1996 Feb 16 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm 2 VERSION SOT315-1 21 to 28 20 29 41 R B WCLIP TSW G LSW VDDA1 VDDA2 1 2 8 9 10 11 7 8 SAA9750H CPOB CLAMP 68 to 76 UVENC X2H X0H 9 FIFO 768 × 9 CLAMP 62 X1H + FIFO 768 × 9 61 CLAMP settings Y settings C settings 3 CS CK DI 30 31 32 VRST HRST CLK1 CLK2 51 52 66 67 MICROPROCESSOR INTERFACE 54 42 3 A D 5 YENC COUT VrefC 8 12 to 19 UVENC0 to UVENC7 8 43 to 50 YENC7 to YENC0 Y PROCESSING title mix 8 ENCODER settings DELAY sync SSG settings A 80 D 78 YOUT VrefY SYNC SIGNAL GENERATOR CLOCK 64 8 title mix TITLE SWITCH 8 77 6 59 55 56 63 57 58 33 to 40 VSSD2 VSSD3 VSSD1 TEST1 TEST2 CSYNC HD FLD Y0 to Y7 VD CP2 HSYNC SYNCI 4 VSSA1 79 MHA302 VSSA2 Preliminary specification Fig.1 Block diagram. 60 SAA9750H handbook, full pagewidth CDS0 to CDS8 ENCODER C PROCESSING Philips Semiconductors 53 UV0 to UV7 UVSEL Camera Digital Signal Processor (CAMDSP) 65 VDDD3 VDDD1 BLOCK DIAGRAM 1996 Feb 16 VDDD2 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H PINNING SYMBOL PIN INPUT/OUTPUT ANALOG/DIGITAL DESCRIPTION VDDA1 1 supply − analog supply voltage 1 for Y-DAC VDDA2 2 supply − analog supply voltage 2 for C-DAC COUT 3 output analog C-DAC output VSSA1 4 supply − analog ground 1 for C-DAC VrefC 5 − − C-DAC decoupling voltage TEST2 6 input digital test 2 pin LSW 7 input digital line switch for SECAM TSW 8 input digital title memory switch R 9 input digital title memory colour (red) G 10 input digital title memory colour (green) B 11 input digital title memory colour (blue) UVENC0 12 input digital B−Y and R−Y signal to encoder (LSB) UVENC1 13 input digital B−Y and R−Y signal to encoder UVENC2 14 input digital B−Y and R−Y signal to encoder UVENC3 15 input digital B−Y and R−Y signal to encoder UVENC4 16 input digital B−Y and R−Y signal to encoder UVENC5 17 input digital B−Y and R−Y signal to encoder UVENC6 18 input digital B−Y and R−Y signal to encoder UVENC7 19 input digital B−Y and R−Y signal to encoder (MSB) WCLIP 20 output digital white-clip UV7 21 output digital time multiplexed B−Y and R−Y (MSB) UV6 22 output digital time multiplexed B−Y and R−Y UV5 23 output digital time multiplexed B−Y and R−Y UV4 24 output digital time multiplexed B−Y and R−Y UV3 25 output digital time multiplexed B−Y and R−Y UV2 26 output digital time multiplexed B−Y and R−Y UV1 27 output digital time multiplexed B−Y and R−Y UV0 28 output digital time multiplexed B−Y and R−Y (LSB) UVSEL 29 output digital B−Y or R−Y active at UV output CS 30 input digital microprocessor interface (chip select) CK 31 input digital microprocessor interface (clock) DI 32 input digital microprocessor interface (data input) Y0 33 output digital luminance signal (LSB) Y1 34 output digital luminance signal Y2 35 output digital luminance signal Y3 36 output digital luminance signal Y4 37 output digital luminance signal Y5 38 output digital luminance signal Y6 39 output digital luminance signal Y7 40 output digital luminance signal (MSB) 1996 Feb 16 4 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SYMBOL SAA9750H PIN INPUT/OUTPUT ANALOG/DIGITAL DESCRIPTION VDDD1 41 supply − digital supply voltage 1 VSSD1 42 supply − digital ground 1 YENC7 43 input digital luminance signal to encoder (MSB) YENC6 44 input digital luminance signal to encoder YENC5 45 input digital luminance signal to encoder YENC4 46 input digital luminance signal to encoder YENC3 47 input digital luminance signal to encoder YENC2 48 input digital luminance signal to encoder YENC1 49 input digital luminance signal to encoder YENC0 50 input digital luminance signal to encoder (LSB) VRST 51 input digital external VD (vertical drive) HRST 52 input digital external HD (horizontal drive) VDDD3 53 supply − digital supply voltage 3 VSSD3 54 supply − digital ground 3 VD 55 output digital VD timing for PPG IC HD 56 output digital HD timing for PPG IC FLD 57 output digital field pulse output HSYNC 58 output digital horizontal timing for YC processing CSYNC 59 output digital composite sync pulse SYNCI 60 input digital sync input for bypass mode CLAMP 61 output (3-state) digital clamp voltage control CPOB 62 input digital optical black pulse CP2 63 output digital clamping pulse VSSD2 64 supply − digital ground 2 VDDD2 65 supply − digital supply voltage 2 CLK1 66 input digital clock 1 CLK2 67 input digital clock 2 CDS0 68 input digital CDS signal (LSB) CDS1 69 input digital CDS signal CDS2 70 input digital CDS signal CDS3 71 input digital CDS signal CDS4 72 input digital CDS signal CDS5 73 input digital CDS signal CDS6 74 input digital CDS signal CDS7 75 input digital CDS signal CDS8 76 input digital CDS signal (MSB) TEST1 77 input digital test 1 pin VrefY 78 − − Y-DAC decoupling voltage VSSA2 79 supply − analog ground 2 for Y-DAC YOUT 80 output analog Y-DAC output 1996 Feb 16 5 Philips Semiconductors Preliminary specification 61 CLAMP 62 CPOB 63 CP2 64 VSSD2 65 VDDD2 66 CLK1 67 CLK2 68 CDS0 69 CDS1 70 CDS2 71 CDS3 SAA9750H 72 CDS4 73 CDS5 74 CDS6 75 CDS7 76 CDS8 77 TEST1 78 VrefY 79 VSSA2 handbook, full pagewidth 80 YOUT Camera Digital Signal Processor (CAMDSP) VDDA1 1 60 SYNCI VDDA2 2 59 CSYNC COUT 3 58 HSYNC 57 FLD VSSA1 4 VrefC 5 56 HD TEST2 6 55 VD LSW 7 54 VSSD3 TSW 8 53 VDDD3 52 HRST R 9 51 VRST G 10 SAA9750H Fig.2 Pin configuration. 1996 Feb 16 6 Y7 40 41 VDDD1 Y6 39 WCLIP 20 Y5 38 42 VSSD1 Y4 37 UVENC7 19 Y3 36 43 YENC7 Y2 35 UVENC6 18 Y1 34 44 YENC6 Y0 33 UVENC5 17 DI 32 45 YENC5 CK 31 UVENC4 16 CS 30 46 YENC4 UVSEL 29 UVENC3 15 UV0 28 47 YENC3 UV1 27 UVENC2 14 UV2 26 48 YENC2 UV3 25 UVENC1 13 UV4 24 49 YENC1 UV5 23 UVENC0 12 UV6 22 50 YENC0 UV7 21 B 11 MHA301 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H The encoded signal is output via separate 8-bit digital-to-analog converters (DACs) for luminance and chrominance. In the event of SECAM the output is a line sequential −(R−Y)/(B−Y) signal. A line memory interface allows for mixing of RGB signals in the main signal. The encoder can be bypassed completely, in this event only the title mix is carried out before digital-to-analog conversion. FUNCTIONAL DESCRIPTION The Camera Digital Signal Processor (CAMDSP) is intended for use with a mosaic filter colour CCD. The input signal is an 8-bit or 9-bit digitized CCD signal. After AGC and gamma correction, clamping of the input signal is achieved by feedback clamp level control. In the luminance processing, symmetrical horizontal and vertical aperture correction are carried out. Coring is also carried out to reduce noise at LOW signal levels. In the chrominance processing, white balance control and matrix control is adjustable. A false colour correction circuit reduces aliasing of high frequency input signals. A white-clip makes the colour white at highlights. The SSG generates all necessary timing signals. Timing signals for external devices NTSC, PAL and SECAM are also made. The SSG can be locked to an external video source. CAMDSP can operate with 510H, 670H, 720H and 768H colour mosaic CCDs both PAL and NTSC type. In the 510H CCD application the upsampling clock is used for the encoder part, therefore two clock frequencies (fs and 2fs) are required. In the encoder part, the colour encoder subcarrier is made by the discrete time oscillator thus eliminating the use of an extra crystal. The subcarrier frequency for PAL or NTSC is selectable. The encoding can be in PAL or NTSC format. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.5 +5.0 V VDDA analog supply voltage −0.5 +5.0 V Ptot total power dissipation − 500 mW VI digital input voltage −0.5 VDDD + 0.5 V VO digital output voltage −0.5 VDDD + 0.5 V Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −20 +70 °C Ves electrostatic handling −2000 +2000 V Ilatch latch-up protection current 100 − mA note 1 Note 1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Feb 16 PARAMETER thermal resistance from junction to ambient in free air 7 VALUE UNIT 57 K/W Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H DC CHARACTERISTICS VDD = 2.7 to 3.3 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL IDD PARAMETER supply current CONDITIONS MIN. − note 1 TYP. 60 MAX. 150 UNIT mA Inputs: LSW, TSW, R, G, B, UVENC0 to UVENC7, CS, CK, DI, YENC0 to YENC7, VRST, HRST, SYNCI, CPOB, CLK1, CLK2, CDS0 to CDS7, TEST1 and TEST2 VIH HIGH level input voltage 0.7VDD − − V VIL LOW level input voltage − − 0.3VDD V IIH HIGH level input current VIH = VDD − − 1 µA IIL LOW level input current VIL = VSS − − −1 µA Outputs: WCLIP, UV0 to UV7, UVSEL, Y0 to Y7, VD, HD, FLD, HSYNC, CSYNC and CP2 VOH VOL HIGH level output voltage LOW level output voltage IOH = −20 µA VDD − 0.1 − − V IOH = −2 mA VDD − 0.5 − − V IOL = +20 µA − − 0.1 V IOL = +2 mA − − 0.5 V Output: CLAMP (3-state output) VOH VOL ITL HIGH level output voltage LOW level output voltage 3-state leakage current IOH = −20 µA VDD − 0.1 − − V IOH = −8 mA VDD − 0.5 − − V IOL = +20 µA − − 0.1 V IOL = +8 mA − − 0.5 V VIH = VDD; VIL = VSS − − ±5 µA Note 1. 510H PAL; VDD = 3 V; DAC RL = 2 kΩ. DAC CHARACTERISTICS VDD = 3.0 V; Tamb = +25 °C; RL = open-circuit; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Outputs: YOUT and COUT fCmax conversion frequency speed 20 − − MHz INL DC integral linearity error −0.5 − +0.5 LSB DNL DC differential linearity error −0.5 − +0.5 LSB VO(p-p) full scale output except sync (peak-to-peak value) 1.61 1.66 1.72 V RO internal series output resistance − 75 − Ω 1996 Feb 16 8 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H AC CHARACTERISTICS Microprocessor interface VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD; Tamb = −20 to +70 °C; input tr and tf = 30 ns; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT tCSs CS set-up time 0.4 − − µs tCSh CS hold time 0.4 − − µs tCSd CS deselection time 0.2 − − µs tDs DI set-up time 0.4 − − µs tDh DI hold time 0.4 − − µs fCK CK frequency − − 0.5 MHz tWCKH HIGH level pulse width of CK 1.0 − − µs tWCKL LOW level pulse width of CK 1.0 − − µs tr rise time of CK − − 100 ns tf fall time of CK − − 100 ns tCSs tCSd VIH Vref CS VIL tCSh tWCKH tWCKL 90% VIH 90% CK Vref 10% 10% tr VIL tf tDs tDh VIH Vref DI MHA305 Fig.3 Microprocessor interface timing. 1996 Feb 16 9 VIL Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H Data input/output timing (CLK1 and CLK2) VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD;Tamb = −20 to +70 °C; tr and tf = 6 ns; output load capacitance = 20 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS tDIs data input set-up time note 1 tDIh data input hold time note 1 tDOd data output delay time notes 2 and 3 tDOh data output hold time notes 2 and 3 tduty duty factor of CLK1 and CLK2 MIN. TYP. MAX. − − ns 8 − − ns − − 50 ns − − 50 ns − 50 − % 5 Notes 1. Data inputs: SYNCI, CPOB, CDS0 to CDS8, VRST, HRST, R, G, B, TSW, YENC0 to YENC7, LSW and UVENC0 to UVENC7. 2. Data outputs: UVSEL, UV0 to UV7, Y0 to Y7, WCLIP, CSYNC, HSYNC, FLD, HD, VD and CP2. 3. Tamb = +25 °C; VDD = 3.0 V. tf tr 90% 90% CLK1 and CLK2 VIH Vref 10% 10% tDIs VIL tDIh 90% 90% 10% 10% VIH data inputs tDOd VIL tDOh 90% 90% 10% 10% VOH data outputs MHA306 Fig.4 Data input/output timing (CLK1 and CLK2). 1996 Feb 16 10 UNIT VOL Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H SSG TIMING Clock count for NTSC and PAL mode CCD 510H handbook, full pagewidth −10 (−15) 1H 606 (618) clocks 596 (603) 0 50 (45) SHD 60 (60) HD ,, ,, ,,,,, ,, ,, ,,,,, ,,, , ,,,,,, ,,, ,,,,,,, 24 (24) CP2 75 (75) 33 (33) Y0 to Y7 139 (151) 48 (48) HSYNC 93 (93) 57 (57) YDA and CDA 165 (177) 62 (62) SYNC CCD 670H 0 107 (107) 1H 806 (824) clocks 80 (80) SHD 80 (80) HD 32 (32) CP2 ,, ,,, 100 (100) 48 (48) HSYNC 108 (108) 195 (203) 51 (51) YDA and CDA 61 (61) ,,,,,,, ,,,,,, 168 (184) 28 (28) Y0 to Y7 121 (121) SYNC MHA307 Fig.5 SSG timing (continued in Fig.6). 1996 Feb 16 11 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) CCD 720H handbook, full pagewidth SAA9750H 1H 858 (864) clocks 0 83 (83) SHD 83 (83) HD 36 (36) CP2 104 (104) ,,, ,,, 34 (34) Y0 to Y7 50 (50) HSYNC 113 (113) 63 (63) 209 (229) YDA and CDA 67 (67) SYNC CCD 768H ,,,,,,, ,,,,,,, 172 (182) 0 130 (130) 1H 910 (908) clocks 89 (89) SHD 89 (89) HD ,,, ,,, ,,, ,,, 36 (36) CP2 108 (108) 54 (54) HSYNC 121 (121) 223 (235) 65 (63) YDA and CDA 71 (71) SYNC ,, ,,,,, ,, ,,,,, ,, ,,,,, ,,,,,,, 191 (203) 33 (33) Y0 to Y7 138 (138) MHA308 Fig.6 SSG timing (continued from Fig.5). SHD: HD output can be changed by microprocessor to SHD outputs. HD: For timing of input CDS signal for PPG IC. HSYNC: For output luminance signal Y7 to Y0 and chrominance signal UV7 to UV0 of CAMDSPs YC processing. SYNC: Composite SYNC pulse of DACs output. Output of CSYNC (pin 59): SYNC + 1 clock (see Figs 5 and 6). 1996 Feb 16 12 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H Clock Table 1 Clock frequency MODE CCD NTSC PAL SECAM Table 2 CLK1 (MHz) CLK2 (MHz) 510H 9.5350 19.0699 670H 12.7132 − 720H 13.5000 − 768H 14.3182 − 510H 9.6563 19.3125 670H 12.8750 − 720H 13.5000 − 768H 14.1875 − Clock used for each block MODE SSG BLOCK ENCODER BLOCK Y/C BLOCK Y-DAC BLOCK C-DAC BLOCK 510H NTSC/PAL CLK1 CLK1 CLK1 and CLK2 (upsampling) CLK1 CLK2 Other modes CLK1 CLK1 CLK1 CLK1 CLK1 MICROPROCESSOR INTERFACE FORMAT handbook, full pagewidth CS CK DI MSB LSB slave address(1) MSB LSB MSB subaddress data (1) Slave address 001. Fig.7 Microprocessor interface format. 1996 Feb 16 LSB 13 MHA304 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) Table 3 SAA9750H Microprocessor interface format DATA FUNCTION SUBADDRESS MSB LSB Field delay 00000 X − − − − − − FD Title enable 00000 X − − − Title polarity 00000 X − − − − − TE − − TP − − False colour +6 dB 00000 X − − − FCU − − − UV +6 dB 00000 X − − CUP − − − − Y +6 dB 00000 X − YUP − − − − − Y clear 00000 X YCL − − − − − − HAP LOW clip 00001 X X HA5 HA4 HA3 HA2 HA1 HA0 VAP LOW clip 00010 X X VA5 VA4 VA3 VA2 VA1 VA0 AP HIGH clip 00011 X − − − AP3 AP2 AP1 AP0 AP gain 00011 X AG2 AG1 AG0 − − − − Y gain 00100 X X YG5 YG4 YG3 YG2 YG1 YG0 Y pedestal 00101 YP7 YP6 YP5 YP4 YP3 YP2 YP1 YP0 Slice 00110 X X X − − − SLI SNP Mosaic 00110 X X X MOS PX1 PX0 − − Slice level 00111 SLL7 SLL6 SLL5 SLL4 SLL3 SLL2 SLL1 SLL0 Subcarrier 01000 S7 S6 S5 S4 S3 S2 S1 S0 01001 S15 S14 S13 S12 S11 S10 S9 S8 01010 − − − − S19 S18 S17 S16 01010 − − − UVP − − − − UV polarity SYNCI 01010 − − SYN − − − − − Encoder mode 01010 EM1 EM0 − − − − − − Burst level 01011 X BL6 BL5 BL4 BL3 BL2 BL1 BL0 HRST delay 01101 D7 D6 D5 D4 D3 D2 D1 D0 01110 − − − − − − D9 D8 01110 − − − − H1 H0 − − CCD type 525/625 line 01110 − − − LL − − − − Master/slave 01110 − − MS − − − − − ADC delay 01110 AD1 AD0 − − − − − − Solarization 01111 X X X − − − TR1 TR0 01111 X X X − − SOL − − Sepia 01111 X X X − SEP − − − Negative/positive 01111 X X X NP − − − − R gain 10000 X RG6 RG5 RG4 RG3 RG2 RG1 RG0 B gain 10001 X BG6 BG5 BG4 BG3 BG2 BG1 BG0 U gain 10010 X X UGP5 UGP4 UGP3 UGP2 UGP1 UGP0 10011 X X UGN5 UGN4 UGN3 UGN2 UGN1 UGN0 1996 Feb 16 14 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H DATA FUNCTION SUBADDRESS MSB V gain LSB 10100 X X VGP5 VGP4 VGP3 VGP2 VGP1 VGP0 10101 X X VGN5 VGN4 VGN3 VGN2 VGN1 VGN0 10110 X X UM5 UM4 UM3 UM2 UM1 UM0 U matrix 2 gain 10111 X X UN5 UN4 UN3 UN2 UN1 UN0 V matrix 1 gain 11000 X X VM5 VM4 VM3 VM2 VM1 VM0 V matrix 2 gain 11001 X X VN5 VN4 VN3 VN2 VN1 VN0 SP polarity 11010 X X X − − − − SPP FH2 polarity 11010 X X X − − − FHP − Colour filter 11010 X X X − − LPF − − HD, VD polarity 11010 X X X − SHV − − − Sub LPF 11010 X X X JGM − − − − False colour 11011 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 White-clip level 11100 WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0 Y delay 11101 X X X X − − YDL1 YDL0 C delay 11101 X X X X CDL1 CDL0 − − U matrix 1 gain Table 4 Explanation of functions of Table 3 SYMBOL DESCRIPTION FD field delay control TE title enable control TP title polarity control FCU false colour plus 6 dB up CUP UV +6 dB up YUP Y gain +6 dB up YCL Y clear control HA0 to HA5 horizontal aperture LOW clip level control VA0 to VA5 vertical aperture LOW clip level control AP0 to AP3 aperture HIGH clip level control AG0 to AG2 aperture gain control YG0 to YG5 Y gain control YP0 to YP7 Y pedestal control SNP slice effect polarity SLI slice ON/OFF PX0 and PX1 mosaic effect pixels control MOS mosaic ON/OFF SLL0 to SLL7 slice level control S0 to S19 subcarrier control UVP UVSEL polarity control SYN SYNC signal selection 1996 Feb 16 15 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H SYMBOL DESCRIPTION EM0 and EM1 encoder mode control BL0 to BL6 burst level control D0 to D9 HRST and VRST preset control H0 and H1 CCD type selection LL 525/625 line control MS master/slave control AD0 and AD1 ADC delay control TR0 and TR1 solarization effect control SOL solarization ON/OFF SEP sepia ON/OFF NP negative/positive ON/OFF RG0 to RG6 red gain control BG0 to BG6 blue gain control UGP0 to UGP5 U gain control for positive side UGN0 to UGN5 U gain control for negative side VGP0 to VGP5 V gain control for positive side VGN0 to VGN5 V gain control for negative side UM0 to UM5 U matrix 1 gain control UN0 to UN5 U matrix 2 gain control VM0 to VM5 V matrix 1 gain control VN0 to VN5 V matrix 2 gain control SPP SP polarity control FHP FH2 polarity control LPF colour filter control SHV HD and VD polarity control JGM sub LPF control for false colour TH0 to TH7 threshold control for false colour suppression WC0 to WC7 white-clip level control YDL0 and YDL1 Y delay control CDL0 and CDL1 C delay control 1996 Feb 16 16 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H MICROPROCESSOR SETTING Horizontal aperture LOW clip level control = HA5 to HA0. Table 5 Vertical aperture LOW clip level control = VA5 to VA0. Field delay control FIELD DELAY CONTROL Normal 0 One field delay 1 Table 6 YG [ 5:0 ] Y gain control = ------------------------32 TE Title insertion OFF 0 Title insertion ON 1 Table 7 Y pedestal level control = YP7 to YP0. Table 12 Slice effect polarity SLICE EFFECT POLARITY Title polarity control TITLE POLARITY CONTROL TP Negative 0 Positive 1 0 Positive 1 Table 13 Slice ON/OFF SLICE ON/OFF FCU 0 dB gain 0 +6 dB gain 1 SLI OFF normal 0 ON slice 1 Table 14 Mosaic effect pixels control MOSAIC EFFECT PIXELS CONTROL UV +6 dB up UV +6 dB UP SNP Negative False colour +6 dB up FALSE COLOUR +6 dB UP Table 9 AG [ 2:0 ] Aperture gain control = -----------------------8 Title enable control TITLE ENABLE CONTROL Table 8 Aperture HIGH clip level control = AP3 to AP0. FD CUP PX1 PX0 4 × 4 pixels 0 0 8 × 8 pixels 0 1 0 dB gain 0 16 × 16 pixels 1 0 +6 dB gain 1 32 × 32 pixels 1 1 Table 10 Y gain +6 dB up Y GAIN +6 dB UP Table 15 Mosaic ON/OFF YUP MOSAIC ON/OFF MOS 0 dB gain 0 OFF normal 0 +6 dB gain 1 ON mosaic 1 Table 11 Y clear control Y CLEAR CONTROL Slice level control = SLL7 to SLL0. YCL Normal 0 Clear 1 1996 Feb 16 S [ 19:0 ] × f encoder Subcarrier frequency control = -----------------------------------------------1048576 17 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H Table 21 Master/slave control Table 16 UVSEL polarity control UVSEL POLARITY CONTROL MASTER/SLAVE CONTROL UVP Normal 0 HIGH: U(B−Y) LOW: V(R−Y) Invert 1 HIGH: V(R−Y) LOW: U(B−Y) MS Master 0 Slave 1 Table 22 AD converter delay control Table 17 SYNC signal selection SYNC SIGNAL SELECTION ADC DELAY CONTROL (CAMDSP DELAY) SYN AD1 AD0 Internal SYNC 0 3Ts 0 0 External SYNC (from SYNCI pin 60) 1 4Ts 0 1 5Ts 1 0 6Ts 1 1 TR1 TR0 3 bits (LSB) 0 0 4 bits (LSB) 0 1 5 bits (LSB) 1 0 6 bits (LSB) 1 1 Table 18 Encoder mode control ENCODER MODE CONTROL EM1 EM0 PAL 0 0 NTSC 0 1 SECAM 1 0 Bypass 1 1 Table 23 Solarization effect control SOLARIZATION EFFECT CONTROL (SLICE OF BITS) BL [ 6:0 ] Burst level control = ----------------------- (of full-scale DAC output). 128 HRST and VRST preset control = D9 to D0, preset horizontal counter to count D9 to D0. Table 24 Solarization ON/OFF SOLARIZATION ON/OFF Table 19 CCD type selection CCD TYPE SELECTION H1 H0 510H 0 0 670H 0 1 720H 1 0 768H 1 1 SOL Normal 0 Solarization ON 1 Table 25 Sepia ON/OFF SEPIA ON/OFF SEP Normal 0 Sepia ON 1 Table 20 525/625 line control 525/625 LINE CONTROL 525 line 0 625 line 1 1996 Feb 16 Table 26 Negative/positive ON/OFF LL NEGATIVE/POSITIVE ON/OFF 18 NP Normal 1 Negative 0 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H RG [ 6:0 ] R channel gain control = 1 + ------------------------- (1) 128 Table 29 Colour filter control COLOUR FILTER CONTROL BG [ 6:0 ] B channel gain control = 1 + ------------------------ (1) 128 UGP [ 5:0 ] U gain control for positive side = ----------------------------16 UN [ 5:0 ] U matrix 2 gain control = ------------------------ (1) 32 Normal 0 Invert 1 JGM Normal 0 Sub LPF 1 Y DELAY CONTROL SPP H: Ye + Mg or Ye + Gr L: Cy + Gr or Cy + Mg FHP 0 1 YDL0 0 clock period 0 0 +1 clock period 0 1 +2 clock periods 1 0 +3 clock periods 1 1 CDL1 CDL0 0 clock period 0 0 +1 clock period 0 1 +2 clock periods 1 0 +3 clock periods 1 1 C DELAY CONTROL L: Ye + Mg or Ye + Gr FH2 POLARITY CONTROL YDL1 Table 33 C delay control H: Cy + Gr or Cy + Mg Table 28 FH2 polarity control H: 2B-G L: 2R-G H: 2R-G L: 2B-G (1) RG, BG, UM, UN, VM and VN are twos complement. 1996 Feb 16 SHV Table 32 Y delay control Table 27 SP polarity control Invert [−1,0,4,8,10,8,4,0,−1]/32 White clip level control = 2 × WC7 to WC0. VN [ 5:0 ] V matrix 2 gain control = ------------------------ (1) 32 Normal 1 Threshold control for false colour suppress = TH7 to TH0. VM [ 5:0 ] V matrix 1 gain control = ------------------------- (1) 32 1 LPF2 SUB LPF CONTROL FOR FALSE COLOUR UM [ 5:0 ] U matrix 1 gain control = ------------------------- (1) 32 Invert [1,1,3,3,4,4,4,4,3,3,1,1]/32 Table 31 Sub LPF control for false colour VGN [ 5:0 ] V gain control for negative side = ----------------------------16 0 0 HD AND VD POLARITY CONTROL VGP [ 5:0 ] V gain control for positive side = ----------------------------16 Normal LPF1 Table 30 HD and VD polarity control UGN [ 5:0 ] U gain control for negative side = ----------------------------16 SP POLARITY CONTROL LPF 19 focus sensor Y hall sensor LPF CCD CLAMP CDS AGC, GAMMA ADC 20 AGC zoom lens focus lens iris PPG MOTOR DRIVER MOTOR DRIVER IRIS DRIVER C BPF DAC CAMDSP SIGNAL PROCESSOR 8-bit Y/C SEPARATION SSG serial ENCODER data bus HD/VD SAA9750H UVSEL HSYNC WCLIP high speed shuffle control UV (8-bit) ADC UV(8) Y(5) A2CF AF/AE/AWB CDS(8) Y (8-bit) Philips Semiconductors zoom encoder CAMERA Camera Digital Signal Processor (CAMDSP) CAMERA 1996 Feb 16 handbook, full pagewidth I/F(8) MICROPROCESSOR SAA9750H 3 MHA303 Preliminary specification SAA9750H Fig.8 Camera block diagram (SAA9750H and SAA9740H). Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp L pin 1 index 80 Lp 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1.0 0.75 0.30 0.2 0.15 0.1 Z D (1) Z E (1) θ 1.45 1.05 7 0o 1.45 1.05 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-07-15 SOT315-1 1996 Feb 16 EUROPEAN PROJECTION 21 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Feb 16 22 Philips Semiconductors Preliminary specification Camera Digital Signal Processor (CAMDSP) SAA9750H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Feb 16 23 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1100/01/pp24 Document order number: Date of release: 1996 Feb 16 9397 750 00641