SC900 Programmable Penta ULDO with RESET and I2C Interface POWER MANAGEMENT Description Features The SC900 is a highly integrated power management device for low power portable applications. The device contains five adjustable low-dropout linear regulators (LDOs) with CMOS pass-devices as well as a band-gap reference, I2C interface, and DACs to control the output voltages. ! ! ! ! ! ! ! ! ! ! ! ! ! Many features of the SC900 are programmable through the I2C interface. These include the ability to independently turn on any combination of the five regulators. All five of the LDO output voltages are programmable in 50mV steps from 1.45V to 3.00V. Each LDO can have an active shutdown or nonactive shutdown program option through the interface. There is also a reset monitor flag that is associated with LDOA. In addition, the device has a separate programmable power-good monitor flag that activates when one or more LDOs go out of regulation. The SC900 offers significant quiescent current and space savings to the system designer by sharing reference and biasing among five LDOs. The small and thermally efficient 20-lead MLPQ package make it ideal for use in portable products where minimizing layout area is critical. Five LDO regulators in one package I2C interface with multiple device capability Independent I2C enable/disable of LDOs Independent I2C control of output voltages Low thermal impedance of 40°C per watt 150mV dropout at 150mA Input range from 2.7V to 5.5V Programmable power-good flag Minimal number of external components Over temperature protection Small 4mm x 4mm 20-lead MLPQ package Small input/output filter capacitors Programmable VOUT range - 1.45V to 3.00V for each LDO Applications ! ! ! ! ! Typical Application Circuit Palmtop/Laptop computers Personal Digital Assistants Cellular telephones Battery-powered equipment High efficiency linear power supplies SC900 LDOE 2.2µF LDOD VIN 4.7µF VBAT LDOA INA LDOB INB LDOC 2.2µF INCD 2.2µF 2.2µF INE EN Baseband Processor Receiver Section VREF LNA LDOPGD TXCO & Synthesizer ARST 0.1µF SDA SCL A0 VASEL GND DGND Audio Processing Transmitter Section PA Keypad Digital Interface March 29, 2005 1 2.2µF www.semtech.com SC900 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Input Supply Voltage VIN -0.3 to +7 V Digital Input Voltage VDIG -0.3 to VIN+0.3 V Operating Ambient Temperature Range TA -40 to +85 °C Operating Junction Temperature Range TJ -40 to +125 °C Peak IR Reflow Temperature TLEAD 260 °C Storage Temperature TSTG -60 to +150 °C Thermal Resistance Junction to Ambient θJ A * 40 °C/W *1 Square inch, 2 ounce copper. Electrical Characteristics Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min VIN All outputs < VIN - dropout 2.7 Typ Max Units 5.5 V 10 µA General Supply Voltage Quiescent Current Shutdown Supply Bypass Capacitor IQ-SHUTDOWN Per input pin C VC C 1 µF Digital Inputs Digital Input Voltage Digital Input Current 0.4 VIL VIH 1.6 IDIG -0.2 V V 0.2 µA 10 % LDOB Digital Outputs Digital Output Voltage(1) VOL ISINK = 1.2mA, VLDOB ≥ 1.8V VOH ISOURCE = 0.5mA, VLDOB ≥ 1.8V 2 90 98 % LDOB Reference and Biasing Circuitry Quiescent Current Reference IQ-REF 25 µA Reference Voltage VREF 1.227 V VREF Start-up Time tVREF 15 ms 2005 Semtech Corp. CVREF= 100nF 2 www.semtech.com SC900 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85°C. Typical values are at TA = +25°C. Parameters Symbol Conditions Min Typ Max Units Reference and Biasing Circuitry (cont.) VREF Bypass Capacitor CVREF 0.1 µF LDO Regulators Quiescent Supply Current IQ All LDOs active in default states 190 Quiescent Supply Current at Start-up IQSUP LDO A, B, C active in default states VOUT + 0.5V < VIN < 5.5V 125 VOUT = 3.0V, IOUT = 1mA VOUT = 3.0V, IOUT= 50mA VOUT = 3.0V, IOUT= 150mA 1.1 50 150 64 190 VOUT = 3.0V, IOUT = 200mA 200 250 410 650 Dropout Voltage LDO B,C,D,E VD LD O A Current Limit ILIM Power Supply Rejection Ratio Output Voltage Noise(2) Bypass Capacitor 250 360 µA µA mV mA PSRR f = 10Hz -1kHz, CBYP = 0.1µF, IOUT = 50mA 2.5V < VOUT < 3.0V 60 dB en f =10Hz to 100kHz, IOUT= 50mA CVREF = 0.1µF, COUT = 2.2µF 2.5V ≤ VOUT ≤ 3.0V 45 µVrms CBYP Ceramic, low ESR 2.2 VOAA 1.45V ≤ VOUT ≤ 3.00V VOUT+0.2V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25OC -3 +3 % IOUT = 1mA -2 +2 % IOUT = 1mA, TA = 25OC -3 +3 % IOUT= 200mA, VOUT+0.5V ≤ VIN ≤ 5.5V -3.5 +3.5 % µF LDO Regulator A (CORE SUPPLY) Output Voltage Accuracy Output Voltage Accuracy at 2.80V (DAC=11011) Output Voltage Accuracy at 1.80V (DAC=00111) VOASA Output Voltage Accuracy at 2.80V (DAC=11011) Maximum Output Current Default Setting: ON IOMAXA 200 mA VOA-HI VASEL – High 2.80 V VOA-LO VASEL – Low 1.80 V Line Regulation at 1.8V, 2.8V LINEREGA IOUT = 1mA, VOUT+0.2V < VIN< 5.5V 2.5 12 mV Load Regulation at 1.8V, 2.8V LOADREGA 1mA < IOUT < 200mA -3 -20 mV 2005 Semtech Corp. 3 www.semtech.com SC900 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min 1.45V ≤ VOUT ≤ 3.00V VOUT+0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25OC Typ Max Units -3 +3 % IOUT = 1mA -2 +2 % IOUT = 150mA, VOUT +0.5V ≤ VIN ≤ 5.5V -3.5 +3.5 % LDO Regulator B (DIGITAL I/O SUPPLY) Output Voltage Accuracy VOAB Output Voltage Accuracy at 2.80V (DAC=11011) VOASB Maximum Output Current IOMAXB Default Setting: ON Line Regulation 2.80V Load Regulation at 2.80V 150 mA 2.80 VOB V LINEREGB IOUT = 1mA, VOUT +0.15V ≤ VIN ≤ 5.5V 2.5 12 mV LOADREGB 1mA < IOUT <150mA -3 -20 mV VOAC 1.45V ≤ VOUT ≤ 3.00V VOUT+0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25OC -3 +3 % IOUT = 1mA -2 +2 % IOUT = 150mA, VOUT+0.5V ≤ VIN ≤ 5.5V -3.5 +3.5 % LDO Regulator C Output Voltage Accuracy Output Voltage Accuracy at 2.60V (DAC=10111) VOASC Maximum Output Current IOMAXC Default Setting: ON mA 150 VOC V 2.60 Line Regulation at 2.60V LINEREGC IOUT = 1mA, VOUT+0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 2.60V LOADREGC 1mA < IOUT <150mA -3 -20 mV Output Voltage Accuracy VOAD 1.45V ≤ VOUT ≤ 3.00V VOUT+0.15V ≤ VIN ≤ 5.5V IOUT = 1mA, TA = 25OC -3 +3 % Output Voltage Accuracy at 2.80V (DAC=11011) VOASD IOUT = 1mA -2 +2 % IOUT = 150mA, VOUT+0.5V ≤ VIN ≤ 5.5V -3.5 +3.5 % Maximum Output Current IOMAXD LDO Regulator D Default Setting: OFF mA 150 2.80 VOD V Line Regulation at 2.80V LINEREGD IOUT = 1mA, VOUT+0.15V < VIN < 5.5V 2.5 12 mV Load Regulation at 2.80V LOADREGD 1mA < IOUT <150mA -3 -20 mV 2005 Semtech Corp. 4 www.semtech.com SC900 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min VOAE 1.45V < VOUT < 3.00V VOUT +0.15V < VIN < 5.5V IOUT = 1mA, TA = 25OC Output Voltage Accuracy at 2.80V (DAC=11011) VOASE Maximum Output Current IOMAXE Typ Max Units -3 +3 % IOUT = 1mA -2 +2 % IOUT = 150mA, VOUT + 0.5V < VIN < 5.5V -3.5 +3.5 % LDO Regulator E Output Voltage Accuracy Default Setting: OFF Line Regulation at 2.80V Load Regulation at 2.80V 150 VOE mA 2.80 V LINEREGE IOUT = 1mA, VOUT +0.15V < VIN < 5.5V 2.5 12 mV LOADREGE 1mA < IOUT < 150mA -3 -20 mV I2C Interface Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January 2000. Digital Input Voltage VIL 0.4 1.6 VIH SDA Output Low Level Digital Input Current IDG I/O Pin Capacitance CIN V V IDIN(SDA) = 3mA 0.4 V IDIN(SDA) = 6mA 0.6 V 0.2 µA -0.2 10 pF I2C Timing Clock Frequency SC L SCL Low Period tLOW 1.3 µs SCL High Period tHIGH 0.6 µs Data Hold Time tHD_DAT 0 µs Data Setup Time tSU_DAT 100 ns Setup Time for Repeated Start Condition tSU_STA 0.6 µs Hold Time for Repeated Start Condition tHD_STA 0.6 µs SetupTime for Stop Condition tSU_STO 0.6 µs tBUF 1.3 µs Bus-Free Time Between STOP and START 2005 Semtech Corp. 400 5 kHz www.semtech.com SC900 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min Typ Max Units A R ESET Reset Threshold Reset Active Timeout Delay 77 RESETTHLD tRD Delay in default state 75 100 % 125 ms LDO POWER GOOD PGOOD Threshold PGOOD Active Timeout Delay 77 PGOODTHLD tPG Delay in default state 75 100 % 125 ms Notes: (1) Digital outputs are powered from LDOB, so LDOB must be active for operation of LDOPGD and ARST. (2) Below 2.5V: becomes digital regulator. 2005 Semtech Corp. 6 www.semtech.com SC900 20 19 18 17 LDOD Ordering Information INCD LDOC INA LDOA POWER MANAGEMENT Pin Configuration 16 15 LDOE 14 INE 3 13 VIN SCL 4 12 GND EN 5 11 VREF T 6 7 8 9 10 ARST SDA TOP VIEW LDOPGD 2 VASEL INB DGND 1 A0 LDOB DEVICE PACKAGE(1) SC900IMLTRT(2) MLPQ20L S C 900E V B Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in Lead-free package only. This product is fully WEEE and RoHS compliant. MLPQ20: 4X4 20 LEAD 2005 Semtech Corp. 7 www.semtech.com SC900 POWER MANAGEMENT Pin Description Pin# Pin Name Pin Function 1 LDOB LDO B output. 2 INB Input supply for the digital system logic and the LDO B pass transistor. 3 SD A Bidirectional open drain digital I/O pin. I2C serial data. 4 SC L Digital input. I2C serial clock. EN Digital input. High to enable part. Low to disable part (sleep mode). Note I2C control is active only when part is enabled. 6 A0 One bit address for connecting two SC900 devices onto the system through the I2C interface. 7 DGND Digital ground. 8 VASEL LDO A selection default voltage. Tie this pin to ground for 1.8V or INB for 2.8V. 5 9 LDOPGD Digital output. State change indicates that one of four LDO output voltages (A,C,D or E) is out of spec. Note, desired state of pin is programmable through the I2C interface. ARST Digital output. State change indicates LDOA output voltage is out of spec. Note; desired state of pin is programmable through the I2C interface. 11 VREF Bandgap reference output voltage. Connect at least 0.1µF to ground (CVREF ≥ 0.1µF). 12 GND Analog ground. 13 VIN Analog supply voltage. 14 INE Input supply for the LDO E pass transistor. 15 LDOE LDO E output. 16 LDOD LDO D output. 17 INCD Input supply for the LDO C and LDO D pass transistors. 18 LDOC LDO C output. 19 INA 20 LDOA T Thermal 10 2005 Semtech Corp. Input supply for the LDO A pass transistor. LDO A output. Pad for heat sinking purposes. Connect to ground plane using multiple vias. Not connected internally. 8 www.semtech.com SC900 POWER MANAGEMENT Block Diagram INA INB INB Reference VIN EN VREF DACs I2C Interface DAC A en vasel SCL SDA A0 scl sda a0 en out LDOA dac DAC B DAC C en VASEL LDO ref input CTRL Input DAC CTRL DAC D LDO DAC E LDO CTRL reset CTRL ref en input out dac VOB LDOB INB VOB ARST LDOPGD Reset/ Shutdown CTRL arst LDO ref en input dac out LDOC reset ldopgd LDO ref input en out dac LDO INCD INE DGND 2005 Semtech Corp. LDOD ref en input dac out LDOE GND 9 www.semtech.com SC900 POWER MANAGEMENT Applications Information General Description Each of the five low-dropout linear regulators (LDOs) can be independently enabled or disabled and their output voltages can each be set by an independent DAC. These controls can be accessed through the I2C serial port. There are five 8-bit volatile registers in the SC900; one for each LDO (registers A,B,C,D,E). In addition there is one common reset and power good control register and one on/off control register. The active shutdown circuitry can be accessed through each LDO register (refer to the section “Active Shutdown” on page 11 for more information). At power-up, the register contents are reset to their default values and the ARST for LDO A has a default startup delay of 100ms. At any time the part can be put into it’s lowest power state (shutdown) by pulling the EN pin low. Whenever the EN pin is forced low, the previous settings are lost and the part requires reprogramming to return to the desired state. When EN is pulled high, the device starts up in the default state. A detailed description of the protocol used to load the registers with data is described in the section entitled “Using the I2C Interface” on page 13. VIN and Enable Pin The VIN supply must be ≥ 2.7V before the EN pin can be asserted. This means that the EN pin should not be tied to VIN so that it does not reach a logic high level before the input supply reaches 2.7V. LDOA (Core Supply) LDOA is intended to be used as the MSM core supply. It has an output current capability of 200mA and a dedicated reset signal ARST. INA is the dedicated input supply for this regulator. LDOB (Digital I/O Supply) INB supplies power for the internal I2C interface and other digital I/O functions, while LDOB supplies power for ARST and LDOPGD output ports (see block diagram). Therefore it is imperative that LDOB be operational to make use of ARST and LDOPGD. If LDOB is turned off by the on/off control register, these output ports will not function. 2005 Semtech Corp. 10 LDO RESET Control Register: ARST Pin There are two functions that can be programmed, defining the ARST pin action: • Set the polarity of the reset signal • Set the reset clear delay time in milliseconds As soon as the LDOA output voltage falls below its programmed value, the ARST pin is asserted. The polarity of the ARST pin can be set to active high or active low during a reset condition, by bit 6 of the LDO Reset Control Register. Once the error condition is resolved (output rises to the programmed value), a delay is initiated before the ARST pin is cleared. The delay is programmable by bits 0-1 of the LDO Reset Control Register. The Default delay time is 100ms, and the delay can be programmed for 0, 50, 100, or 150ms. LDOPGD Pin There are three functions that can be programmed to define the LDOPGD pin action: • Set which LDOs are to be monitored for power-good • Set the polarity of the power-good signal • Set the power-good delay time in milliseconds Bits 4 and 5 of the LDO Reset Control Register select which LDO or LDOs are monitored. LDO C, D and E can be monitored independently or LDOs A, C, D, & E can be monitored collectively. The polarity of the LDOPGD pin can be set to active high or active low by bit 7 of the LDO Reset Control Register. As soon as any of the selected LDO output voltages which are monitored falls within spec, the LDO power-good (LDOPGD) pin is asserted. Once the LDO output power is stable (output rises to the programmed value), a delay is initiated before the LDOPGD pin is set. The delay is programmable by bits 2 and 3 of the LDO Reset Control Register. The default delay is 100ms, and this delay can be programmed to 0, 50, 100, or 150ms. www.semtech.com SC900 POWER MANAGEMENT Applications Information (Cont.) Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Each LDO register uses bit 5 of the LDO output voltage data byte to control the shutdown behavior. When the active shutdown bit is enabled (set to 1), the capacitance on the LDO output will be discharged by an on-chip FET after the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default active shutdown state for all LDOs is on. ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bit to 1. Likewise, they can be turned off by setting the on/off bit to 0. This allows for on/off control with a single write command. If the enable (EN) pin is high and data is written to the LDO voltage registers, the LDO outputs will go to the voltage prescribed by the Output Voltage Code bits (0-4). Data will not be lost when toggling the on/off bit from 0 to 1. However, if the EN pin is forced low, all circuitry in the device is disabled. All programmed information is lost when the enable bit is subsequently pulled high. VASEL Pin The VASEL pin sets the default voltage of LDO A, the core supply. When this pin is set to VIN, the default voltage is 2.80V. When this pin is set to GND, the default voltage is 1.80V. The voltage can be changed from its default state after start up by writing to the LDO voltage code register. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The most significant six bits of the slave are the device type identifier (ID). For the SC900 this is fixed at 000100[B]. The next significant bit addresses a particular device. A system can have up to two SC900 devices on the bus. The two addresses are defined by the state of the A0 input (see Figure 1). D EVIC E TYPE ID EN TIFIER 0 0 0 1 0 D EVIC E AD D R ESS 0 Pi n A0 to GND = 0 Pi n A0 to VIN = 1 R /W X When the A0 pin is tied to GND, device 1 has an address of 0 and the combination of device type ID and address is 0x08H. When the A0 pin is tied to VIN, device 2 has and address of 1 and the combination of device type ID and address is 0x09H. The last bit of the slave address defines the operation to be performed. When set to a one a read operation is selected; when set to a zero a write operation is selected. Following a start condition, the SC900 monitors the SDA line comparing the slave address being transmitted with its slave address (device type ID and state of A0 input). Upon a correct compare the SC900 outputs an acknowledge on the SDA line. Depending on the state of the R/ W bit, the SC900 will execute a read or write operation. Protection Circuitry The SC900 provides protection circuitry that prevents the device from operating in an unspecified state. These include Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under Voltage Lockout The SC900 provides an Under Voltage Lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, the LDOs are disabled. As the battery voltage increases above the hysteresis level, the LDOs are re-enabled into their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900 will shut down. Over-temperature Protection The SC900 provides an internal Over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold, the OT protection disables all the LDO outputs. As the junction temperature drops below the hysteresis level the OT protection re-enables all the LDOs in their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900 will shut down. Short-circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed. Figure 1 - Slave Address Structure 2005 Semtech Corp. 11 www.semtech.com SC900 POWER MANAGEMENT Applications Information (Cont.) voltage track is very thin, then use five 1µF capacitors placed very close to the input pins of the SC900. If the input track is fairly thick, then you can use a single 4.7µF capacitor at the beginning of the voltage feed track since a wider track has less inductance per inch. The SC900EVB has five 1µF capacitors, but these can be replaced with one 4.7µF in place of C1 and opens in place of C9, C14, C15, and C16 (see page 20 for details). Layout Considerations Layout is straightforward if you use the Gerber files on page 21 as a reference. Notice that the input voltage feed to the SC900 is on the bottom of the board and vias connect this voltage track to the top of the board and then to the SC900 itself. The input bypass can be one 4.7µF capacitor, two 3.3µF capacitors, three 2.2µF capacitors or five 1µF capacitors. The determining factor is how much copper is available on the input voltage feed track and how much room is available. If the input LDO Reset Control Logic Table (Defaults are in Bold) Register Name Register Address Bit 7 Bit 6 Bit 5 X X Active Shutdown 1 = ON 0 = OFF LD O A 0x00 LD O B 0x01 LD O C 0x02 LD O D 0x03 LD O E 0x04 LDO Reset Control 0x05 LDOPGD Pin Reset Polarity Bit ARST Pin Reset Polarity Bit On/Off Control Register 0x06 X X Bit 4 Bit 3 Bit 1 Bit 0 LDO Output Voltage Codes Table A LDOPGD Monitor Logic Bits X Bit 2 ON/OFF Control LD O E LDOPGD Delay Bits ON/OFF Control LD O D LDO (A) Reset Delay Bits ON/OFF Control LD O C ON/OFF Control LD O B ON/OFF Control LD O A 1 0 1 0 1 0 1 0 1 0 ON OFF ON OFF ON OFF ON OFF ON OFF LDO Reset Control Logic Table (Defaults are in Bold) Bit 7 Result Bit 6 LDOPGD Pin Polarity Result ARST Pin Polarity Bit 5 Bit 4 Result LDOPGD Monitor Logic Bit 3 Bit 2 Result LDOPGD Delay Bit 1 Bit 0 Result ARST Delay 0 High: Power Fail Low: Power Good 0 High: Reset Low: Power Good 0 0 LDOs A,C,D&E Good 0 0 150ms 0 0 150ms 1 High: Pow er Good Low : Pow er Fail 1 High: Pow er Good L o w : R eset 0 1 LDO E Good 0 1 100ms 0 1 50ms 1 0 LDO C Good 1 0 50ms 1 0 100ms 1 1 LDO D Good 1 1 0ms 1 1 0ms Notes: Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST. SC900 Slave Address: D EVIC E TYPE ID EN TIFIER 0 0 0 1 2005 Semtech Corp. 0 D EVIC E AD D R ESS 0 A0 R /W X 12 www.semtech.com SC900 POWER MANAGEMENT Applications Information (Cont.) Output Voltage Code Bits: A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages. Table A - LDO Output Voltage Control Settings Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDO Output Voltage 0 0 0 0 0 1.45V 0 0 0 0 1 1.50V 0 0 0 1 0 1.55V 0 0 0 1 1 1.60V 0 0 1 0 0 1.65V - - - - - - - - - - - - 1 1 1 1 0 2.95V 1 1 1 1 1 3.00V Using the I2C Interface The SC900 is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January 2000. The SC900 has six user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC900 enabling it to be a slave transmitter/ receiver, any register can be written or read from independent of each other. While there is no auto increment/ decrement capability in the SC900 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC900 Limitations to the I2C Specifications Seven-bit addressing is required for communicating with the SC900; ten-bit addressing is not allowed. Any general call address will be ignored by the SC900. Note that the SC900 is not CBUS compatible. Finally, the SC900 can operate in standard mode (100kbit/s) or fast mode (400kbit/s). 2005 Semtech Corp. 13 www.semtech.com SC900 POWER MANAGEMENT Applications Information (Cont.) Supported Formats Direct Format - Write The simplest format for an I2C write is the direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. I2C Direct Format - Write S Slave Address W A Register Address A S : Start Condition W: Write = '0' A : Acknowledge (sent by slave) Sr: Repeated Start Condition P : Stop Condition Data A P Slave Address : 7 bit Register Address : 8 bit Data : 8 Bit Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. I2C Combined Format - Read S Slave Address W A Register Address A Sr S : Start Condition W: Write = '0' R : Read = '1' A : Acknowledge (Sent by Slave) B : Acknowledge (Sent by Master) Sr: Repeated Start Condition P : Stop Condition 2005 Semtech Corp. 14 Slave Address R A Data B P Slave Address : 7 bit Register Address : 8 bit Data : 8 Bit www.semtech.com SC900 POWER MANAGEMENT Applications Information (Cont.) Stop Separated Reads Another read format is available which is, in effect, an extension of the combined format read. This format allows a master to set up the register address pointer for a read and return to that slave some time later to read the data. After the start condition [S], the slave address is sent, followed by a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with the 8-bit register address. The master then sends a stop or restart condition, and may address another slave. Some time later the master sends a start or restart condition, and a valid slave address is sent, followed by a read. The SC900 I2C then acknowledges and returns the data at the register address location that had previously been set up. I2C I2C Stop Stop Separated Format - Read Register Address Setup Access S Slave Address AW A Register Address Master Addresses other Slaves A P S Slave Address B Register Read Access S/ Sr Slave Address AR A Data B P S : Start Condition Slave Address : 7 bit W: Write = '0' Register Address : 8 bit R : Read = '1' Data : 8 Bit A : Acknowledge (sent by slave) B : Acknowledge (sent by master) Sr: Repeated Start Condition P : Stop Condition 2005 Semtech Corp. 15 www.semtech.com SC900 POWER MANAGEMENT Timing Diagrams ARST & LDOPGD Timing LDO A: VOUTA VTH(A) VTH(A) TRD VARST 90% VARST 10% VARST LDO A, C, D, & E: VOUT VTH VTH TPGD VLDOPGD 90% VLDOPGD 10% VLDOPGD LDO On/Off Control via the I2C Interface STOP START STOP SCL SDA VLDOn 40us 2005 Semtech Corp. 300us 16 www.semtech.com SC900 POWER MANAGEMENT Timing Diagram Default Start-Up, Shut-Down Timing Diagram Enable VREF LDO A LDO B LDO C LDO D LDO E ARST LDOPGD 200us 15ms 100ms 100ms 15ms 2005 Semtech Corp. 17 www.semtech.com SC900 POWER MANAGEMENT Typical Characteristics Dropout Voltage (LDOB-E) Dropout Voltage (LDOA) 180 180 160 160 140 TA = 85°C 120 Dropout Voltage (V) Dropout Voltage (V) 140 TA = -40°C 100 80 TA = 25°C 60 120 TA = 85°C 100 TA = 25°C 80 60 40 40 20 20 0 TA = -40°C 0 0 25 50 75 100 125 150 175 0 200 25 50 75 Load Regulation (LDOA-E) -0.5 6 Output Voltage Variation (mV) Output Voltage Variation (mV) 7 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 50 150 VIN(MIN) < VIN < 5.5V 0 25 125 Line Regulation (LDOA-E) TA = 25°C, VIN = 3.7V 0 100 Load Current (mA) Load Current (mA) 75 100 Load Current (mA) 125 5 4 3 2 1 0 1.4 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Output Voltage (V) Output Noise vs. Load Current (LDOA-E) 60 VOUT = 2.5V Output Noise (µV) 50 40 VOUT = 3.0V 30 20 10 0 0 25 50 75 100 125 150 175 200 Load Current (mA) 2005 Semtech Corp. 18 www.semtech.com SC900 POWER MANAGEMENT Typical Characteristics Load Transient (LDOA-E) Line Transient VIN = 3.7V, Io = 10mA to 150mA step VIN = 3.7V, Io = 100mA VIN 500mV/div Vo 20mV/div Vo 10mV/div Io 100mA/div 100µs/div 2005 Semtech Corp. 1ms/div 19 www.semtech.com SC900 PROBE A PROBE B PROBE C PROBE D PROBE E J1 LDOA J2 LDOB J3 LDOC J4 LDOD J5 LDOE 1 1 1 1 SC900 PWR 1 POWER MANAGEMENT Evaluation Board TP1 1 AM1 R1 150 R2 150 R3 0 TP2 D2 ARST 1 TP8 TP7 ARST LDOPGD AM2 1 1 R4 7.5K U1 TP3 SCLK TP4 SDAT 1 1 Q2 FMMT3904 13 19 2 17 14 5 9 10 3 4 6 12 VIN INA INB INCD INE EN LDOPGD ARST SDA SCL A0 GND LDOA LDOB LDOC LDOD LDOE VREF VASEL DGND SC900 20 1 18 16 15 11 C2 0.1uF 8 7 R6 100K R7 2 1 4.75k 6 C11 SC900 Power Select 0.1uF +5V USB J11 1 2 3 4 R12 150 R13 150 D4 EXTERNAL D5 USB F1 1A R14 100K R15 100K +5V USB BOARD APPLICATION I.D. 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 C7 2.2uF J7 GND J8 GND R10 SC900 PWR 100K SW1 R18 100K (No-Pop) SC900 PWR 150 R11 100K U2 SC900 PWR SC900 PWR VASEL TP6 VASEL R9 C8 10uF EXTERNAL SUPPLY C6 2.2uF 1 TP5 A0 4.75k R8 1 2 C5 2.2uF TP9 ENABLE SC900 PWR SC900 PWR J9 C4 2.2uF J6 1 +5V EXTRNAL C3 2.2uF 1 VIN INA INB INCD INE R5 7.5K 1 Q1 FMMT3904 1 D1 LDOPGD P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D C2CK/RST VREGIN VBUS DD+ GND 18 17 16 15 14 13 12 11 R17 0 D3 ENABLE SC900 PWR 1 U3 5 2 3 J10 10 9 4 NC7S04 C2DAT 1 C2CLK 2 3 C10 0.1uF PROGRAM & DEBUG 7 8 5 4 3 R16 150 C8051F320 C12 4.7uF C13 1uF D6 USB BUS USB VIN INA C1 1uF 2005 Semtech Corp. INB C9 1uF 20 INCD C14 1uF INE C15 1uF C16 1uF www.semtech.com SC900 POWER MANAGEMENT Evaluation Board Gerbers Top Gerber Top Silk Screen Gerber Bottom Gerber Bottom Silk Screen Gerber 2005 Semtech Corp. 21 www.semtech.com SC900 POWER MANAGEMENT Outline Drawing - MLPQ-20L 4 x 4 A D B DIM PIN 1 INDICATOR (LASER MARK) A A1 A2 b D D1 E E1 e L N aaa bbb E A2 A DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .020 BSC .011 .016 .020 20 .004 .004 0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 20 0.10 0.10 SEATING PLANE aaa C A1 C D1 LxN E/2 E1 2 1 N bxN bbb C A B e D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Marking Information SC900 yyww xxxxx xxxxx yy = two digit year of manufacture ww = two digit week of manufacture xxxxx = lot number 2005 Semtech Corp. 22 www.semtech.com SC900 POWER MANAGEMENT Land Pattern - MLPQ-20L 4 x 4 K DIMENSIONS (C) G H Z Y DIM C G H K P X Y Z INCHES (.155) .122 .106 .106 .021 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80 X P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804 Visit us at: www.semtech.com 2005 Semtech Corp. 23 www.semtech.com