FAIRCHILD SG6742HL

SG6742HL/HR
Highly Integrated Green-Mode PWM Controller
Features
Description
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The highly integrated SG6742HL/HR PWM controller
provides several features to enhance the performance
of flyback converters.
High-Voltage Startup
Low Operating Current: 2.7mA
Linearly Decreasing PWM Frequency to 22KHz
Frequency Hopping to Reduce EMI Emission
Fixed PWM Frequency: 100KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Open-Loop Protection
GATE Output Maximum Voltage Clamp: 18V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OVP, OTP)
Internal-Sense, Short-Circuit Protection
Built-in 6ms Soft-Start Function
Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ
ƒ
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
linearly decrease the switching frequency at light-load
conditions. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 22KHz. This
green-mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss
due to bleeding resistors is eliminated. To further
reduce power consumption, SG6742HL/HR is
manufactured using the BiCMOS process, which allows
an operating current of 2.7mA.
SG6742HL/HR integrates a frequency-hopping function
internally that helps reduce EMI emission of a power
supply with minimum line filters. Its built-in synchronized
slope compensation achieves stable peak-current-mode
control. The proprietary, internal line compensation
ensures constant output power limit over a wide AC
input voltage range, from 90VAC to 264VAC.
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
April 2009
SG6742HL/HR provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, when the controller starts up again. As long as VDD
exceeds ~25V, the internal OVP circuit is triggered.
SG6742HL/HR is available in an 8-pin SOP package.
Power Adapters
Open-Frame SMPS
Ordering Information
Part
Number
Operating
Temperature
Range
OLP
Function
Package
Eco
Status
Packing
Method
SG6742HLSY
-40 to +105°C
Latch
8-Lead Small Outline Package (SOP)
Green
Tape & Reel
SG6742HRSY
-40 to +105°C
Restart
8-Lead Small Outline Package (SOP)
Green
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
Figure 1. Typical Application
Internal Block Diagram
SG6742HL
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Application Diagram
SG6742HR
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
2
F - Fairchild Logo
Z - Plant Code
X - 1-Digit Year Code
Y - 1-Digit Week Code
TT - 2-Digit Die Run Code
T - Package Type (S=SOP)
P - Y: Green Package
M - Manufacture Flow Code
ZXYTT
6742HL
TPM
ZXYTT
6742HR
TPM
Figure 3. Top Mark
Pin Configuration
SOP-8
GND
1
8
GATE
FB
2
7
VDD
NC
3
6
SENSE
HV
4
5
RT
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Marking Information
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
GND
2
FB
3
NC
No connection.
4
HV
For startup, this pin is pulled high to the line input or bulk capacitor via resistors.
5
RT
For over-temperature protection, an external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched.
6
SENSE
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
7
VDD
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
8
GATE
Ground.
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
The totem-pole output driver. Soft driving waveform is implemented for improved EMI.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
(1, 2)
Max.
Unit
30
V
VVDD
DC Supply Voltage
VFB
FB Pin Input Voltage
-0.3
7.0
V
SENSE Pin Input Voltage
-0.3
7.0
V
VRT
RT Pin Input Voltage
-0.3
7.0
V
VHV
HV Pin Input Voltage
500
V
PD
Power Dissipation (TA＜50°C)
400
mW
ΘJA
Thermal Resistance (Junction-to-Air)
141
°C/W
TJ
Operating Junction Temperature
-40
+125
°C
Storage Temperature Range
-55
+150
°C
+260
°C
VSENSE
TSTG
TL
ESD
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Human Body Model,
JEDEC:JESD22-A114
All pins except HV pin
4.0
Charged Device Model,
JEDEC:JESD22-C101
All pins except HV pin
1.5
kV
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
22
V
V
VDD Section
VOP
VDD-ON
VDD-OFF
Continuously Operating Voltage
Start Threshold Voltage
Minimum Operating Voltage
IDD-ST
Startup Current
VDD-ON – 0.16V
IDD-OP
Operating Supply Current
VDD=15V, GATE Open
VTH-OLP+0.1V
14.5
15.5
16.5
8.5
9.5
10.5
V
30
µA
3.7
mA
2.7
IDD-OLP
Internal Sink Current
30
60
90
µA
VTH-OLP
IDD-OLP off Voltage
6.5
7.5
8.0
V
VDD-OVP
VDD Over-Voltage Protection
24
25
26
V
tD-VDDOVP
VDD Over-Voltage Protection
Debounce Time
75
125
200
µs
1.75
2.30
3.35
mA
1
20
µA
90
100
110
±4.2
±4.7
±5.2
HV Section
IHV
IHV-LC
Supply Current from HV Pin
VAC=90V (VDC=120V),
VDD=0V
Leakage Current After Startup
HV=500V, VDD=VDDOFF+1V
Oscillator Section
Center Frequency
fOSC
Frequency in Normal Mode
tHOP
Hopping Period
4.9
5.6
6.3
ms
Green-Mode Frequency
18
22
25
KHz
fOSC-G
Hopping Range
KHz
fDV
Frequency Variation vs. VDD
Deviation
VDD=11V to 22V
5
%
fDT
Frequency Variation vs.
Temperature Deviation
TA=-40 to 105°C
5
%
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
Continued on the following page…
PWM Frequency
fOSC
fOSC-G
VFB-ZDC VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
5
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
1/4.15
1/4.00
1/3.85
V/V
7
kΩ
5.0
V
Feedback Input Section
AV
Input Voltage to Current-Sense Attenuation
ZFB
Input Impedance
VFB-OPEN
Output High Voltage
VFB-OLP
FB Open-Loop Trigger Level
4
FB Pin Open
5.2
4.6
4.8
V
tD-OLP
Delay Time of FB Pin Open-loop Protection
50
56
62
ms
VFB-N
Green-Mode Entry FB Voltage
3.1
3.3
3.5
V
VFB-G
Green-Mode Ending FB Voltage
VFB-ZDC
VFB-N-
V
1.6
V
0.5
Zero Duty-Cycle Input Voltage
Current-Sense Section
ZSENSE
Input Impedance
VSTHFL
Current Limit Flatten Threshold Voltage
Duty cycle=45%
0.97
1.00
12
1.03
KΩ
V
VSTHVA
Current Limit Valley Threshold Voltage
VSTHFL–VSTHVA
0.27
0.30
0.33
V
tPD
Delay to Output
100
200
ns
tLEB
Leading-Edge Blanking Time
100
140
180
ns
VS-SCP
Threshold Voltage for SENSE Short-Circuit Protection
0.10
0.15
0.20
V
tD-SSCP
Delay Time for SENSE Short-Circuit
Protection
VSENSE<0.15V
100
150
200
µs
Period During Soft-Startup Time
Startup Time
5
6
7
ms
60
65
70
%
1.5
V
tSS
GATE Section
DCYMAX
Maximum Duty Cycle
VGATE-L
Gate Low Voltage
VDD=15V, IO=50mA
VGATE-H
Gate High Voltage
VDD=12V, IO=50mA
8
tr
Gate Rising Time
VDD=15V, CL=1nF
150
250
350
ns
tf
Gate Falling Time
VDD=15V, CL=1nF
30
50
90
ns
Gate Source Current
VDD=15V, GATE=6V
250
mA
VDD=15V, GATE=1V
300
mA
IGATESOURCE
IGATE-SINK Gate Sink Current
VGATECLAMP
V
VDD=22V
Gate Output Clamping Voltage
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
18
V
RT Section
RRT
VRTTH1
VRTTH2
tD-OTP1
tD-OTP2
Internal Resistor from RT Pin
Over-Temperature Protection Threshold
Voltage
Over-Temperature Latch-off Debounce
10.08
10.50
10.92
KΩ
0.7V ＜ VRT ＜ 1.05V,
After 12ms Latch Off
1.015
1.050
1.085
V
VRT ＜ 0.7V, After
100µs Latch Off
0.65
0.70
0.75
V
VRTTH2 ＜ VRT ＜ VRTTH1
16
20
24
ms
VRT< VRTTH2
90
130
170
µs
Over-Temperature Protection Section (OTP)
TOTP
TRestart
Protection Junction Temperature
Restart Junction Temperature
(3)
(4)
+135
°C
TOTP-25
°C
Notes:
3. When activated, the output is disabled and the latch is turned off.
4. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
6
5
20
4
IDD-OP (mA)
IDD_ST (μA)
25
15
10
5
0
-40
3
2
1
-30
-15
0
25
50
75
85
100
0
-40
125
-30
-15
0
Temperature (℃)
12
17
11
VDD-OFF (V)
VDD-ON (V)
18
16
15
14
-30
-15
0
25
50
75
85
100
125
-30
-15
0
25
50
75
85
100
125
Temperature (℃)
Figure 9. Minimum Operating Voltage (VDD-OFF)
vs. Temperature
5
10
4
8
3
6
IHV-LC (μA)
IHV (mA)
100
9
7
-40
125
2
1
4
2
-30
-15
0
25
50
75
85
100
0
-40
125
-30
-15
0
Temperature (℃)
25
50
75
85
100
125
Temperature (℃)
Figure 10. Supply Current Drawn from HV Pin (IHV)
vs. Temperature
Figure 11. HV Pin Leakage Current after Startup
(IHV-LC) vs. Temperature
105
70
103
68
DCYMAX (%)
FOSC (kHz)
85
8
Figure 8. Start Threshold Voltage (VDD-ON)
vs. Temperature
101
99
97
95
-40
75
10
Temperature (℃)
0
-40
50
Figure 7. Operation Supply Current (IDD-OP)
vs. Temperature
Figure 6. Startup Current (IDD-ST) vs. Temperature
13
-40
25
Temperature (℃)
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
66
64
62
-30
-15
0
25
50
75
85
100
60
-40
125
Temperature (℃)
-15
0
25
50
75
85
100
125
Temperature (℃)
Figure 12. Frequency in Normal Mode (fOSC)
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
-30
Figure 13. Maximum Duty Cycle (DCYMAX)
vs. Temperature
www.fairchildsemi.com
7
62
7
60
6
tD-OLP (ms)
VFB-OLP (V)
58
5
56
54
4
52
3
-40
-30
-15
0
25
50
75
85
100
50
-40
125
-30
-15
0
25
Temperature (℃)
Figure 14. FB Open-Loop Trigger Level (VFB-OLP) vs.
Temperature
99
IRT (μA)
0.145
VS-SCP (V)
100
0.14
0.135
85
100
125
98
97
0.13
-40
-30
-15
0
25
50
75
85
100
96
-40
125
-30
-15
0
Temperature (℃)
25
50
75
85
100
125
Temperature (℃)
Figure 16. Threshold Voltage for SENSE Short-Circuit
Protection (VS-SCP) vs. Temperature
Figure 17. Output Current from RT Pin (IRT)
vs. Temperature
0.9
1.1
0.8
VRTTH2 (V)
1.2
VRTTH1 (V)
75
Figure 15. Delay Time of FB Pin Open-Loop Protection
(tD-OLP) vs. Temperature
0.15
1
0.9
0.8
-40
50
Temperature (℃)
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
0.7
0.6
-30
-15
0
25
50
75
85
100
0.5
-40
125
Temperature (℃)
-30
-15
0
25
50
75
85
100
125
Temperature (℃)
Figure 18. Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature
Figure 19. Over-Temperature Protection Threshold
Voltage (VRTTH2) vs. Temperature
28
VDD-OVP (V)
27
26
25
24
23
-40
-30
-15
0
25
50
75
85
100
125
Temperature (℃)
Figure 20. VDD Over-Voltage Protection (VDD-OVP)
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
8
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, (1N4007 / 100KΩ recommended). Typical startup
current drawn from pin HV is 2.3mA and charges the
hold-up capacitor through the diode and resistor. When
the VDD capacitor level reaches VDD-ON, the startup
current switches off. At this moment, the VDD capacitor
only supplies the SG6742HL/HR to keep the VDD before
the auxiliary winding of the main transformer to provide
the operating current.
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 6ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Operating Current
Operating current is around 2.7mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
SG6742HL/HR inserts a synchronized positive-going
ramp at every switching cycle.
Green-Mode Operation
The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in
the light-load and no-load conditions. The on time is
limited for better abnormal or brownout protection. VFB,
which is derived from the voltage feedback loop, is
taken as the reference. Once VFB is lower than the
threshold voltage, switching frequency is continuously
decreased to the minimum green-mode frequency of
around 22KHz.
Constant Output Power Limit
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and VFB, the feedback voltage.
When the voltage on SENSE pin reaches around
VCOMP=(VFB–0.6)/4, a switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.85V for output power limit.
When the SENSE voltage, across the sense resistor
RS, reaches the threshold voltage, around 1V, the
output GATE drive is turned off after a small delay, tPD.
This delay introduces an additional current proportional
to tPD • VIN / LP. Since the delay is nearly constant
regardless of the input voltage VIN, higher input voltage
results in a larger additional current and the output
power limit is higher than under low input line voltage.
To compensate this variation for wide AC input range, a
sawtooth power-limiter is designed to solve the unequal
power-limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
Leading-Edge Blanking (LEB)
VDD Over-Voltage Protection (OVP)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
VDD over-voltage protection has been built in to prevent
damage due to abnormal conditions. If the VDD voltage
is over the over-voltage protection voltage (VDD-OVP) and
lasts for tD-VDDOVP, the PWM pulses are disabled until
the VDD voltage drops below the UVLO, then starts
again. Over-voltage conditions are usually caused by
open feedback loops.
Current Sensing / PWM Current Limiting
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Functional Description
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 15.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 15.5V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply VDD before the energy can be delivered from
auxiliary winding of the main transformer. VDD must not
drop below 9.5V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply VDD during startup.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
9
Thermal Protection
Noise Immunity
An NTC thermistor, RNTC, in series with a resistor RA,
can be connected from the RT pin to ground. A
constant current IRT is output from the RT pin. The
voltage on the RT pin can be expressed as VRT = IRT •
(RNTC + RA), where IRT is 100µA. At high ambient
temperatures, RNTC is smaller, such that VRT decreases.
When VRT is less than 1.05V (VRTTH1), the PWM turns
off after 20ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2),
PWM turns off immediately after 130µs (tD-OTP2).
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the SG6742HL/HR, and increasing
the power MOS gate resistance improve performance.
Limited Power Control
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned off, VDD begins decreasing.
When VDD goes below the turn-off threshold (~9.5V) the
controller is totally shut down. VDD is charged up to the
turn-on threshold voltage of 15.5V through the startup
resistor until PWM output is restarted. This protection
feature continues as long as the overloading condition
persists. This prevents the power supply from
overheating due to overloading conditions. When VRT is
less than 1.05V (VRTTH1), the PWM is turned off after
20ms (tD-OTP1). If VRT is less than 0.7V (VRTTH2), PWM is
turned off immediately after 130µs (tD-OTP2).
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
www.fairchildsemi.com
10
2
F1
T1
C6
4
2
4
L1
1
VZ1
1
2
3
C1
4
C2
1
4
T2
8
2
2
5
R1
C5
+
Q1
1
L2
VO+
1
2
1
6
2
2
2
3
2
C3
VO+
2
C4
+
D4
4
3
1
3
3
1
CN1
R2
BD1
2
CN1
L3
+
D1
C8
1
2
7
3
1
3
D2
1
1
1
C7
2
VO-
2
R3
R4
Q2
3
1
D3
2
2
1
+
U1
1
SG6742MR
8
1
GND GATE
C9
2
C12
3
4
FB
VDD
NC
SENSE
HV
RT
7
R5
6
5
R6
C10
R7
R8
1
4
THER1
U2
VO+
R9
2
K
3
R10
C11
R
U3
A
R11
Figure 21. 60W Flyback 12V/5A Application Circuit
BOM
Designator
Part Type
Designator
BD1
BD 4A/600V
L3
C1
Part Type
Inductor (900µH)
XC 0.68µF/300V
Q1
STP20-100CT
C2
XC 0.1µF/300V
Q2
MOS 7A/600V
C3
YC 2200pF/Y1
R1
R 100KΩ 1/2W
C4
EC 120µF/400V
R2
R 47Ω 1/4W
C5
CC 0.01µF/500V
R3
R 100KΩ 1/2W
C6
CC 1000pF/100V
R4
R 4.7Ω 1/8W
C7
EC 1000µF/25V
R5
R 100Ω 1/8W
C8
EC 470µF/25V
R6, R9
R 4.7KΩ 1/8W
C9
EC 22µF/50V
R7
R 0.3Ω 2W
C10
CC 47pF/50V
R8
R 680Ω 1/8W
C11
CC 2200pF/50V
R10
R 150KΩ 1/8W
C12
CC 0.01µF/50V
R11
R 39KΩ 1/8W
D1
Zener Diode 15V 1/2W (option)
THER1
Thermistor TTC104
D2
BYV95C
T1
10mH
D3
FR103
T2
255µH(PQ2620)
D4
1N4007
U1
IC SG6742
F1
FUSE 4A/250V
U2
IC PC817
L1
Inductor (900µH)
U3
IC TL431
L2
Inductor (2µH)
VZ1
VZ 9G
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Applications Information
www.fairchildsemi.com
11
5.00
4.80
A
0.65
3.81
8
5
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
Physical Dimensions
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 22. 8-Pin SOP-8 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
12
SG6742HL/HR — Highly Integrated Green-Mode PWM Controller
© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
www.fairchildsemi.com
13