FAIRCHILD FAN6300SY

FAN6300
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
Description
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The highly integrated FAN6300 PWM controller
provides several features to enhance the performance
of flyback converters. A built-in HV startup circuit can
provide more startup current to reduce the startup time
of the controller. Once the VDD voltage exceeds the
turn-on threshold voltage, the HV startup function is
disabled immediately to improve power consumption.
An internal valley voltage detector ensures the power
system operates at Quasi-Resonant operation in widerange line voltage and any load conditions and reduces
switching loss to minimize switching voltage on drain of
power MOSFET.
High-Voltage Startup
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking
Internal Minimum tOFF
Internal 2ms Soft-Start
Over-Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Short-Circuit Protection (FB Pin)
Auto-Recovery Open-Loop Protection (FB Pin)
VDD Pin & Output Voltage (DET Pin) OVP Latched
FAN6300 controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as VDD drops below
the turn-off threshold voltage, controller also disables
PWM output. The gate output is clamped at 18V to
protect the power MOS from high gate-source voltage
conditions. The minimum tOFF time limit prevents the
system frequency from being too high. If the DET pin
reaches OVP, internal OTP is triggered, and the power
system enters latch-mode until AC power is removed.
Applications
ƒ
ƒ
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage.
AC/DC NB Adapters
Open-Frame SMPS
FAN6300 controller is available in 8-pin SOP and DIP
packages.
Ordering Information
Part Number
Operating
Temperature Range
FAN6300SY
-40 to +105°C
FAN6300DY
-40 to +105°C
Package
Packing Method
Green
8-Lead, Small Out-line Package
(SOP)
Tape & Reel
Green
8-Lead, Dual In-line Package
(DIP)
Tube
Eco Status
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
October 2008
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
HV
VDD
8
6
FB
2
27V
2R
Soft-Start
2ms
R
Timer
55ms
Internal
Bias
OVP
IHV
4.2V
Latched
Two Steps
UVLO
16V/10V/8V
FB OLP
500µs
30µs
Starter
CS
3
DRV
Blanking
Circuit
S
PWM
Current Limit
Over-Power
Compensation
SET
5
Q
GATE
18V
R
IDET
CLR
Q
Latched
0.3V
tOFF-MIN
(8µs/38µs)
tOFF
Blanking
(4µs)
S/H
Valley
Detector
VDET
1st
Valley
tOFF-MIN
+9µs
VDET
Latched
2.5V
DET OVP
DET
1
Internal
OTP
0.3V
5V
IDET
Latched
4
7
GND
NC
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
2
: Fairchild logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package type (D =DIP, S = SOP)
P: Y = Green Package
M: Manufacturing flow code
Figure 3. Marking Diagram
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Marking Information
- Generates a ZCD signal once the secondary-side switching current falls to zero.
1
DET
- Produces an offset voltage to compensate the threshold voltage of the peak current limit to
provide a constant power limit. The offset is generated in accordance with the input voltage
when PWM signal is enabled.
- Detects the valley voltage of the switching waveform to achieve the valley voltage switching
and minimize the switching losses.
A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The
ratio of the divider decides what output voltage to stop gate, as an optical coupler and
secondary shunt regulator are used.
The Feedback pin is supposed to be connected to the output of the error amplifier for achieving
the voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.
2
FB
For the primary-side control application, this pin is applied to connect a RC network to the
ground for feedback-loop compensation.
The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop gain attenuation.
FAN6300 performs an open-loop protection once the FB voltage is higher than a threshold
voltage (around 4.2V) more than 55ms.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
3
Name
Description
3
CS
4
GND
The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and
GND is recommended.
5
GATE
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18V.
6
VDD
7
NC
No connect.
8
HV
High-voltage startup.
Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The threshold
voltage for peak current limit is 0.8V.
Power supply. The threshold voltages for startup and turn-off are 16V and 10V. The startup
current is less than 20µA and the operating current is lower than 4.5mA.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Pin #
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
DC Supply Voltage
Max.
Unit
30
V
VHV
HV Pin
500
V
VH
GATE Pin
-0.3
25.0
V
VL
VFB, VCS, VDET
-0.3
7.0
V
PD
Power Dissipation
TJ
Operating Junction Temperature
TSTG
TL
ESD
Storage Temperature Range
-55
Lead Temperature, Soldering 10 Seconds
400
mW
+150
°C
+150
°C
+270
°C
Human Body Model, JEDEC:JESD22-A114
2.5
Charged Device Model, JEDEC:JESD22-C101
1.5
KV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
Min.
Max.
Unit
-40
+105
°C
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
5
VDD=15V, TA=25℃, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
25
V
VDD SECTION
VOP
Continuously Operating Voltage
VDD-ON
Turn-on Threshold Voltage
15
16
17
V
VDD-PWM-OFF
PWM Off Threshold Voltage
9
10
11
V
VDD-OFF
Turn-Off Threshold Voltage
7
8
9
V
IDD-ST
Startup Current
0V< VDD < VDD-ON
GATE Open
10
30
µA
IDD-OP
Operating Current
VDD=15V, fs=60KHz,
CL=2nF
4.5
5.5
mA
Operating Current at PWM-Off Phase
VDD=VDD-PWM-OFF-0.5V
70
80
90
µA
IDD-PWM-OFF
VDD-OVP
VDD Over-Voltage Protection (Latch-Off)
26
27
28
V
tVDD-OVP
VDD OVP Debounce Time
100
150
200
µs
HV STARTUP CURRENT SOURCE SECTION
IHV
IHV-LC
Supply Current Drawn From HV Pin
VAC=90V (VDC=120V),
VDD=0V
Leakage Current After Startup
HV=500V,
VDD=VDD-OFF +1V
1.2
mA
1
20
µA
1/2.75
1/3.00
1/3.25
V/V
3
5
7
KΩ
1.2
2.0
mA
FEEDBACK INPUT SECTION
AV
Input-voltage to Current Sense
Attenuation
ZFB
Input Impedance
IOZ
Bias Current
VOZ
Zero Duty Cycle Input Voltage
VFB-OLP
Open-Loop Protection Threshold
Voltage
tD-OLP
Debounce Time for Open-Loop /
Overload Protection
tSS
AV=ΔVCS/ΔVFB
0<VCS<0.9
FB=VOZ
1
3.9
4.2
V
4.5
V
55
Internal Soft-Start Time
ms
1.6
2.0
2.4
ms
Comparator Reference Voltage
2.45
2.50
2.55
V
VV-HIGH
Output High Voltage
4.5
VV-LOW
Output Low Voltage
tDET-OVP
Output OVP (Latched) Debounce Time
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics
DET PIN OVP AND VALLEY DETECTION SECTION
VDET-OVP
IDET-SOURCE
100
V
150
0.5
V
200
µs
Maximum Source Current
1
mA
VDET-HIGH
Upper Clamp Voltage
5
V
VDET-LOW
Lower Clamp Voltage
tOFF-BNK
Leading-Edge Blanking Time for DET(3)
OVP, PWM MOS Turns Off
0.1
0.3
V
4
µs
Note:
3. Guaranteed by design.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
6
VDD=15V, TA=25℃, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
38
45
52
µs
7
8
9
µs
OSCILLATOR SECTION
tON-MAX
Maximum On Time
tOFF-MIN
Minimum Off Time
(Maximum Frequency)
VFB≧VN
VFB=VG
38
µs
VN
Beginning of Green-On Mode
at FB Voltage Level
1.95
2.10
2.25
V
VG
Beginning of Green-Off Mode
at FB Voltage Level
1.05
1.20
1.35
V
ΔVFBG
Green-Off Mode VFB Hysteresis
Voltage
tSTARTER
Start Timer (Time-out Timer)
tTIME-OUT
Timeout After tOFF-MIN
(If No Valley Signal)
0.1
V
VFB<VG
450
550
650
µs
VFB>VFB-OLP
25
30
35
µs
9
µs
OUTPUT SECTION
VOL
Output Voltage Low
VDD=15V, IO=150mA
VOH
Output Voltage High
VDD=12V, IO=150mA
tR
tF
VCLAMP
1.5
7.5
Rising Time
V
120
Falling Time
ns
60
GATE Output Clamping Voltage
17
V
ns
18
19
V
150
250
ns
CURRENT SENSE SECTION
tPD
VLIMIT
VSLOPE
tBNK
Delay to Output
Cycle-by-Cycle Current Limit
Threshold Voltage
Slope Compensation
IDET = 60µA
0.74
0.78
0.82
V
IDET = 175µA
0.545
0.585
0.625
V
IDET = 220µA
0.42
0.46
0.50
V
tON=45µs
0.3
V
tON=0µs
0.1
V
Leading Edge Blanking Time
(MOS Turns On)
225
VCS-H
VCS Camped High Voltage
CS Pin Floating
4.5
tCS-H
Delay Time
CS Pin Floating
100
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
300
150
375
ns
5.0
V
200
µs
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
7
These characteristic graphs are normalized at TA = 25°C.
17.0
10.5
10.3
V DD-P WM-OFF (V)
V DD-ON (V)
16.5
16.0
15.5
10.1
9.9
9.7
15.0
9.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
50
65
80
95
110
125
Figure 6. PWM Off Threshold Voltage
8.2
10
8.1
9
8.0
8
7.9
7.8
7
6
5
7.6
4
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
Temperature℃
Temperature℃
Figure 7. Turn-off Threshold Voltage
Figure 8. Startup Current
5.2
2.2
5.0
2.0
4.8
1.8
IHV (mA)
IDD-OP (mA)
35
Figure 5. Turn-on Threshold Voltage
7.7
4.6
4.4
4.2
110
125
110
125
1.6
1.4
1.2
4.0
1.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
Temperature℃
Temperature℃
Figure 9. Operating Current
Figure 10. Supply Current Drawn From HV Pin
0.30
1.0
V DE T-LOW (V)
0.8
IHV-LC (uA)
20
Temperature℃
IDD-S T (uA)
V DD-OFF (V)
Temperature℃
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Typical Performance Characteristics
0.6
0.4
0.25
0.20
0.15
0.2
0.0
0.10
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
Temperature℃
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Figure 11. Leakage Current After Startup
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
-25
Figure 12. Lower Clamp Voltage
www.fairchildsemi.com
8
2.6
9.0
2.6
8.5
tOFF-MIN (us)
V DE T-OVP (V)
These characteristic graphs are normalized at TA = 25°C.
2.5
2.5
8.0
7.5
2.4
7.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 13. Comparator Reference Voltage
Figure 14. Minimum Off Time (VFB>VN)
600
40
575
tS TAR TE R (us)
tOFF-MIN (us)
39
38
37
36
550
525
500
475
35
450
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
-25
-10
5
20
35
50
65
80
95
110
Temperature℃
Temperature℃
Figure 15. Minimum Off Time (VFB=VG)
Figure 16. Start Timer (VFB<VG)
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
125
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Typical Performance Characteristics
www.fairchildsemi.com
9
The FAN6300 of PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation in a wide
range of line voltage. The following descriptions highlight
some of the features of the FAN6300 series.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, which are recommended as 1N4007 and 100kΩ.
Typical startup current drawn from pin HV is 1.2mA and
it charges the hold-up capacitor through the diode and
resistor. When the VDD voltage level reaches VDD-ON, the
startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6300 to maintain VDD
until the auxiliary winding of the main transformer
provides the operating current.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 19, once VFB is lower than VN, the tOFF-MIN time
increases linearly with lower VFB. The valley voltage
detection signal does not start until the tOFF-MIN time
finishes. Therefore, the valley detect circuit is activated
until the tOFF-MIN time finishes, which decreases the
switching frequency and provides extended valley
voltage switching. However, in very light load condition,
it might fail to detect the valley voltage after the tOFF-MIN
expires. Under this condition, an internal tTIME-OUT signal
initiates a new cycle start after a 9μs delay. Figure 20
and Figure 21 show the two different conditions.
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors RDET and RA. RDET is recommended as
150kΩ to 220kΩ to achieve valley voltage switching.
When VAUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3V.
Figure 19. VFB vs. tOFF-MIN Curve
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Operation Description
Figure 17. Valley Detect Section
The internal timer (minimum tOFF time) prevents gate
retriggering within 8µs after the gate signal going-low
transition. The minimum tOFF time limit prevents the
system frequency being too high. Figure 18 shows a
typical drain voltage waveform with first valley switching.
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
Figure 18. First Valley Switching
Figure 21. Internal tTIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage (with 9µs Delay)
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
10
VDD Over-Voltage Protection
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current sense signal and VFB. When the voltage on CS
pin reaches around VLIMIT = (VFB-1.2)/3, the switch cycle
is terminated immediately. VLIMIT is internally clamped to
a variable voltage around 0.8V for output power limit.
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
VDD over-voltage protection voltage (VDD-OVP) and lasts
for tVDDOVP, controller enters latch mode and stops all
switching operation.
Leading Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking
time is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs blanking time ignores the leakage
inductance ringing. A voltage comparator and a 2.5V
reference voltage develop an output OVP protection.
The ratio of the divider determines the sampling voltage
of the stop gate, as an optical coupler and secondary
shunt regulator are used. If the DET pin OVP is
triggered, power system enters latch-mode until AC
power is removed.
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply VDD during startup.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Over-Power Compensation
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of RDET is higher. RDET
also affects the H/L line constant power limit.
Figure 23. Voltage Sampled After 4μs Blanking Time
After Switch-off Sequence
Short-Circuit and Open-Loop Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned-off, the supply voltage VDD begins decreasing.
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Current Sensing and PWM Current Limiting
When VDD goes below the PWM-off threshold of 10V,
VDD decreases to 8V, then the controller is totally shut
down. VDD is charged up to the turn-on threshold voltage
of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
11
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Physical Dimensions
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
Figure 24. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
12
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Physical Dimensions (Continued)
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
5.08 MAX
7.62
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 25. 8-Pin Dual Inline Package (DIP-8)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
13
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
14