Si52147 PCI-E XPRESS G EN 1, G EN 2, & G EN 3 N IN E O UTPUT C L O C K G ENERATOR Features Ordering Information: See page 20. 42 41 SCLK 43 SDATA 44 VDD_CORE 45 40 39 38 37 36 DIFF8 VDD 2 35 DIFF8 OE0 1 3 34 VDD OE1 1 4 33 DIFF7 SSON 2 5 VSS_PLL3 6 VSS_PLL4 7 OE2 1 8 49 GND 32 DIFF7 31 DIFF6 30 DIFF6 29 VDD 28 DIFF5 27 DIFF5 DIFF4 VDD 12 25 DIFF4 13 14 15 16 17 18 19 20 21 22 23 24 VSS 26 VDD 11 DIFF3 OE[6:8] 1 DIFF3 9 10 DIFF2 OE3 1 OE[4:5] 1 DIFF2 Functional Block Diagram 46 1 DIFF1 The Si52147 is a spread-controlled PCIe clock generator that can source nine PCIe clocks simultaneously. The device has six hardware output enable control inputs for enabling the respective differential outputs on the fly while powered on along with the hardware spread control for EMI reduction. 47 VDD VSS Description 48 CKPWRGD_PDB1 Wireless access point Routers DIFF1 DIFF0 NC Network attached storage Multi-function printer VDD DIFF0 XOUT Pin Assignments Applications XIN NC NC I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature: –40 to 85 oC 3.3 V power supply 48-pin QFN package VSS_CORE 25 MHz crystal input or clock input NC PCI-Express Gen 1, Gen 2, & Gen 3 compliant Low power push-pull type differential output buffers Integrated resistors on differential clocks Output enable pin for all clocks Hardware selectable spread control Nine PCI-Express clocks VSS_PCI Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Patents pending DIFF0 XIN/CLKIN DIFF1 XOUT DIFF2 DIFF3 PLL1 (SSC) Divider DIFF4 DIFF5 DIFF6 SCLK SDATA CKPWRGD/PDB OE [8:0] Control & Memory DIFF7 Control RAM SSON Preliminary Rev. 0.1 12/11 DIFF8 Copyright © 2011 by Silicon Laboratories Si52147 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si52147 2 Preliminary Rev. 0.1 Si52147 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Preliminary Rev. 0.1 3 Si52147 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ±5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (SE) VOH IOH = –1 mA 2.4 — — V 3.3 V Output Low Voltage (SE) VOL IOL = 1 mA — — 0.4 V High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH Power Down Current IDD_PD — — 1 mA Dynamic Supply Current IDD_3.3V — — 85 mA Output Pin Capacitance Pin Inductance 4 All outputs enabled. Differential clocks with 5” traces and 2 pF load. Preliminary Rev. 0.1 Si52147 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 47 — 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 uA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA TDC Measured at 0 V differential 45 — 55 % Any DIFF Clock Skew from the TSKEW(win Earliest Bank to the Latest dow) Bank Measured at 0 V differential — — 50 ps DIFF Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps Output PCIe Gen1 REFCLK Phase Jitter RMSGEN1 Includes PLL BW 1.5–22 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz with BER = 1E-12 0 40 108 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns, Low Band, F < 1.5 MHz 0 2 3.0 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns, High Band,1.5 MHz < F < Nyquist 0 2 3.1 ps Output Phase Jitter Impact— PCIe Gen3 RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz 0 0.5 1.0 ps DIFF Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm DIFF Rising/Falling Slew Rate TR/TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle DIFF at 0.7 V DIFF Duty Cycle Crossing Point Voltage at 0.7 V Swing Enable/Disable and Setup Preliminary Rev. 0.1 5 Si52147 Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 22 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 30 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) V–0 MSL JEDEC (J-STD-020) 2 Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 Preliminary Rev. 0.1 Si52147 2. Functional Description 2.1. Crystal Recommendations The clock device requires a parallel resonance crystal. Substituting a series resonance crystal causes the clock device to operate at the wrong frequency and violates the ppm specification. For most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. Figure 1. Crystal Capacitive Clarification 2.1.2. Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Preliminary Rev. 0.1 7 Si52147 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci : Internal capacitance (lead frame, bond wires, etc.) CLe: 2.2. CKPWRGD_PDB (Power down) Clarification The CKPWRGD_PDB pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Upon the first powerup if the CKPWRGD is low, the device outputs will be disabled, but the crystal oscillator and I2C logics are active. Once CKPWRGD has been sampled high by the clock chip, the pin assumes a PDB functionality. When the pin has assumed a PDB functionality and the pin is pull low, the device will be placed in standby mode. 2.3. PDB (Power down) Assertion The PDB pin is an asynchronous active low input used to disable all clocks in a glitch free manner. All outputs will be driven low in power down mode. In power down mode, all outputs, the crystal oscillator and the I2C logic are disabled. 2.4. PDB Deassertion When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch free manner within two to six output clock cycle. 2.5. OE Clarification The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins is required to be driven at all time and even though it has an internally 100 k resistor. 2.6. OE Assertion The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.7. OE Deassertion When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the final output state is driven low. 2.8. SSON Clarification SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread. 8 Preliminary Rev. 0.1 Si52147 3. Test and Measurement Setup This diagram shows the test load configuration for the differential clock signals. M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" O U T- M e a s u re m e n t P o in t L1 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration Figure 4. Differential Output Signals (for AC Parameters Measurement) Preliminary Rev. 0.1 9 Si52147 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) 10 Preliminary Rev. 0.1 Si52147 4. Control Registers 4.1. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. 4.2. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1 on page 4. The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address—7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Command Code–8 bits Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Preliminary Rev. 0.1 11 Si52147 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address–7 bits Byte Read Protocol Bit 1 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Preliminary Rev. 0.1 Si52147 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W D2 D1 D0 DIFF1_OE DIFF2_OE DIFF3_OE R/W R/W R/W Name Type Reset settings = 00000000 Bit Name 7:0 Reserved Function Control Register 1. Byte 1 Bit D7 D6 D5 D3 DIFF0_OE Name Type D4 R/W R/W R/W R/W R/W Reset settings = 00010111 Bit Name 7:5 Reserved 4 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 3 Reserved 2 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 1 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 0 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. Preliminary Rev. 0.1 13 Si52147 Control Register 2. Byte 2 Bit D7 D6 D5 D4 D3 Name DIFF4_OE DIFF5_OE DIFF6_OE DIFF7_OE DIFF8_OE Type R/W R/W R/W R/W R/W Reset settings = 11111000 Bit Name 7 DIFF4_OE Function Output Enable for DIFF4. 0: Output disabled. 1: Output enabled. 6 DIFF5_OE Output Enable for DIFF5. 0: Output disabled. 1: Output enabled. 5 DIFF6_OE Output Enable for DIFF6. 0: Output disabled. 1: Output enabled. 4 DIFF7_OE Output Enable for DIFF7. 0: Output disabled. 1: Output enabled. 3 DIFF8_OE Output Enable for DIFF8. 0: Output disabled. 1: Output enabled. 2:0 14 Reserved Preliminary Rev. 0.1 D2 D1 D0 R/W R/W R/W Si52147 Control Register 3. Byte 3 Bit D7 D6 D4 D3 Rev Code[3:0] Name Type D5 R/W R/W R/W D2 D1 D0 Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W Reset settings = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 BC[7:0] Name Type R/W R/W R/W R/W Reset settings = 00000110 Bit Name 7:0 BC[7:0] Function Byte Count Register. Preliminary Rev. 0.1 15 Si52147 Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W Reset settings = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 16 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Preliminary Rev. 0.1 011: 600 mV 111: 1000 mV Si52147 NC NC VSS_PCI VSS_CORE NC NC XIN XOUT VDD_CORE CKPWRGD_PDB1 SDATA SCLK 5. Pin Descriptions: 48-Pin QFN 48 47 46 45 44 43 42 41 40 39 38 37 VDD 1 36 DIFF8 VDD 2 35 DIFF8 OE0 1 3 34 VDD OE1 1 4 33 DIFF7 SSON 2 5 32 DIFF7 VSS_PLL3 6 31 DIFF6 VSS_PLL4 7 30 DIFF6 OE2 1 8 29 VDD OE3 1 9 28 DIFF5 OE[4:5]1 10 27 DIFF5 OE[6:8]1 11 26 DIFF4 VDD 12 49 GND 16 17 18 19 20 21 DIFF0 DIFF0 VSS DIFF1 DIFF1 DIFF2 DIFF2 DIFF3 22 23 24 VSS 15 VDD 14 DIFF3 13 VDD 25 DIFF4 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Table 7. Part Number 48-Pin QFN Descriptions Pin # Name Type Description 1 VDD PWR 3.3 V Power Supply 2 VDD PWR 3.3 V Power Supply 3 OE0 I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 4 OE1 I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 5 SSON I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks (internal 100 k pull-down) 6 VSS GND Ground Preliminary Rev. 0.1 17 Si52147 Table 7. Part Number 48-Pin QFN Descriptions Pin # Name Type 7 VSS GND Ground 8 OE2 I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 9 OE3 I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 10 OE[4:5] I,PU 3.3 V input to disable DIFF[4:5] (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 11 OE[6:8] I,PU 3.3 V input to disable DIFF[6:8] (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 12 VDD PWR 3.3 V Power Supply 13 VDD PWR 3.3 V Power Supply 14 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 15 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 16 VSS 17 DIFF1 O, DIF 0.7 V, 100 MHz differential clock 18 DIFF1 O, DIF 0.7 V, 100 MHz differential clock 19 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 20 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 21 DIFF3 O, DIF 0.7 V, 100 MHz differential clock 22 DIFF3 O, DIF 0.7 V, 100 MHz differential clock 23 VDD PWR 3.3V Power Supply 24 VSS GND 25 DIFF4 O, DIF 0.7 V, 100 MHz differential clock 26 DIFF4 O, DIF 0.7 V, 100 MHz differential clock 27 DIFF5 O, DIF 0.7 V, 100 MHz differential clock 28 DIFF5 O, DIF 0.7 V, 100 MHz differential clock 29 VSS 30 DIFF6 O, DIF 0.7 V, 100 MHz differential clock 31 DIFF6 O, DIF 0.7 V, 100 MHz differential clock 32 DIFF7 O, DIF 0.7 V, 100 MHz differential clock 33 DIFF7 O, DIF 0.7 V, 100 MHz differential clock 18 VSS GND Description Ground Ground Ground Preliminary Rev. 0.1 Si52147 Table 7. Part Number 48-Pin QFN Descriptions Pin # Name Type Description 34 VDD 35 DIFF8 O, DIF 0.7 V, 100 MHz differential clock 36 DIFF8 O, DIF 0.7 V, 100 MHz differential clock 37 SCLK I 38 SDATA I/O 39 CKPWRGD_PDB I, PU 40 VDD_CORE 41 XOUT O 25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input) 42 XIN/CLKIN I 25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input 43 NC NC No Connect 44 NC NC No Connect 45 VSS_CORE GND Ground 46 VSS GND Ground 47 NC NC No Connect 48 NC NC No Connect 49 GND GND PWR 3.3 V Power Supply SMBus compatible SCLOCK SMBus compatible SDATA 3.3 V CMOS input. A real-time active low input for asserting power down (PDB) and disabling all outputs (internal 100 k pull-up). PWR 3.3 V Power Supply Ground for bottom pad of the IC. Preliminary Rev. 0.1 19 Si52147 6. Ordering Guide Part Number Package Type Temperature Si52147-A01AGM 48-pin QFN Industrial, –40 to 85 C Si52147-A01AGMR 48-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 20 Preliminary Rev. 0.1 Si52147 7. Package Outline Figure 6 illustrates the package details for the Si52147. Table 8 lists the values for the dimensions shown in the illustration. Figure 6. 48-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol Millimeters Min Nom Max 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.15 0.20 0.25 A D D2 6.00 BSC 4.30 4.40 e 0.40 BSC E 6.00 BSC 4.50 E2 4.30 4.40 4.50 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components Preliminary Rev. 0.1 21 Si52147 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Preliminary Rev. 0.1