SL2150D Cable Tuner Front End LNA with AGC Data Sheet Features September 2005 • Single chip dual output LNA • Wide dynamic range on both channels • Independent AGC facility incorporated into all channel paths • Independent disable facility incorporated into all channel paths • Full ESD protection. (Normal ESD handling procedures should be observed) Ordering Information SL2150D/KG/LH1S 28 Pin QFN SL2150D/KG/LH2R 28 Pin QFN* SL2150D/KG/LH2T 28 Pin QFN* *Pb Free Matte Tin -20°C to +85°C Description Applications • The SL2150D is a wide dynamic range front end for tuner applications. Multi-tuner cable set top box and cable modem applications • Data communications systems • Terrestrial TV tuner loop though The device offers two buffered outputs from a single input, where both paths contain an independently controllable AGC and disable facility. AGC1 AGC2 RFOUT1 AGC Control RFINPUT RFINPUTB Tubes Trays Tape & Reel RFOUT1B Power Splitter AGC Control Power Down DIS1 DIS2 Figure 1 - SL2150D Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved. RFOUT2 RFOUT2B Vcc Data Sheet Vcc NC# NC# NC# Vcc Vcc SL2150D Vee Vee Vee Vee RFOUT1 RFOUT2 RFOUT1B RFOUT2B SL2150D Vcc NC# Vcc AGC2 Vcc AGC1 DIS2 DIS1 Vee RF INPUT RF INPUT VEE (PACKAGE PADDLE) Vcc Vcc 1 LH28 # Pins marked NC should be connected to Vee Figure 2 - Pin Allocation 1.0 Quick Reference Data NB all data applies with differential termination and single ended source both of 75 Ω. Characteristics Units RF input operating range 50-860 MHz Gain with external load as in Figure 11 maximum minimum 11 -25 dB dB Input NF, both paths enabled at maximum gain 6.4 dB CTB, both paths enabled, all gain settings * -66 dBc CSO, both paths enabled, all gain settings * -64 dBc CXM, both paths enabled, all gain settings * -60 dBc Input impedance 75 Ω Input VSWR 8 dB Output impedance differential, all loops (requires external load for example as in Figure 11) 440 Ω Input to output isolation (both outputs) 30 dB Output to output isolation 25 dB Table 1 - Reference Data *132 channel matrix at +15 dBmV per channel, 75 Ω source impedance 2 Zarlink Semiconductor Inc. SL2150D 2.0 Data Sheet Functional Description The SL2150D is a broadband wide dynamic range dual output tuner front end LNA with AGC. It also has application is any system where a wide dynamic range broadband power splitter is required. The pin assignment is contained in Figure 2 and the block diagram in Figure 1.The port internal peripheral circuits are contained in Figure 14. In normal application the RF input is interfaced to the device input. The input preamplifier is designed for low noise figure, within the operating region of 50 to 860 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides an impedance match to a 75 Ω source; the typical impedance is shown in Figure 4. The input NF is shown in Figure 6. The output of the preamplifier is then power split to two independently controlled AGC stages. Each AGC stage provides for a minimum of 30 dB of gain control across the input frequency range. The typical AGC characteristic and NF versus gain setting are contained in Figure 5 and Figure 7 respectively. Finally each of the AGC stages drive an output buffer of differential output impedance of 440 Ω, which provides a nominal 11 dB of gain when terminated into a differential 75 Ω load, as in Figure 11. Each channel AGC and output buffer can be independently powered down. In application it is important to avoid saturation of the output stage, therefore it is recommended that the output standing current be sunk to Vcc through an inductor. A resistive pull up can also be used as shown in Figure 13 "Example Application Driving 100 W Load with Resistive Pull Up", however the resistor values should not exceed 20 ohm single ended. If an inductive current sink is used the maximum available gain from the device is circa 26 dB. This gain can be reduced by application of an external load between the differential output ports. The gain can be approximately calculated from the following formula: - GAIN = 20*log ((Parallel combination of 440 ohm and external load between ports)/22 ohm)+2 dB For example when driving a 100 ohm load as in Figure 12, the gain equals - GAIN = 20 *log ((440 *100)/(440+100)/22)+2 dB =12 dB. 3 Zarlink Semiconductor Inc. SL2150D Data Sheet 3 1nF RF INPUT SL2150D RFIN 4 1nF F TYPE RF INPUTB 5.1nH MABAES0029 1:1 Figure 3 - Input Network CH1 S11 1 U FS Ω 4_: 133.23 16 Nov 2001 10:10:47 55.758 Ω 10.44 nH 850.000 000 MHz PRm Cor Avg 16 Smo Z0 75 Ω 4 3 1_: 169.02 -44.117 50 MHz Ω Ω 2_: 49.916 -57.436 250 MHz Ω Ω 3_: 31.238 -5.5576 500 MHz Ω Ω 1 2 START 50.000 000 MHz STOP 850.000 000 MHz Figure 4 - Typical Single-end Input Impedance 4 Zarlink Semiconductor Inc. SL2150D Data Sheet Typical AGC vs Control Voltage 15 5 -5 -25 -35 -45 -55 -65 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 AGC Voltage (V) Figure 5 - Typical AGC Characteristic Typical Noise Figure vs Frequency (Vagc = 3 V, Maximum Gain) 9 8.5 8 7.5 7 NF(dB) Gain (dB) -15 6.5 6 5.5 5 4.5 4 50 150 250 350 450 Frequency (MHz) 550 Figure 6 - Input Noise Figure at 25°C 5 Zarlink Semiconductor Inc. 650 750 850 SL2150D Data Sheet Typical Variation in Noise Figure vs. Gain Setting 20 18 Noise Figure (dB) 16 14 12 10 8 6 -10 -8 -6 -4 -2 0 2 4 6 8 Gain (dB) Figure 7 - Typical Variation in NF versus Gain Setting 6 Zarlink Semiconductor Inc. 10 12 SL2150D Data Sheet 132 channel matrix, 75 ohm source, all channels at +15 dBmV. Input and output conditions as in Fig. 3 and Fig. 12. -50 CSO,CTB (dBS) -60 CSO (dBC) CTB (dBC) -70 -80 -20 -15 -10 -5 0 Figure 8 - Typical Variation In CSO and CTB Versus Backoff from Maximum Gain 50 Ω C Driven output stage A Directional coupler D Port 1 B Network Analyzer C Monitored output stage Directional coupler D A B 50 Ω Directional coupler phase relationship A C 0 D 180 Port 2 B 0 0 Figure 9 - Test Condition for Output Crosstalk 7 Zarlink Semiconductor Inc. SL2150D Data Sheet Driven output stage 50 Ω C A Directional coupler D Port 1 B Network Analyzer Monitored input stage Port 2 Directional coupler phase relationship A C 0 D 180 B 0 0 Figure 10 - Test Condition for Output to Input Crosstalk Vcc 100nF SL2150D 100pF To 75Ω load MABAES0029 1:1 1nF FTYPE Figure 11 - Example Application Driving 75 Ω Load 8 Zarlink Semiconductor Inc. SL2150D Data Sheet Vcc 10 µH 10 µH 1 nF SL2150D 100 Ω 1 nF Figure 12 - Example Application Driving 100 Ω Load with Inductive Pull Up Vcc 2x 20 Ω 1 nF SL2150D 100 Ω Note: External resistor values must not exceed 20Ω 1 nF Figure 13 - Example Application Driving 100 Ω Load with Resistive Pull Up 9 Zarlink Semiconductor Inc. SL2150D Vcc Data Sheet INPUT DECOUPLED INPUT 440 Ω 1kΩ 440 Ω 2.5 V Output 270 Ω 3.9 V 2.5 V 1 k Ω 32 mA 32 mA Output Ports RF Input Port 30 k Ω 20 k Ω AGC INPUT 1.6 V 1.5 V 1.5 kΩ 1.7 kΩ AGC Port DIS Port Figure 14 - Port Peripheral Circuitry 10 Zarlink Semiconductor Inc. AGC INPUT SL2150D 3.0 Data Sheet Electrical Characteristics Test conditions (unless otherwise stated). T amb = -20o to 85oC, Vee = 0 V, Vcc = 5 V+-5% These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Electrical Characteristics Characteristic Pin Min. Supply current Input frequency range Input impedance Input return loss Typ. Max. Units 190 110 42 220 140 60 mA mA mA 860 MHz 50 3, 4 6.8 Input Noise Figure Both outputs enabled One output enabled Both outputs disabled 75 Ω See Figure 4 8 dB See Figure 4 7.2 dB Tamb = 27°C, see Figure 6 All loops at maximum gain -1 dB/dB 6.4 Variation in NF with gain adjust Gain Power gain from 75 Ω single ended source to differential 75 Ω load, with application as in Figure 11. Vagcip = 3.0 V Vagcip = 0.5 V Vagcip = Vee AGC monotonic from Vee to Vcc. Refer to Functional description section for information on calculating maximum gain with other load conditions dB dB dB CSO -66 -62 dBc dBc See note (2) See note (3) CTB -65 -62 dBc dBc See note (2) See note (3) CXM -60 dBc See note (2) dBm All gain settings, with load as in Figure 11 Input P1dB 11 See Figure 7 12.5 -25 maximum minimum minimum 9.5 Conditions -50 +4.5 11 Zarlink Semiconductor Inc. SL2150D Data Sheet Electrical Characteristics (continued) Characteristic Pin Min. Typ. Gain variation within channel Output impedance 11,12, 24,25 Output port DC standing current 11,12, 24,25 AGC1, 2 input leakage current 8,9 DIS1, 2 input Input high voltage Input low voltage Leakage current 6, 7 Max. Units 0.25 dB Channel bandwidth 8 MHz within operating frequency range, all loops, all gain settings Ω Differential 440 Conditions 50 mA Standing current that any external load has to sustain. -200 200 µA Vagcip = Vee to Vcc 2.8 Vee -200 Vcc 0.8 200 V V µA Output disabled Output enabled DIS1, 2 = Vee to Vcc Crosstalk between outputs -25 dB All gain settings, measured differential output to differential output, driven ports in phase and monitored ports out of phase, see Figure 9 Crosstalk between outputs and RF input -30 dB All gain settings, measured differential output to single ended input, driven ports in phase, see Figure 10 Note 1: Note 2: Note 3: All power levels are referred to 75 Ω, and 0 dBm = 109 dB µV. Load as in Figure 11and Figure 12, at maximum gain, 132 channel matrix, 75 ohm source with all channels at +15 dBmV, assuming power match. Load as in Figure 11 and Figure 12, all gain settings, 132 channel matrix, 75 ohm source with all channels at +15 dBmV, assuming power match. 12 Zarlink Semiconductor Inc. SL2150D Data Sheet Absolute Maximum Ratings All voltages are referred to Vee at 0V Characteristic Supply voltage Min. Max. Units -0.3 6 V 8 dBm RF input voltage All I/O port DC offsets -0.3 Vcc+0.3 V Storage temperature -55 150 oC Junction temperature 125 o Package thermal resistance, chip to ambient 35 oC/W 1155 mW Power consumption at 5.25 V ESD protection 1.5 C kV 13 Zarlink Semiconductor Inc. Conditions Differential Power applied Paddle to be soldered to ground plane Mil-std 883B method 3015 cat1 SL2150D Application Diagram Note: Baluns are only required to interface to 75/50 ohm test equipment. 4.0 Data Sheet Figure 15 - SL2150D Evaluation PCB Schematic 14 Zarlink Semiconductor Inc. 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