SM320F2812, SMJ320F2812 Digital Signal Processors Data Manual Literature Number: SGUS053B December 2004 − Revised September 2006 ! ! IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated Features 1 Features D High-Performance Static CMOS Technology D D D D D D D D D − 150 MHz (6.67-ns Cycle Time) − Low-Power (1.8-V Core at 135 MHz, 1.9-V Core at 150 MHz, 3.3-V I/O) Design − 3.3-V Flash Voltage JTAG Boundary Scan Support† High-Performance 32-Bit CPU (TMS320C28x) − 16 x 16 and 32 x 32 MAC Operations − 16 x 16 Dual MAC − Harvard Bus Architecture − Atomic Operations − Fast Interrupt Response and Processing − Unified Memory Programming Model − 4M Linear Program Address Reach − 4M Linear Data Address Reach − Code-Efficient (in C/C++ and Assembly) − TMS320F24x/LF240x Processor Source Code Compatible On-Chip Memory − Flash Devices: Up to 128K x 16 Flash (Four 8K x 16 and Six 16K x 16 Sectors) − ROM Devices: Up to 128K x 16 ROM − 1K x 16 OTP ROM − L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM) − H0: 1 Block of 8K x 16 SARAM − M0 and M1: 2 Blocks of 1K x 16 Each SARAM Boot ROM (4K x 16) − With Software Boot Modes − Standard Math Tables External Interface − Up to 1M Total Memory − Programmable Wait States − Programmable Read/Write Strobe Timing − Three Individual Chip Selects Clock and System Control − Dynamic PLL Ratio Changes Supported − On-Chip Oscillator − Watchdog Timer Module Three External Interrupts Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts 128-Bit Security Key/Lock − Protects Flash/ROM/OTP and L0/L1 SARAM − Prevents Firmware Reverse Engineering D Three 32-Bit CPU-Timers D Motor Control Peripherals D D D D D D D D − Two Event Managers (EVA, EVB) − Compatible to 240xA Devices Serial Port Peripherals − Serial Peripheral Interface (SPI) − Two Serial Communications Interfaces (SCIs), Standard UART − Enhanced Controller Area Network (eCAN) − Multichannel Buffered Serial Port (McBSP) With SPI Mode 12-Bit ADC, 16 Channels − 2 x 8 Channel Input Multiplexer − Two Sample-and-Hold − Single/Simultaneous Conversions − Fast Conversion Rate: 80 ns/12.5 MSPS Up to 56 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins Advanced Emulation Features − Analysis and Breakpoint Functions − Real-Time Debug via Hardware Development Tools Include − ANSI C/C++ Compiler/Assembler/Linker − Supports TMS320C24x/240x Instructions − Code Composer Studio IDE − DSP/BIOS − JTAG Scan Controllers† [Texas Instruments (TI) or Third-Party] − Evaluation Modules − Broad Third-Party Digital Motor Control Support Low-Power Modes and Power Savings − IDLE, STANDBY, HALT Modes Supported − Disable Individual Peripheral Clocks Package Options − 172-Pin Ceramic Quad Flatpack (HFG) Temperature Options: − M: −55°C to 125°C (HFG) TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. † IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port December 2004 − Revised September 2006 SGUS053B 3 Introduction 2 Introduction This section provides a summary of the device features, lists the pin assignments, and describes the function of each pin. This document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging. 2.1 Description The SM320F2812 and SMJ320F2812 devices, members of the C28x DSP generation, are a highly integrated, high-performance solution for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview. Throughout this document SM320F2812 and SMJ320F2812 are abbreviated as F2812. TMS320C28x is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 4 SGUS053B December 2004 − Revised September 2006 Introduction 2.2 Device Summary Table 2−1 provides a summary of the device features. Table 2−1. Hardware Features† FEATURE F2812 Instruction Cycle (at 150 MHz) 6.67 ns Single-Access RAM (SARAM) (16-bit word) 18K 3.3-V On-Chip Flash (16-bit word) 128K On-Chip ROM (16-bit word) — Code Security for On-Chip Flash/SARAM/OTP/ROM Yes Boot ROM Yes OTP ROM (1K X 16) Yes External Memory Interface Yes Event Managers A and B (EVA and EVB) EVA, EVB S General-Purpose (GP) Timers S Compare (CMP)/PWM 16 S Capture (CAP)/QEP Channels 6/2 4 Watchdog Timer Yes 12-Bit ADC Yes S Channels 32-Bit CPU Timers SPI SCIA, SCIB 16 3 Yes SCIA, SCIB CAN Yes McBSP Yes Digital I/O Pins (Shared) 56 External Interrupts Supply Voltage Packaging 3 1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O 179-ball GHH 176-pin PGF 172-pin HFG Yes‡ Temperature Options M: −55°C to 125°C † The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Silicon Errata (SPRZ193) has been posted on the Texas Instruments (TI) website. The errata is updated as needed. ‡ HFG package only December 2004 − Revised September 2006 SGUS053B 5 Introduction 2.3 Pin Assignments XA[11] TDI XA[10] V SS V DD TDO TMS XA[9] C3TRIP C2TRIP C1TRIP XA[8] XCLKOUT XA[7] TCLKINA TDIRA T2CTRIP / EVASOC V DDIO V SS V DD XA[6] T1CTRIP_PDPINTA CAP3_QEPI1 XA[5] CAP2_QEP2 CAP1_QEP1 V SS T2PWM_T2CMP XA[4] T1PWM_T1CMP PWM6 V DD V SS PWM5 XD[13] XD[12] PWM4 PWM3 PWM2 PWM1 SCIRXDB SCITXDB CANRXA The SM/SMJ320F2812 172-pin HFG ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2−1. See Table 2−2 for a description of each pin’s function(s). 87 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 129 130 XZCS6AND7 TESTSEL TRST TCK EMU0 XA[12] XD[14] XF_XPLLDIS XA[13] VSS VDD XA[14] VDDIO EMU1 XD[15] XA[15] XINT1_XBIO XNMI_XINT13 XINT2_ADCSOC XA[16] VDD SCITXDA XA[17] SCIRXDA XA[18] XHOLD XRS XREADY VDD1 VSS1 ADCBGREFIN VSSA2 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLO VSSAIO 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 86 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 172 XZCS2 CANTXA VSS XA[3] XWE T4CTRIP/EVBSOC XHOLDA VDDIO XA[2] T3CTRIP_PDPINTB VSS X1/XCLKIN X2 VDD XD[11] XD[10] TCLKINB TDIRB VDD3VFL XD[9] TEST1 TEST2 XD[8] VDDIO C6TRIP C5TRIP C4TRIP CAP6_QEPI2 CAP5_QEP4 VSS CAP4_QEP3 VDD T4PWM_T4CMP XD[7] T3PWM_T3CMP VSS XR/W PWM12 PWM11 PWM10 PWM9 PWM8 PWM7 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 V DDAIO ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP AVSSREFBG AVDDREFBG V DDA1 V SSA1 ADCRESEXT XMP/ MC XA[0] MDRA XD[0] MDXA V DD XD[1] MCLKRA MFSXA XD[2] MCLKXA MFSRA XD[3] V DDIO V SS XD[4] SPICLKA SPISTEA XD[5] V DD V SS XD[6] SPISIMOA SPISOMIA XRD XA[1] XZCS0AND1 1 Figure 2−1. SM320F2812 172-Pin HFG CQFP (Top View) 6 SGUS053B December 2004 − Revised September 2006 Introduction 2.4 Signal Descriptions Table 2−2 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used. Table 2−2. Signal Descriptions† PIN NO. NAME 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION XINTF SIGNALS XA[18] 154 O/Z − XA[17] 152 O/Z − XA[16] 149 O/Z − XA[15] 145 O/Z − XA[14] 141 O/Z − XA[13] 138 O/Z − XA[12] 135 O/Z − XA[11] 129 O/Z XA[10] 127 O/Z − XA[9] 122 O/Z − XA[8] 118 O/Z − XA[7] 116 O/Z − XA[6] 109 O/Z − XA[5] 106 O/Z − XA[4] 101 O/Z − XA[3] 83 O/Z − XA[2] 78 O/Z − XA[1] 42 O/Z − XA[0] 18 O/Z XD[15] 144 I/O/Z PU XD[14] 136 I/O/Z PU XD[13] 95 I/O/Z PU XD[12] 94 I/O/Z PU XD[11] 72 I/O/Z PU XD[10] 71 I/O/Z PU XD[9] 67 I/O/Z PU XD[8] 64 I/O/Z PU XD[7] 53 I/O/Z PU XD[6] 38 I/O/Z PU XD[5] 35 I/O/Z PU XD[4] 32 I/O/Z PU XD[3] 29 I/O/Z PU XD[2] 26 I/O/Z PU XD[1] 23 I/O/Z PU 19-bit XINTF Address Bus 16-bit XINTF Data Bus XD[0] 20 I/O/Z PU † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown December 2004 − Revised September 2006 SGUS053B 7 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. NAME 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION XINTF SIGNALS (CONTINUED) XMP/MC XHOLD 17 155 I I PD Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface. When low, Zone 7 is disabled from the external interface and on-chip boot ROM may be accessed instead. This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software. The state of the XMP/MC pin is ignored after reset. PU External Hold Request. XHOLD, when active (low), requests the XINTF to release the external bus and place all buses and strobes into a high-impedance state. The XINTF releases the bus when any current access is complete and there are no pending accesses on the XINTF. XHOLDA 80 O/Z − External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has granted a XHOLD request. All XINTF buses and strobe signals are in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). XZCS0AND1 43 O/Z − XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an access to the XINTF Zone 0 or Zone 1 is performed. XZCS2 86 O/Z − XINTF Zone 2 Chip Select. XZCS2 is active (low) when an access to the XINTF Zone 2 is performed. XZCS6AND7 130 O/Z − XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an access to the XINTF Zone 6 or Zone 7 is performed. XWE 82 O/Z − Write Enable. Active-low write strobe. The write strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. XRD 41 O/Z − Read Enable. Active-low read strobe. The read strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. NOTE: The XRD and XWE signals are mutually exclusive. XR/W 50 O/Z − Read Not Write Strobe. Normally held high. When low, XR/W indicates write cycle is active; when high, XR/W indicates read cycle is active. XREADY 157 I PU Ready Signal. Indicates peripheral is ready to complete the access when asserted to 1. XREADY can be configured to be a synchronous or an asynchronous input. See the timing diagrams for more details. JTAG AND MISCELLANEOUS SIGNALS X1/XCLKIN 75 I Oscillator Input − input to the internal oscillator. This pin is also used to feed an external clock. The 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used. X2 74 O Oscillator Output O Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1. XCLKOUT 117 − † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown 8 SGUS053B December 2004 − Revised September 2006 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. NAME TESTSEL 172-PIN HFG 131 I/O/Z‡ PU/PD§ I PD DESCRIPTION Test Pin. Reserved for TI. Must be connected to ground. Device Reset (in) and Watchdog Reset (out). XRS 156 I/O PU Device reset. XRS causes the device to terminate execution. The PC points to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 XCLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is recommended that this pin be driven by an open-drain device. TEST1 66 I/O − Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected. TEST2 65 I/O − Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected. JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application specific, it is recommended that each target board is validated for proper operation of the debugger and the application. TRST 132 I PD TCK 133 I PU JTAG test clock with internal pullup TMS 123 I PU JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. TDI 128 I PU JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 124 O/Z − JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. EMU0 133 I/O/Z PU Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. EMU1 143 I/O/Z PU Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown December 2004 − Revised September 2006 SGUS053B 9 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. NAME 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION ADC ANALOG INPUT SIGNALS ADCINA7 163 I ADCINA6 164 I ADCINA5 165 I ADCINA4 166 I ADCINA3 167 I ADCINA2 168 I ADCINA1 169 I ADCINA0 170 I ADCINB7 9 I ADCINB6 8 I ADCINB5 7 I ADCINB4 6 I ADCINB3 5 I ADCINB2 4 I ADCINB1 3 I ADCINB0 2 I ADCREFP 11 Eight-channel analog inputs for Sample-and-Hold A. The ADC pins should not be driven before VDDA1, VDDA2, and VDDAIO pins have been fully powered up. Eight-channel analog inputs for Sample-and-Hold B. The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up. O ADC Voltage Reference Output (2 V). Requires a low ESR (50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. (Can accept external reference input (2 V) if the software bit is enabled for this mode. 1-µF to 10-µF low ESR capacitor can be used in the external reference mode.) ADCREFM 10 O ADC Voltage Reference Output (1 V). Requires a low ESR (50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. (Can accept external reference input (1 V) if the software bit is enabled for this mode. 1-µF to 10-µF low ESR capacitor can be used in the external reference mode.) ADCRESEXT 16 O ADC External Current Bias Resistor (24.9 kΩ ±5%) ADCBGREFIN 160 I Test Pin. Reserved for TI. Must be left unconnected. AVSSREFBG 12 I ADC Analog GND AVDDREFBG 13 I ADC Analog Power (3.3 V) ADCLO 171 I Common Low Side Analog Input. Connect to analog ground. VSSA1 15 I ADC Analog GND VSSA2 161 I ADC Analog GND VDDA1 14 I ADC Analog 3.3-V Supply VDDA2 162 I ADC Analog 3.3-V Supply VSS1 159 I ADC Digital GND VDD1 158 I ADC Digital 1.8-V (or 1.9-V) Supply VDDAIO 1 3.3-V Analog I/O Power Pin VSSAIO 172 Analog I/O Ground Pin † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown 10 SGUS053B December 2004 − Revised September 2006 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. NAME 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION POWER SIGNALS VDD VDD 22 VDD VDD 55 VDD VDD VDD VDD VDD VDD VSS VSS 36 73 − 98 1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2, Recommended Operating Conditions, for voltage requirements. 110 125 140 150 − 31 VSS VSS 37 VSS VSS 57 VSS VSS 76 VSS VSS 97 51 − 84 Core and Digital I/O Ground Pins 103 VSS VSS 111 VSS VSS 126 VSS VSS − VDDIO VDDIO 30 VDDIO VDDIO 79 − 139 − 63 − VDDIO VDDIO 142 VDD3VFL 68 3.3-V I/O Digital Power Pins 112 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met. This pin is used as VDDIO in ROM parts and must be connected to 3.3 V in ROM parts as well. † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown December 2004 − Revised September 2006 SGUS053B 11 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. GPIO PERIPHERAL SIGNAL 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION GPIO OR PERIPHERAL SIGNALS GPIOA OR EVA SIGNALS GPIOA0 PWM1 (O) 90 I/O/Z PU GPIO or PWM Output Pin #1 GPIOA1 PWM2 (O) 91 I/O/Z PU GPIO or PWM Output Pin #2 GPIOA2 PWM3 (O) 92 I/O/Z PU GPIO or PWM Output Pin #3 GPIOA3 PWM4 (O) 93 I/O/Z PU GPIO or PWM Output Pin #4 GPIOA4 PWM5 (O) 96 I/O/Z PU GPIO or PWM Output Pin #5 GPIOA5 PWM6 (O) 99 I/O/Z PU GPIO or PWM Output Pin #6 GPIOA6 T1PWM_T1CMP (I) 100 I/O/Z PU GPIO or Timer 1 Output GPIOA7 T2PWM_T2CMP (I) 102 I/O/Z PU GPIO or Timer 2 Output GPIOA8 CAP1_QEP1 (I) 104 I/O/Z PU GPIO or Capture Input #1 GPIOA9 CAP2_QEP2 (I) 105 I/O/Z PU GPIO or Capture Input #2 GPIOA10 CAP3_QEPI1 (I) 107 I/O/Z PU GPIO or Capture Input #3 GPIOA11 TDIRA (I) 114 I/O/Z PU GPIO or Timer Direction GPIOA12 TCLKINA (I) 115 I/O/Z PU GPIO or Timer Clock Input GPIOA13 C1TRIP (I) 119 I/O/Z PU GPIO or Compare 1 Output Trip GPIOA14 C2TRIP (I) 120 I/O/Z PU GPIO or Compare 2 Output Trip GPIOA15 C3TRIP (I) 121 I/O/Z PU GPIO or Compare 3 Output Trip GPIOB OR EVB SIGNALS GPIOB0 PWM7 (O) 44 I/O/Z PU GPIO or PWM Output Pin #7 GPIOB1 PWM8 (O) 45 I/O/Z PU GPIO or PWM Output Pin #8 GPIOB2 PWM9 (O) 46 I/O/Z PU GPIO or PWM Output Pin #9 GPIOB3 PWM10 (O) 47 I/O/Z PU GPIO or PWM Output Pin #10 GPIOB4 PWM11 (O) 48 I/O/Z PU GPIO or PWM Output Pin #11 GPIOB5 PWM12 (O) 49 I/O/Z PU GPIO or PWM Output Pin #12 GPIOB6 T3PWM_T3CMP (I) 52 I/O/Z PU GPIO or Timer 3 Output GPIOB7 T4PWM_T4CMP (I) 54 I/O/Z PU GPIO or Timer 4 Output GPIOB8 CAP4_QEP3 (I) 56 I/O/Z PU GPIO or Capture Input #4 GPIOB9 CAP5_QEP4 (I) 58 I/O/Z PU GPIO or Capture Input #5 GPIOB10 CAP6_QEPI2 (I) 59 I/O/Z PU GPIO or Capture Input #6 GPIOB11 TDIRB (I) 69 I/O/Z PU GPIO or Timer Direction GPIOB12 TCLKINB (I) 70 I/O/Z PU GPIO or Timer Clock Input GPIOB13 C4TRIP (I) 60 I/O/Z PU GPIO or Compare 4 Output Trip GPIOB14 C5TRIP (I) 61 I/O/Z PU GPIO or Compare 5 Output Trip GPIOB15 C6TRIP (I) 62 I/O/Z PU GPIO or Compare 6 Output Trip † Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown 12 SGUS053B December 2004 − Revised September 2006 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. GPIO PERIPHERAL SIGNAL 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION GPIOD OR EVA SIGNALS GPIOD0 T1CTRIP_PDPINTA (I) 108 I/O/Z PU Timer 1 Compare Output Trip GPIOD1 T2CTRIP/EVASOC (I) 113 I/O/Z PU Timer 2 Compare Output Trip or External ADC Start-of-Conversion EV-A GPIOD5 T3CTRIP_PDPINTB (I) 77 I/O/Z PU Timer 3 Compare Output Trip GPIOD6 T4CTRIP/EVBSOC (I) 81 I/O/Z PU Timer 4 Compare Output Trip or External ADC Start-of-Conversion EV-B GPIOE0 XINT1_XBIO (I) 146 I/O/Z GPIOE1 XINT2_ADCSOC (I) 148 GPIOE2 XNMI_XINT13 (I) 147 GPIOD OR EVB SIGNALS GPIOE OR INTERRUPT SIGNALS − GPIO or XINT1 or XBIO input I/O/Z − GPIO or XINT2 or ADC start of conversion I/O/Z PU GPIO or XNMI or XINT13 GPIOF OR SPI SIGNALS GPIOF0 SPISIMOA (O) 39 I/O/Z − GPIO or SPI slave in, master out GPIOF1 SPISOMIA (I) 40 I/O/Z − GPIO or SPI slave out, master in GPIOF2 SPICLKA (I/O) 33 I/O/Z − GPIO or SPI clock GPIOF3 SPISTEA (I/O) 34 I/O/Z − GPIO or SPI slave transmit enable GPIOF OR SCI-A SIGNALS GPIOF4 SCITXDA (O) 151 I/O/Z PU GPIO or SCI asynchronous serial port TX data GPIOF5 SCIRXDA (I) 153 I/O/Z PU GPIO or SCI asynchronous serial port RX data GPIOF OR CAN SIGNALS GPIOF6 CANTXA (O) 85 I/O/Z PU GPIO or eCAN transmit data GPIOF7 CANRXA (I) 87 I/O/Z PU GPIO or eCAN receive data GPIOF8 MCLKXA (I/O) 27 I/O/Z PU GPIO or transmit clock GPIOF9 MCLKRA (I/O) 24 I/O/Z PU GPIO or receive clock GPIOF10 MFSXA (I/O) 25 I/O/Z PU GPIO or transmit frame synch GPIOF11 MFSRA (I/O) 28 I/O/Z PU GPIO or receive frame synch GPIOF12 MDXA (O) 21 I/O/Z − GPIOF OR McBSP SIGNALS GPIO or transmitted serial data GPIOF13 MDRA (I) 19 I/O/Z PU GPIO or received serial data † Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown December 2004 − Revised September 2006 SGUS053B 13 Introduction Table 2−2. Signal Descriptions† (Continued) PIN NO. GPIO PERIPHERAL SIGNAL 172-PIN HFG I/O/Z‡ PU/PD§ DESCRIPTION GPIOF OR XF CPU OUTPUT SIGNAL GPIOF14 XF_XPLLDIS (O) 137 I/O/Z GPIOG4 SCITXDB (O) 88 I/O/Z PU This pin has three functions: 1. XF − General-purpose output pin. 2. XPLLDIS − This pin is sampled during reset to check if the PLL needs to be disabled. The PLL will be disabled if this pin is sensed low. HALT and STANDBY modes cannot be used when the PLL is disabled. 3. GPIO − GPIO function GPIOG OR SCI-B SIGNALS − GPIO or SCI asynchronous serial port transmit data GPIOG5 SCIRXDB (I) 89 I/O/Z − GPIO or SCI asynchronous serial port receive data † Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown NOTE: Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions. 14 SGUS053B December 2004 − Revised September 2006 Functional Overview 3 Functional Overview Memory Bus TINT0 CPU-Timer 0 CPU-Timer 1 Real-Time JTAG CPU-Timer 2 TINT2 INT14 PIE (96 interrupts)† TINT1 XINT13 External Interrupt Control (XINT1/2/13, XNMI) XNMI INT[12:1] INT13 NMI G P I GPIO Pins O SCIA/SCIB FIFO SPI FIFO McBSP FIFO C28x CPU eCAN XRS 12-Bit ADC X1/XCLKIN X2 XF_XPLLDIS ÍÍÍ ÍÍÍ System Control (Oscillator and PLL + Peripheral Clocking + Low-Power Modes + WatchDog) Data(16) M0 SARAM 1K x 16 M1 SARAM 1K x 16 ÍÍÍÍÍÍ ÍÍÍÍÍÍ ÍÍÍÍÍÍ ÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ L1 SARAM 4K x 16 Flash 128K x 16 EVA/EVB 16 Channels Address(19) L0 SARAM 4K x 16 M U X Control External Interface (XINTF) RS CLKIN OTP 1K x 16 H0 SARAM 8K × 16 Memory Bus Boot ROM 4K × 16 Peripheral Bus Protected by the code-security module. † 45 of the possible 96 interrupts are used on the device. Figure 3−1. Functional Block Diagram December 2004 − Revised September 2006 SGUS053B 15 Functional Overview 3.1 Memory Map Block Start Address On-Chip Memory External Memory XINTF ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ Data Space 0x00 0000 M0 Vector − RAM (32 × 32) (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K × 16) 0x00 0400 0x00 0800 Low 64K (24x/240x Equivalent Data Space) Prog Space 0x00 0D00 0x00 0E00 Data Space Prog Space M1 SARAM (1K × 16) Peripheral Frame 0 (2K × 16) PIE Vector - RAM (256 × 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Reserved Reserved 0x00 2000 Reserved 0x00 6000 Peripheral Frame 1 (4K × 16, Protected) 0x00 7000 Peripheral Frame 2 (4K × 16, Protected) XINTF Zone 0 (8K × 16, XZCS0AND1) 0x00 2000 XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected) 0x00 4000 Reserved 0x00 8000 L0 SARAM (4K × 16, Secure Block) 0x00 9000 L1 SARAM (4K × 16, Secure Block) Reserved 0x00 A000 Reserved XINTF Zone 2 (0.5M × 16, XZCS2) 0x08 0000 XINTF Zone 6 (0.5M × 16, XZCS6AND7) 0x10 0000 0x18 0000 0x3D 7800 0x3D 7C00 High 64K (24x/240x Equivalent Program Space) 0x3D 8000 0x3F 7FF8 0x3F 8000 OTP (or ROM) (1K × 16, Secure Block) Reserved (1K) Reserved Flash (or ROM) (128K × 16, Secure Block) 128-Bit Password H0 SARAM (8K × 16) 0x3F A000 Reserved 0x3F F000 0x3F FFC0 LEGEND: Boot ROM (4K × 16) (Enabled if MP/MC = 0) BROM Vector - ROM (32 × 32) (Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0) 0x3F C000 XINTF Zone 7 (16K × 16, XZCS6AND7) (Enabled if MP/MC = 1) XINTF Vector - RAM (32 × 32) (Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0) Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time. NOTES: A. B. C. D. Memory blocks are not to scale. Reserved locations are reserved for future expansion. Application should not access these areas. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program cannot access these memory maps in program space. E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. F. Certain memory ranges are EALLOW protected against spurious writes after configuration. G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations. Figure 3−2. F2812 Memory Map (See Notes A through E) 16 SGUS053B December 2004 − Revised September 2006 Functional Overview Table 3−1. Addresses of Flash Sectors in F2812 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 0x3D 9FFF Sector J, 8K x 16 0x3D A000 0x3D BFFF Sector I, 8K x 16 0x3D C000 0x3D FFFF Sector H, 16K x 16 0x3E 0000 0x3E 3FFF Sector G, 16K x 16 0x3E 4000 0x3E 7FFF Sector F, 16K x 16 0x3E 8000 0x3E BFFF Sector E, 16K x 16 0x3E C000 0x3E FFFF Sector D, 16K x 16 0x3F 0000 0x3F 3FFF Sector C, 16K x 16 0x3F 4000 0x3F 5FFF Sector B, 8K x 16 0x3F 6000 Sector A, 8K x 16 0x3F 7F80 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 0x3F 7FF7 Boot-to-Flash (or ROM) Entry Point (program branch instruction here) 0x3F 7FF8 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) December 2004 − Revised September 2006 SGUS053B 17 Functional Overview The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code only executes from the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7 (if MP/MC mode is high). The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. This makes interfacing to external peripherals easy and glueless. NOTE: The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select (XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for details. Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, appears in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones. On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/MC. I/O space is not supported on the 2812 XINTF. The wait states for the various spaces in the memory map area are listed in Table 3−2. 18 SGUS053B December 2004 − Revised September 2006 Functional Overview Table 3−2. Wait States 3.2 3.2.1 AREA WAIT-STATES M0 and M1 SARAMs 0-wait Fixed COMMENTS Peripheral Frame 0 0-wait Fixed Peripheral Frame 1 0-wait (writes) 2-wait (reads) Fixed Peripheral Frame 2 0-wait (writes) 2-wait (reads) Fixed L0 & L1 SARAMs 0-wait OTP (or ROM) Programmable, 1-wait minimum Programmed via the Flash registers. 1-wait-state operation is possible at a reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information. Flash (or ROM) Programmable, 0-wait minimum Programmed via the Flash registers. 0-wait-state operation is possible at reduced CPU frequency. The CSM password locations are hardwired for 16 wait-states. See Section 3.2.6, Flash (F281x Only), for more information. H0 SARAM 0-wait Fixed Boot-ROM 1-wait Fixed XINTF Programmable, 1-wait minimum Programmed via the XINTF registers. Cycles can be extended by external memory or peripheral. 0-wait operation is not possible. Brief Descriptions C28x CPU The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. C28x and TMS320C2000 are trademarks of Texas Instruments. December 2004 − Revised September 2006 SGUS053B 19 Functional Overview 3.2.2 Memory Bus (Harvard Bus Architecture) As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritizes memory accesses. Generally, the priority of Memory Bus accesses can be summarized as follows: Highest: Data Writes† Program Writes† Data Reads Program Reads‡ Lowest: 3.2.3 Fetches‡ Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2812 adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral frame 1). 3.2.4 Real-Time JTAG and Analysis The F281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F2812 supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F2812 implements the real-time mode in hardware within the CPU. This is a unique feature to the F2812, no software monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs. 3.2.5 External Interface (XINTF) This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select, and programmable strobe timing enables glueless interface to external memories and peripherals. † Simultaneous Data and Program writes cannot occur on the Memory Bus. ‡ Simultaneous Program Reads and Fetches cannot occur on the Memory Bus. 20 SGUS053B December 2004 − Revised September 2006 Functional Overview 3.2.6 Flash The F2812 contains 128K x 16 of embedded flash memory, segregated into four 8K X 16 sectors, and six 16K X 16 sectors. The F2810 has 64K X 16 of embedded flash, segregated into two 8K X 16 sectors, and three 16K X 16 sectors. The device also contains a single 1K x 16 of OTP memory at address range 0x3D 7800 − 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. NOTE: The F2812 Flash and OTP wait states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution is much faster than the raw performance indicated by the wait state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. The pipeline mode is not available for the OTP block. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078). 3.2.7 L0, L1, H0 SARAMs The F281x contains an additional 16K x 16 of single-access RAM, divided into three blocks (4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both program and data space. 3.2.8 Boot ROM The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can select to execute code already present in the internal Flash or download new software to internal RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3−3 shows the details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide (SPRS095), for more information. Table 3−3. Boot Mode Selection GPIOF4 (SCITXDA) GPIOF12 (MDXA) GPIOF3 (SPISTEA) GPIOF2 (SPICLK) PU No PU No PU No PU 1 x x x Call SPI_Boot to load from an external serial SPI EEPROM 0 1 x x Call SCI_Boot to load from SCI-A 0 0 1 1 Jump to H0 SARAM address 0x3F 8000 0 0 1 0 Jump to OTP address 0x3D 7800 0 0 0 1 Call Parallel_Boot to load from GPIO Port B 0 0 0 0 BOOT MODE SELECTED GPIO PU status† Jump to Flash/ROM address 0x3F 7FF6 A branch instruction must have been programmed here prior to reset to redirect code execution as desired. † PU = pin has an internal pullup. No PU = pin does not have an internal pullup ‡ Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic. § If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader. December 2004 − Revised September 2006 SGUS053B 21 Functional Overview 3.2.9 Security The F281x supports high levels of security to protect the user firmware from being reversed engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/ROM/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which matches the value stored in the password locations within the Flash/ROM. NOTE: For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data, but must be programmed to 0x0000 when the Code Security Passwords are programmed. If security is not a concern, then these addresses may be used for code or data. The 128-bit password (at 0x3F 7FF8 − 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device. Code Security Module Disclaimer The Code Security Module (CSM) included on this device was designed to password protect the data stored in the associated memory (either ROM or Flash) and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI’s published specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 3.2.10 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F281x, 45 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block. 22 SGUS053B December 2004 − Revised September 2006 Functional Overview 3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) The F281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. 3.2.12 Oscillator and PLL The F281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode. 3.2.13 Watchdog The F281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog generates a reset to the processor. The watchdog can be disabled if necessary. 3.2.14 Peripheral Clocking The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds. 3.2.15 Low-Power Modes The F281x device is a full-static CMOS device. Three low-power modes are provided: IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral wakes the processor from IDLE mode. STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event wakes the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event. HALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowest possible power consumption mode. Only a reset or XNMI wakes the device from this mode. December 2004 − Revised September 2006 SGUS053B 23 Functional Overview 3.2.16 Peripheral Frames 0, 1, 2 (PFn) The F281x segregates peripherals into three sections. The mapping of peripherals is as follows: PF0: XINTF: External Interface Configuration Registers (2812 only) PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Control, Programming, Erase, Verify Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers PF1: eCAN: eCAN Mailbox and Control Registers PF2: SYS: System Control Registers GPIO: GPIO Mux Configuration and Control Registers EV: Event Manager (EVA/EVB) Control Registers McBSP: McBSP Control and TX/RX Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Peripheral Interface (SPI) Control and RX/TX Registers ADC: 12-Bit ADC Registers 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. 3.2.18 32-Bit CPU Timers (0, 1, 2) CPU Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. CPU Timer 1 is also reserved for TI system functions. CPU Timer 2 is connected to INT14 of the CPU. CPU Timer 1 can be connected to INT13 of the CPU. CPU Timer 0 is for general use and is connected to the PIE block. 24 SGUS053B December 2004 − Revised September 2006 Functional Overview 3.2.19 Control Peripherals The F2812 supports the following peripherals which are used for embedded control and communication: EV: The event manager module includes general-purpose timers, full-compare/PWM units, capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. The event managers on the F2812 is compatible to the event managers on the 240x devices (with some minor enhancements). ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and-hold units for simultaneous sampling. 3.2.20 Serial Port Peripherals The F2812 supports the following serial communication peripherals: 3.3 eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. McBSP: This is the multichannel buffered serial port that is used to connect to E1/T1 lines, phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This significantly reduces the overhead for servicing this peripheral. SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the F2812, the port supports a 16-level receive and transmit FIFO for reducing servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. On the F2812, the port supports a 16-level receive and transmit FIFO for reducing servicing overhead. Register Map The F2812 device contains three peripheral register spaces. The spaces are categorized as follows: • Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3−4. • Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3−5. • Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3−6. December 2004 − Revised September 2006 SGUS053B 25 Functional Overview Table 3−4. Peripheral Frame 0 Registers† NAME ACCESS TYPE‡ ADDRESS RANGE SIZE (x16) Device Emulation Registers 0x00 0880 0x00 09FF 384 reserved 0x00 0A00 0x00 0A7F 128 FLASH Registers§ 0x00 0A80 0x00 0ADF 96 Code Security Module Registers 0x00 0AE0 0x00 0AEF 16 reserved 0x00 0AF0 0x00 0B1F 48 XINTF Registers 0x00 0B20 0x00 0B3F 32 reserved 0x00 0B40 0x00 0BFF 192 CPU-TIMER0/1/2 Registers 0x00 0C00 0x00 0C3F 64 reserved 0x00 0C40 0x00 0CDF 160 PIE Registers 0x00 0CE0 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 0x00 0DFF 256 EALLOW protected Reserved 0x00 0E00 0x00 0FFF 512 EALLOW protected EALLOW protected CSM Protected EALLOW protected Not EALLOW protected Not EALLOW protected † Registers in Frame 0 support 16-bit and 32-bit accesses. ‡ If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction disables writes. This prevents stray code or pointers from corrupting register contents. § The Flash Registers are also protected by the Code Security Module (CSM). Table 3−5. Peripheral Frame 1 Registers¶ NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE eCAN Registers 0x00 6000 0x00 60FF 256 (128 x 32) Some eCAN control registers (and selected bits in other eCAN control registers) are EALLOW-protected. eCAN Mailbox RAM 0x00 6100 0x00 61FF 256 (128 x 32) Not EALLOW-protected reserved 0x00 6200 0x00 6FFF 3584 ¶ The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries. 26 SGUS053B December 2004 − Revised September 2006 Functional Overview Table 3−6. Peripheral Frame 2 Registers† NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE reserved 0x00 7000 0x00 700F 16 System Control Registers 0x00 7010 0x00 702F 32 reserved 0x00 7030 0x00 703F 16 SPI-A Registers 0x00 7040 0x00 704F 16 Not EALLOW Protected SCI-A Registers 0x00 7050 0x00 705F 16 Not EALLOW Protected reserved 0x00 7060 0x00 706F 16 External Interrupt Registers 0x00 7070 0x00 707F 16 reserved 0x00 7080 0x00 70BF 64 GPIO Mux Registers 0x00 70C0 0x00 70DF 32 EALLOW Protected GPIO Data Registers 0x00 70E0 0x00 70FF 32 Not EALLOW Protected ADC Registers 0x00 7100 0x00 711F 32 Not EALLOW Protected reserved 0x00 7120 0x00 73FF 736 EV-A Registers 0x00 7400 0x00 743F 64 reserved 0x00 7440 0x00 74FF 192 EV-B Registers 0x00 7500 0x00 753F 64 reserved 0x00 7540 0x00 774F 528 SCI-B Registers 0x00 7750 0x00 775F 16 reserved 0x00 7760 0x00 77FF 160 McBSP Registers 0x00 7800 0x00 783F 64 reserved 0x00 7840 0x00 7FFF 1984 EALLOW Protected Not EALLOW Protected Not EALLOW Protected Not EALLOW Protected Not EALLOW Protected Not EALLOW Protected † Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written). December 2004 − Revised September 2006 SGUS053B 27 Functional Overview 3.4 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3−7. Table 3−7. Device Emulation Registers NAME ADDRESS RANGE SIZE (x16) DEVICECNF 0x00 0880 0x00 0881 2 Device Configuration Register reserved 0x00 0882 1 Not supported on Revision C and later silicon DEVICEID 0x00 0883 1 Device ID Register (0x0003 − Silicon − Rev. C and D) Device ID Register (0x0004 − Reserved) Device ID Register (0x0005 − Silicon − Rev. E) PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protection Range Address Register reserved 0x00 0886 0x00 09FF 378 3.5 DESCRIPTION External Interface, XINTF This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 device. The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The external interface on the 2812 is mapped into five fixed zones shown in Figure 3−3. Figure 3−3 shows the 2812 XINTF signals. 28 SGUS053B December 2004 − Revised September 2006 Functional Overview Data Space Prog Space 0x00 0000 XD(15:0) XA(18:0) 0x00 2000 XINTF Zone 0 (8K × 16) 0x00 4000 XINTF Zone 1 (8K × 16) XZCS0 XZCS1 XZCS0AND1 0x00 6000 0x08 0000 XINTF Zone 2 (512K × 16) XZCS2 0x10 0000 XINTF Zone 6 (512K × 16) XZCS6 XZCS6AND7 0x18 0000 0x3F C000 XINTF Zone 7 (16K × 16) (mapped here if MP/MC = 1) 0x40 0000 XZCS7 XWE XRD XR/W XREADY XMP/MC XHOLD XHOLDA XCLKOUT NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled. B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals. C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external memory that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1. D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the MP/MC mode) then any external memory is still accessible via Zone 6 address space. Figure 3−3. External Interface Block Diagram December 2004 − Revised September 2006 SGUS053B 29 Functional Overview The operation and timing of the external interface, can be controlled by the registers listed in Table 3−8. Table 3−8. XINTF Configuration and Control Register Mappings ADDRESS SIZE (x16) DESCRIPTION XTIMING0 NAME 0x00 0B20 2 XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register XTIMING1 0x00 0B22 2 XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register XTIMING2 0x00 0B24 2 XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register XTIMING6 0x00 0B2C 2 XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register XTIMING7 0x00 0B2E 2 XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register XINTCNF2 0x00 0B34 2 XINTF Configuration Register can access as two 16-bit registers or one 32-bit register XBANK 0x00 0B38 1 XINTF Bank Control Register XREVISION 0x00 0B3A 1 XINTF Revision Register 3.5.1 Timing Registers XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6−27. For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x DSP External Interface (XINTF) Reference Guide (SPRU067). 3.5.2 XREVISION Register The XREVISION register contains a unique number to identify the particular version of XINTF used in the product. For the 2812, this register is configured as described in Table 3−9. Table 3−9. XREVISION Register Bit Definitions BIT(S) 15−0 30 NAME REVISION SGUS053B TYPE R RESET DESCRIPTION 0x0004 Current XINTF Revision. For internal use/reference. Test purposes only. Subject to change. December 2004 − Revised September 2006 Functional Overview 3.6 Interrupts Figure 3−4 shows how the various interrupt sources are multiplexed within the F2812 device. Peripherals (SPI, SCI, McBSP, CAN, EV, ADC) (41 Interrupts) WDINT WAKEINT INT1 to INT12 96 Interrupts† LPMINT PIE Interrupt Control Watchdog Low-Power Modes XINT1 XINT1CR(15:0) XINT1CTR(15:0) Interrupt Control XINT2 XINT2CR(15:0) C28x CPU XINT2CTR(15:0) TINT0 TIMER 0 TINT2 INT14 TIMER 2 (for RTOS) TINT1 TIMER 1 (for RTOS) MUX INT13 GPIO MUX select enable NMI Interrupt Control XNMI_XINT13 XNMICR(15:0) XNMICTR(15:0) † Out of a possible 96 interrupts, 45 are currently used by peripherals. Figure 3−4. Interrupt Sources December 2004 − Revised September 2006 SGUS053B 31 Functional Overview Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F2812, 45 of these are used by peripherals as shown in Table 3−10. IFR(12:1) INTM IER(12:1) INT1 INT2 1 MUX INT11 INT12 (Flag) INTx Global Enable (Enable) INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 MUX PIEACKx (Enable/Flag) (Enable) (Flag) PIEIERx(8:1) PIEIFRx(8:1) CPU 0 From Peripherals or External Interrupts Figure 3−5. Multiplexing of Interrupts Using the PIE Block Table 3−10. PIE Peripheral Interrupts† CPU INTERRUPTS PIE INTERRUPTS INTx.8 INTx.7 INTx.6 INTx.5 INT1 WAKEINT (LPM/WD) TINT0 (TIMER 0) ADCINT (ADC) XINT2 INT2 reserved T1OFINT (EV-A) T1UFINT (EV-A) INT3 reserved CAPINT3 (EV-A) INT4 reserved INT5 INTx.4 INTx.3 INTx.2 INTx.1 XINT1 reserved PDPINTB (EV-B) PDPINTA (EV-A) T1CINT (EV-A) T1PINT (EV-A) CMP3INT (EV-A) CMP2INT (EV-A) CMP1INT (EV-A) CAPINT2 (EV-A) CAPINT1 (EV-A) T2OFINT (EV-A) T2UFINT (EV-A) T2CINT (EV-A) T2PINT (EV-A) T3OFINT (EV-B) T3UFINT (EV-B) T3CINT (EV-B) T3PINT (EV-B) CMP6INT (EV-B) CMP5INT (EV-B) CMP4INT (EV-B) reserved CAPINT6 (EV-B) CAPINT5 (EV-B) CAPINT4 (EV-B) T4OFINT (EV-B) T4UFINT (EV-B) T4CINT (EV-B) T4PINT (EV-B) INT6 reserved reserved MXINT (McBSP) MRINT (McBSP) reserved reserved SPITXINTA (SPI) SPIRXINTA (SPI) INT7 reserved reserved reserved reserved reserved reserved reserved reserved INT8 reserved reserved reserved reserved reserved reserved reserved reserved ECAN0INT (CAN) SCITXINTB (SCI-B) SCIRXINTB (SCI-B) SCITXINTA (SCI-A) SCIRXINTA (SCI-A) INT9 reserved reserved ECAN1INT (CAN) INT10 reserved reserved reserved reserved reserved reserved reserved reserved INT11 reserved reserved reserved reserved reserved reserved reserved reserved INT12 reserved reserved reserved reserved reserved reserved reserved reserved † Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these interrupts can be used as software interrupts if they are enabled at the PIEIFRx level. 32 SGUS053B December 2004 − Revised September 2006 Functional Overview Table 3−11. PIE Configuration and Control Registers NAME ADDRESS Size (x16) DESCRIPTION PIECTRL 0x0000−0CE0 1 PIE, Control Register PIEACK 0x0000−0CE1 1 PIE, Acknowledge Register PIEIER1 0x0000−0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0000−0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0000−0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0000−0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0000−0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0000−0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0000−0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0000−0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0000−0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0000−0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0000−0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0000−0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0000−0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0000−0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0000−0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0000−0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0000−0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0000−0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0000−0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0000−0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0000−0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0000−0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0000−0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0000−0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0000−0CFA 0x0000−0CFF 6 Reserved Note: The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. December 2004 − Revised September 2006 SGUS053B 33 Functional Overview 3.6.1 External Interrupts Table 3−12. External Interrupts Registers ADDRESS SIZE (x16) XINT1CR NAME 0x00 7070 1 XINT1 control register DESCRIPTION XINT2CR 0x00 7071 1 XINT2 control register reserved 0x00 7072 0x00 7076 5 XNMICR 0x00 7077 1 XNMI control register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register reserved 0x00 707A 0x00 707E 5 XNMICTR 0x00 707F 1 XNMI counter register Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078). 34 SGUS053B December 2004 − Revised September 2006 Functional Overview 3.7 System Control This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3−6 shows the various clock and reset domains in the F2812 device that is discussed. Reset XRS Watchdog Block SYSCLKOUT Peripheral Reset CLKIN C28x CPU X1/XCLKIN PLL (See Note A) OSC Power Modes Control System Control Registers eCAN Peripheral Bus Low-Speed Prescaler I/O LSPCLK Low-Speed Peripherals SCI-A/B, SPI, McBSP I/O GPIO MUX GPIOs HSPCLK High-Speed Prescaler Peripheral Registers XF_XPLLDIS Clock Enables Peripheral Registers Peripheral Registers X2 High-Speed Peripherals EV-A/B I/O HSPCLK ADC Registers 12-Bit ADC 16 ADC Inputs NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency. Figure 3−6. Clock and Reset Domains December 2004 − Revised September 2006 SGUS053B 35 Functional Overview The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3−13. Table 3−13. PLL, Clocking, Watchdog, and Low-Power Mode Registers† NAME ADDRESS SIZE (x16) reserved 0x00 7010 0x00 7017 8 reserved 0x00 7018 1 reserved 0x00 7019 1 HISPCP 0x00 701A 1 High-Speed Peripheral Clock Prescaler Register for HSPCLK clock LOSPCP DESCRIPTION 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock PCLKCR 0x00 701C 1 Peripheral Clock Control Register reserved 0x00 701D 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low Power Mode Control Register 1 reserved 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register‡ SCSR 0x00 7022 1 System Control & Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register reserved 0x00 7024 1 WDKEY 0x00 7025 1 reserved 0x00 7026 0x00 7028 3 WDCR 0x00 7029 1 reserved 0x00 702A 0x00 702F 6 Watchdog Reset Key Register Watchdog Control Register † All of the above registers can only be accessed by executing the EALLOW instruction. ‡ The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) does not reset PLLCR. 36 SGUS053B December 2004 − Revised September 2006 Functional Overview 3.8 OSC and PLL Block Figure 3−7 shows the OSC and PLL block on the F2812. XPLLDIS Latch XF_XPLLDIS XRS OSCCLK (PLL Disabled) X1/XCLKIN XCLKIN 0 CLKIN On-Chip Oscillator (OSC) PLL Bypass /2 CPU SYSCLKOUT 1 4-Bit PLL Select X2 PLL 4-Bit PLL Select PLL Block Figure 3−7. OSC and PLL Block The on-chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0] set the clocking ratio. Table 3−14. PLLCR Register Bit Definitions BIT(S) NAME TYPE XRS RESET† 15:4 reserved R=0 0:0 DESCRIPTION SYSCLKOUT = (XCLKIN x n)/2, where n is the PLL multiplication factor. 3:0 DIV R/W 0,0,0,0 Bit Value n SYSCLKOUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PLL Bypassed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 XCLKIN/2 XCLKIN/2 XCLKIN XCLKIN x 1.5 XCLKIN x 2 XCLKIN x 2.5 XCLKIN x 3 XCLKIN x 3.5 XCLKIN x 4 XCLKIN x 4.5 XCLKIN * 5 Reserved Reserved Reserved Reserved Reserved † The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed. December 2004 − Revised September 2006 SGUS053B 37 Functional Overview 3.8.1 Loss of Input Clock In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL still issues a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1 MHz to 4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to work. Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system. 3.9 PLL-Based Clock Module The F2812 has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131 072 XCLKIN cycles. The PLL-based clock module provides two modes of operation: • Crystal operation This mode allows the use of an external crystal/resonator to provide the time base to the device. • External clock source operation This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1/XCLKIN pin. X1/XCLKIN Cb1 (see Note A) X2 Crystal X1/XCLKIN Cb2 (see Note A) (a) X2 External Clock Signal (Toggling 0 −VDD) NC (b) NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that ensures start-up and stability over the entire operating range. Figure 3−8. Recommended Crystal / Clock Connection Table 3−15. Possible PLL Configuration Modes PLL MODE 38 REMARKS SYSCLKOUT PLL Disabled Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin. PLL Bypassed Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed. However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before feeding it to the CPU. XCLKIN/2 PLL Enabled Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to t he CPU. (XCLKIN x n) / 2 SGUS053B XCLKIN December 2004 − Revised September 2006 Functional Overview 3.10 External Reference Oscillator Clock Option The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below: 3.11 • Fundamental mode, parallel resonant • CL (load capacitance) = 12 pF • CL1 = CL2 = 24 pF • Cshunt = 6 pF • ESR range = 25 to 40 Ω Watchdog Block The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog counter. Figure 3−9 shows the various functional blocks within the watchdog module. WDCR (WDPS(2:0)) WDCR (WDDIS) WDCNTR(7:0) OSCCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Generate Output Pulse (512 OSCCLKs) Bad Key Watchdog 55 + AA Key Detector Good Key WDRST WDINT XRS Core-reset WDCR (WDCHK(2:0)) WDRST (See Note A) 1 0 Bad WDCHK Key SCSR (WDENINT) 1 NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles. Figure 3−9. Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module runs off the PLL clock or the oscillator clock. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.12, Low-Power Modes Block, for more details. December 2004 − Revised September 2006 SGUS053B 39 Functional Overview In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG. 3.12 Low-Power Modes Block The low-power modes on the F2812 are similar to the 240x devices. Table 3−16 summarizes the various modes. Table 3−16. F2812 Low-Power Modes MODE LPM(1:0) OSCCLK CLKIN SYSCLKOUT EXIT† Normal X,X on on on − on‡ XRS, WDINT, Any Enabled Interrupt, XNMI Debugger§ off off XRS, WDINT, XINT1, XNMI, T1/2/3/4CTRIP, C1/2/3/4/5/6TRIP, SCIRXDA, SCIRXDB, CANRX, Debugger§ off off XRS, XNMI, Debugger§ IDLE 0,0 on on on STANDBY 0,1 (watchdog still running) off HALT 1,X (oscillator and PLL turned off, watchdog not functional) † The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode is not exited and the device goes back into the indicated low power mode. ‡ The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional while on the 24x/240x the clock is turned off. § On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: All other signals (including XNMI) wakes the device from STANDBY mode if selected by the LPMCR1 register. The user needs to select which signal(s) wakes the device. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: Only the XRS and XNMI external signals can wake the device from HALT mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function. NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They are in whatever state the code left them in when the IDLE instruction was executed. 40 SGUS053B December 2004 − Revised September 2006 Peripherals 4 Peripherals The integrated peripherals of the F2812 are described in the following subsections: 4.1 • Three 32-bit CPU-Timers • Two event-manager modules (EVA, EVB) • Enhanced analog-to-digital converter (ADC) module • Enhanced controller area network (eCAN) module • Multichannel buffered serial port (McBSP) module • Serial communications interface modules (SCI-A, SCI-B) • Serial peripheral interface (SPI) module • Digital I/O and shared pin functions 32-Bit CPU-Timers 0/1/2 There are three 32-bit CPU-timers on the F2812 devices (CPU-TIMER0/1/2). CPU-Timers 1 and 2 are reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0 can be used in user applications. These timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB). NOTE: If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the application. Reset Timer Reload 16-Bit Timer Divide-Down TDDRH:TDDR SYSCLKOUT TCR.4 (Timer Start Status) 32-Bit Timer Period PRDH:PRD 16-Bit Prescale Counter PSCH:PSC Borrow 32-Bit Counter TIMH:TIM Borrow TINT Figure 4−1. CPU-Timers December 2004 − Revised September 2006 SGUS053B 41 Peripherals In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4−2. INT1 to INT12 PIE TINT0 CPU-TIMER 0 C28x INT13 CPU-TIMER 1 (Reserved for TI system functions) TINT1 XINT13 INT14 TINT2 CPU-TIMER 2 (Reserved for TI system functions) NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B) The general operation of the timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the value in the period register PRDH:PRD. The counter register, decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4−1 are used to configure the timers. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078). 42 SGUS053B December 2004 − Revised September 2006 Peripherals Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers NAME ADDRESS SIZE (x16) TIMER0TIM 0x00 0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x00 0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x00 0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x00 0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x00 0C04 1 CPU-Timer 0, Control Register reserved 0x00 0C05 1 TIMER0TPR 0x00 0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x00 0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x00 0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x00 0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x00 0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x00 0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x00 0C0C 1 CPU-Timer 1, Control Register reserved 0x00 0C0D 1 TIMER1TPR 0x00 0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x00 0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x00 0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x00 0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x00 0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x00 0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x00 0C14 1 CPU-Timer 2, Control Register reserved 0x00 0C15 1 TIMER2TPR 0x00 0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x00 0C17 1 CPU-Timer 2, Prescale Register High reserved 0x00 0C18 0x00 0C3F 40 December 2004 − Revised September 2006 DESCRIPTION SGUS053B 43 Peripherals 4.2 Event Manager Modules (EVA, EVB) The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 4−2 shows the module and signal names used. Table 4−2 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature. Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. Table 4−3 lists the EVA registers. For more information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number SPRU065). Table 4−2. Module and Signal Names for EVA and EVB EVA EVENT MANAGER MODULES EVB MODULE SIGNAL MODULE SIGNAL GP Timers GP Timer 1 GP Timer 2 T1PWM/T1CMP T2PWM/T2CMP GP Timer 3 GP Timer 4 T3PWM/T3CMP T4PWM/T4CMP Compare Units Compare 1 Compare 2 Compare 3 PWM1/2 PWM3/4 PWM5/6 Compare 4 Compare 5 Compare 6 PWM7/8 PWM9/10 PWM11/12 Capture Units Capture 1 Capture 2 Capture 3 CAP1 CAP2 CAP3 Capture 4 Capture 5 Capture 6 CAP4 CAP5 CAP6 QEP Channels QEP1 QEP2 QEPI1 QEP1 QEP2 QEP3 QEP4 QEPI2 QEP3 QEP4 Direction External Clock TDIRA TCLKINA Direction External Clock TDIRB TCLKINB Compare C1TRIP C2TRIP C3TRIP Compare C4TRIP C5TRIP C6TRIP External Clock Inputs External Trip Inputs External Trip Inputs T1CTRIP_PDPINTA† T2CTRIP/EVASOC T3CTRIP_PDPINTB† T4CTRIP/EVBSOC † In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB. 44 SGUS053B December 2004 − Revised September 2006 Peripherals Table 4−3. EVA Registers† NAME ADDRESS SIZE (x16) GPTCONA 0x00 7400 1 GP Timer Control Register A DESCRIPTION T1CNT 0x00 7401 1 GP Timer 1 Counter Register T1CMPR 0x00 7402 1 GP Timer 1 Compare Register T1PR 0x00 7403 1 GP Timer 1 Period Register T1CON 0x00 7404 1 GP Timer 1 Control Register T2CNT 0x00 7405 1 GP Timer 2 Counter Register T2CMPR 0x00 7406 1 GP Timer 2 Compare Register T2PR 0x00 7407 1 GP Timer 2 Period Register T2CON 0x00 7408 1 GP Timer 2 Control Register EXTCONA‡ 0x00 7409 1 GP Extension Control Register A COMCONA 0x00 7411 1 Compare Control Register A ACTRA 0x00 7413 1 Compare Action Control Register A DBTCONA 0x00 7415 1 Dead-Band Timer Control Register A CMPR1 0x00 7417 1 Compare Register 1 CMPR2 0x00 7418 1 Compare Register 2 CMPR3 0x00 7419 1 Compare Register 3 CAPCONA 0x00 7420 1 Capture Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two-Level Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two-Level Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two-Level Deep Capture FIFO Stack 3 CAP1FBOT 0x00 7427 1 Bottom Register Of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register Of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Register Of Capture FIFO Stack 3 EVAIMRA 0x00 742C 1 Interrupt Mask Register A EVAIMRB 0x00 742D 1 Interrupt Mask Register B EVAIMRC 0x00 742E 1 Interrupt Mask Register C EVAIFRA 0x00 742F 1 Interrupt Flag Register A EVAIFRB 0x00 7430 1 Interrupt Flag Register B EVAIFRC 0x00 7431 1 Interrupt Flag Register C † The EV-B register set is identical except the address range is from 0x00−7500 to 0x00−753F. The above registers are mapped to Zone 2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results. ‡ New register compared to 24x/240x December 2004 − Revised September 2006 SGUS053B 45 Peripherals GPTCONA(12:4), CAPCONA(8), EXTCONA[0] EVAENCLK EVATO ADC (Internal) T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP Control Logic EVASOC ADC (External) Output T1PWM_T1CMP Logic Timer 1 Compare 16 T1CON(5,4) GPTCONA(1,0) TCLKINA T1CON(1) clock GP Timer 1 HSPCLK Prescaler dir T1CON(10:8) 16 TDIRA T1CON(15:11,6,3,2) Full Compare 1 SVPWM Peripheral Bus Full Compare 2 State Machine Full Compare 3 ACTRA(15:12), COMCONA(15:5,2:0) PWM1 PWM2 PWM3 Output Logic DeadBand Logic PWM4 PWM5 PWM6 DBTCONA(15:0) COMCONA(12), T1CON(13:11) ACTRA(11:0) Output Timer 2 Compare T2PWM_T2CMP Logic 16 T2CON(5,4) T2CON(1) GPTCONA(3,2) TCLKINA GP Timer 2 clock dir reset Prescaler HSPCLK QEPCLK 16 T2CON(10:8) T2CON(15:11,7,6,3,2,0) QEP CAPCONA(10,9) QEPDIR Logic 16 TDIRA CAP1_QEP1 CAP2_QEP2 Capture Units CAP3_QEPI1 Index Qual CAPCONA(15:12,7:0) EXTCONA(1:2) NOTE A: The EVB module is similar to the EVA module. Figure 4−3. Event Manager A Functional Block Diagram (See Note A) 46 SGUS053B December 2004 − Revised September 2006 Peripherals 4.2.1 General-Purpose (GP) Timers There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes: • A 16-bit timer, up-/down-counter, TxCNT, for reads or writes • A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes • A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes • A 16-bit timer-control register,TxCON, for reads or writes • Selectable internal or external input clocks • A programmable prescaler for internal or external clock inputs • Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts • A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode is selected) The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up / down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. 4.2.2 Full-Compare Units There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. 4.2.3 Programmable Deadband Generator Deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTRx register. 4.2.4 PWM Waveform Generation Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares. 4.2.5 Double Update PWM Mode The F2812 Event Manager supports Double Update PWM Mode. This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period. To support this mode, the compare register that determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in F2812 Event Managers are all buffered and support three compare value reload/update (value in buffer becoming active) modes. These modes have earlier been documented as compare value reload conditions. The reload condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for compare value reload. December 2004 − Revised September 2006 SGUS053B 47 Peripherals 4.2.6 PWM Characteristics Characteristics of the PWMs are as follows: • 16-bit registers • Wide range of programmable deadband for the PWM output pairs • Change of the PWM carrier frequency for PWM frequency wobbling as needed • Change of the PWM pulse widths within and after each PWM period as needed • External-maskable power and drive-protection interrupts • Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms • Minimized CPU overhead using auto-reload of the compare and period registers • The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register. • 4.2.7 − PDPINTA pin status is reflected in bit 8 of COMCONA register. − PDPINTB pin status is reflected in bit 8 of COMCONB register. EXTCON register bits provide options to individually trip control for each PWM pair of signals Capture Unit The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits. • 4.2.8 Capture units include the following features: − One 16-bit capture control register, CAPCONx (R/W) − One 16-bit capture FIFO status register, CAPFIFOx − Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base − Three 16-bit 2-level-deep FIFO stacks, one for each capture unit − Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.] − User-specified transition (rising edge, falling edge, or both edges) detection − Three maskable interrupt flags, one for each capture unit − The capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture function. Quadrature-Encoder Pulse (QEP) Circuit Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin. 48 SGUS053B December 2004 − Revised September 2006 Peripherals 4.2.9 External ADC Start-of-Conversion EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively. 4.3 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4−4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include: • 12-bit ADC core with built-in S/H • Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.) • Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS • 16-channel, MUXed inputs • Autosequencing capability provides up to 16 autoconversions in a single session. Each conversion can be programmed to select any 1 of 16 input channels • Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) • Sixteen result registers (individually addressable) to store conversion values − The digital value of the input analog voltage is derived by: when input ≤ 0 V Digital Value + 0, Digital Value + 4096 4095 Input Analog Voltage * ADCLO, 3 Digital Value + 4095, • when 0 V < input < 3 V when input ≥ 3 V Multiple triggers as sources for the start-of-conversion (SOC) sequence − S/W − software immediate start − EVA − Event manager A (multiple event sources within EVA) − EVB − Event manager B (multiple event sources within EVB) • Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS • Sequencer can operate in start/stop mode, allowing multiple time-sequenced triggers to synchronize conversions • EVA and EVB triggers can operate independently in dual-sequencer mode • Sample-and-hold (S/H) acquisition time window has separate prescale control The ADC module in the F2812 has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4−4 shows the block diagram of the F2812 ADC module. The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results. December 2004 − Revised September 2006 SGUS053B 49 Peripherals System Control Block SYSCLKOUT High-Speed Prescaler ADCENCLK C28x HSPCLK Analog MUX Result Registers Result Reg 0 ADCINA0 70A8h Result Reg 1 S/H ADCINA7 12-Bit ADC Module Result Reg 7 70AFh Result Reg 8 70B0h Result Reg 15 70B7h ADCINB0 S/H ADCINB7 ADC Control Registers S/W EVA SOC Sequencer 1 Sequencer 2 ADCSOC SOC S/W EVB Figure 4−4. Block Diagram of the F2812 ADC Module To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2 , AVDDREFBG ) from the digital supply. Figure 4−5 shows the ADC pin connections for the F2812 device. Notes: 1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK). 2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows: ADCENCLK: On reset, this signal is low. While reset is active-low (XRS), the clock to the register still functions. This is necessary to make sure all registers and modes go into their default reset state. The analog module is in a low-power inactive state. As soon as reset goes high, then the clock to the registers is disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers is enabled and the analog module is enabled. There is a certain time delay (ms range) before the ADC is stable and can be used. HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode stops the clock to the CPU, which stops the HSPCLK. Therefore the ADC register logic is turned off indirectly. 50 SGUS053B December 2004 − Revised September 2006 Peripherals Figure 4−5 shows the ADC pin-biasing for internal reference and Figure 4−6 shows the ADC pin-biasing for external reference. ADCINA[7:0] ADCINB[7:0] ADCLO Test Pin ADCBGREFIN† ADC 16-Channel Analog Inputs Analog input 0−3 V with respect to ADCLO Connect to Analog Ground 24.9 k/20 k (See Note C) ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Output ADCREFP ADC Reference Medium Output ADCREFM ADC Analog Power VDDA1 VDDA2 VSSA1 VSSA2 Analog 3.3 V Analog 3.3 V ADC Reference Power AVDDREFBG AVSSREFBG Analog 3.3 V ADC Analog I/O Power VDDAIO VSSAIO ADC Digital Power VDD1 VSS1 10 F‡ 10 F‡ ADCREFP and ADCREFM should not be loaded by external circuitry Analog 3.3 V Analog Ground 1.8 V can use the same 1.8 V (or 1.9 V) supply as Digital Ground the digital core but separate the two with a ferrite bead or a filter † Provide access to this pin in PCB layouts. Intended for test purposes only. ‡ TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent NOTES: A. External decoupling capacitors are recommended on all power pins. B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. C. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz. Figure 4−5. ADC Pin Connections With Internal Reference (See Notes A and B) NOTE: The temperature rating of any recommended component must match the rating of the end product. December 2004 − Revised September 2006 SGUS053B 51 Peripherals Test Pin ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Input ADCREFP 2V ADC Reference Medium Input ADCREFM 1V ADC 16-Channel Analog Inputs Analog Input 0−3 V With Respect to ADCLO Connect to Analog Ground 24.9 k20 k (See Note C) 1 F − 10 F NOTES: A. B. C. D. ADC Analog Power VDDA1 VDDA2 VSSA1 VSSA2 Analog 3.3 V Analog 3.3 V ADC Reference Power AVDDREFBG AVSSREFBG Analog 3.3 V ADC Analog I/O Power VDDAIO VSSAIO ADC Digital Power VDD1 VSS1 (See Note D) 1 F −10 F Analog 3.3 V Analog Ground 1.8 V Can use the same 1.8-V (or 1.9-V) Digital Ground supply as the digital core but separate the two with a ferrite bead or a filter External decoupling capacitors are recommended on all power pins. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM) = 1 V $ 0.1% or better. External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP−ADCREFM determines the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more information. Figure 4−6. ADC Pin Connections With External Reference 52 SGUS053B December 2004 − Revised September 2006 Peripherals The ADC operation is configured, controlled, and monitored by the registers listed in Table 4−4. Table 4−4. ADC Registers† NAME ADDRESS SIZE (x16) ADCTRL1 0x00 7100 1 ADC Control Register 1 ADCTRL2 0x00 7101 1 ADC Control Register 2 ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x00 7107 1 ADC Auto-Sequence Status Register ADCRESULT0 0x00 7108 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9 ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x00 7113 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x00 7114 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15 ADCTRL3 0x00 7118 1 ADC Control Register 3 ADCST 0x00 7119 1 ADC Status Register reserved 0x00 711C 0x00 711F 4 DESCRIPTION † The above registers are Peripheral Frame 2 Registers. December 2004 − Revised September 2006 SGUS053B 53 Peripherals 4.4 Enhanced Controller Area Network (eCAN) Module The CAN module has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following properties: − Configurable as receive or transmit − Configurable with standard or extended identifier − Has a programmable receive mask − Supports data and remote frame − Composed of 0 to 8 bytes of data − Uses a 32-bit time stamp on receive and transmit message − Protects against reception of new message − Holds the dynamically programmable priority of transmit message − Employs a programmable interrupt scheme with two interrupt levels − Employs a programmable alarm on transmission or reception time-out • Low-power mode • Programmable wake-up on bus activity • Automatic reply to a remote request message • Automatic retransmission of a frame in case of loss of arbitration or error • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) • Self-test mode − Operates in a loopback mode receiving its own message. A dummy acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps. The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details. 54 SGUS053B December 2004 − Revised September 2006 Peripherals eCAN0INT Controls Address eCAN1INT Data 32 Enhanced CAN Controller Message Controller Mailbox RAM (512 Bytes) Memory Management Unit 32-Message Mailbox of 4 × 32-Bit Words 32 CPU Interface, Receive Control Unit, Timer Management Unit 32 eCAN Memory (512 Bytes) Registers and Message Objects Control 32 eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.3-V CAN Transceiver CAN Bus Figure 4−7. eCAN Block Diagram and Interface Circuit Table 4−5. 3.3-V eCAN Transceivers for the SM/SMJ320F2812 DSP PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE SLOPE CONTROL VREF OTHER TA SN65HVD230 3.3 V Standby Adjustable Yes −− −40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes −− −40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes −− −40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes −− −40°C to 125°C SN65HVD232 3.3 V None None None −− −40°C to 85°C SN65HVD232Q 3.3 V None None None −− −40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback −40°C to 125°C December 2004 − Revised September 2006 SGUS053B 55 Peripherals Table 4−5. 3.3-V eCAN Transceivers for the TMS320F2812 DSP (Continued) PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE SLOPE CONTROL VREF OTHER TA SN65HVD234 3.3 V Standby & Sleep Adjustable None −− −40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback −40°C to 125°C eCAN Control and Status Registers Mailbox Enable − CANME Mailbox Direction − CANMD Transmission Request Set − CANTRS Transmission Request Reset − CANTRR Transmission Acknowledge − CANTA eCAN Memory (512 Bytes) 6000h Abort Acknowledge − CANAA Received Message Pending − CANRMP Control and Status Registers Received Message Lost − CANRML 603Fh 6040h 607Fh 6080h 60BFh 60C0h 60FFh Remote Frame Pending − CANRFP Local Acceptance Masks (LAM) (32 × 32-Bit RAM) Global Acceptance Mask − CANGAM Message Object Time Stamps (MOTS) (32 × 32-Bit RAM) Bit-Timing Configuration − CANBTC Master Control − CANMC Error and Status − CANES Message Object Time-Out (MOTO) (32 × 32-Bit RAM) Transmit Error Counter − CANTEC Receive Error Counter − CANREC Global Interrupt Flag 0 − CANGIF0 Global Interrupt Mask − CANGIM Global Interrupt Flag 1 − CANGIF1 eCAN Memory RAM (512 Bytes) 6100h−6107h Mailbox 0 6108h−610Fh Mailbox 1 6110h−6117h Mailbox 2 6118h−611Fh Mailbox 3 6120h−6127h Mailbox 4 Mailbox Interrupt Mask − CANMIM Mailbox Interrupt Level − CANMIL Overwrite Protection Control − CANOPC TX I/O Control − CANTIOC RX I/O Control − CANRIOC Time Stamp Counter − CANTSC Time-Out Control − CANTOC Time-Out Status − CANTOS 61E0h−61E7h Mailbox 28 61E8h−61EFh Mailbox 29 61F0h−61F7h Mailbox 30 61F8h−61FFh Mailbox 31 Reserved Message Mailbox (16 Bytes) 61E8h−61E9h Message Identifier − MSGID 61EAh−61EBh Message Control − MSGCTRL 61ECh−61EDh Message Data Low − MDL 61EEh−61EFh Message Data High − MDH Figure 4−8. eCAN Memory Map 56 SGUS053B December 2004 − Revised September 2006 Peripherals The CAN registers listed in Table 4−6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4−6. CAN Registers Map† REGISTER NAME ADDRESS SIZE (x32) CANME 0x00 6000 1 Mailbox enable DESCRIPTION CANMD 0x00 6002 1 Mailbox direction CANTRS 0x00 6004 1 Transmit request set CANTRR 0x00 6006 1 Transmit request reset CANTA 0x00 6008 1 Transmission acknowledge CANAA 0x00 600A 1 Abort acknowledge CANRMP 0x00 600C 1 Receive message pending CANRML 0x00 600E 1 Receive message lost CANRFP 0x00 6010 1 Remote frame pending CANGAM 0x00 6012 1 Global acceptance mask CANMC 0x00 6014 1 Master control CANBTC 0x00 6016 1 Bit-timing configuration CANES 0x00 6018 1 Error and status CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIF0 0x00 601E 1 Global interrupt flag 0 CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1 CANMIM 0x00 6024 1 Mailbox interrupt mask CANMIL 0x00 6026 1 Mailbox interrupt level CANOPC 0x00 6028 1 Overwrite protection control CANTIOC 0x00 602A 1 TX I/O control CANRIOC 0x00 602C 1 RX I/O control CANTSC 0x00 602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x00 6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x00 6032 1 Time-out status (Reserved in SCC mode) † These registers are mapped to Peripheral Frame 1. December 2004 − Revised September 2006 SGUS053B 57 Peripherals 4.5 Multichannel Buffered Serial Port (McBSP) Module The McBSP module has the following features: • Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features • Full-duplex communication • Double-buffered data registers which allow a continuous data stream • Independent framing and clocking for receive and transmit • External shift clock generation or an internal programmable frequency shift clock • A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits • 8-bit data transfers with LSB or MSB first • Programmable polarity for both frame synchronization and data clocks • HIghly programmable internal clock and frame generation • Support A-bis mode • Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices • Works with SPI-compatible devices • Two 16 x 16-level FIFO for Transmit channel • Two 16 x 16-level FIFO for Receive channel The following application interfaces can be supported on the McBSP: • T1/E1 framers • MVIP switching-compatible and ST-BUS-compliant devices including: • − MVIP framers − H.100 framers − SCSA framers − IOM-2 compliant devices − AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) − IIS-compliant devices McBSP clock rate = CLKG = CLKR.† CLKSRG , where CLKSRG source could be LSPCLK, CLKX, or (1 ) CLKGDIV) TMS320C54x and TMS320C55x are trademarks of Texas Instruments. † Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum. 58 SGUS053B December 2004 − Revised September 2006 Peripherals Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of Peripheral Frame 2. Peripheral Write Bus TX FIFO Interrupt MXINT To CPU TX Interrupt Logic McBSP Transmit Interrupt Select Logic TX FIFO _15 TX FIFO _15 — — TX FIFO _1 TX FIFO _1 TX FIFO _0 TX FIFO _0 TX FIFO Registers 16 DXR2 Transmit Buffer LSPCLK McBSP Registers and Control Logic 16 DXR1 Transmit Buffer 16 16 FSX Compand Logic CLKX XSR2 XSR1 DX RSR2 RSR1 DR 16 CLKR 16 Expand Logic FSR McBSP RBR2 Register RBR1 Register 16 16 DRR2 Receive Buffer DRR1 Receive Buffer 16 McBSP Receive Interrupt Select Logic MRINT RX Interrupt Logic To CPU RX FIFO _15 RX FIFO Interrupt 16 RX FIFO _15 — — RX FIFO _1 RX FIFO _1 RX FIFO _0 RX FIFO _0 RX FIFO Registers Peripheral Read Bus Figure 4−9. McBSP Module With FIFO December 2004 − Revised September 2006 SGUS053B 59 Peripherals Table 4−7 provides a summary of the McBSP registers. Table 4−7. McBSP Register Summary NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION DATA REGISTERS, RECEIVE, TRANSMIT† − − − 0x0000 McBSP Receive Buffer Register − − − 0x0000 McBSP Receive Shift Register − − − 0x0000 McBSP Transmit Shift Register DRR2 00 R 0x0000 McBSP Data Receive Register 2 − Read First if the word size is greater than 16 bits, else ignore DRR2 DRR1 01 R 0x0000 McBSP Data Receive Register 1 − Read Second if the word size is greater than 16 bits, else read DRR1 only DXR2 02 W 0x0000 McBSP Data Transmit Register 2 − Write First if the word size is greater than 16 bits, else ignore DXR2 DXR1 03 W 0x0000 McBSP Data Transmit Register 1 − Write Second if the word size is greater than 16 bits, else write to DXR1 only McBSP CONTROL REGISTERS SPCR2 04 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 05 R/W 0x0000 McBSP Serial Port Control Register 1 RCR2 06 R/W 0x0000 McBSP Receive Control Register 2 RCR1 07 R/W 0x0000 McBSP Receive Control Register 1 XCR2 08 R/W 0x0000 McBSP Transmit Control Register 2 XCR1 09 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0B R/W 0x0000 McBSP Sample Rate Generator Register 1 MULTICHANNEL CONTROL REGISTERS MCR2 0C R/W 0x0000 McBSP Multichannel Register 2 MCR1 0D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 12 R/W 0x0000 McBSP Pin Control Register RCERC 13 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 14 R/W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 15 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 16 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D † DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode. ‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers. 60 SGUS053B December 2004 − Revised September 2006 Peripherals Table 4−7. McBSP Register Summary (Continued) NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION MULTICHANNEL CONTROL REGISTERS (CONTINUED) RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H FIFO MODE REGISTERS (applicable only in FIFO mode) FIFO Data Registers‡ DRR2 00 R 0x0000 McBSP Data Receive Register 2 − Top of receive FIFO − Read First FIFO pointers does not advance DRR1 01 R 0x0000 McBSP Data Receive Register 1 − Top of receive FIFO − Read Second for FIFO pointers to advance DXR2 02 W 0x0000 McBSP Data Transmit Register 2 − Top of transmit FIFO − Write First FIFO pointers does not advance DXR1 03 W 0x0000 McBSP Data Transmit Register 1 − Top of transmit FIFO − Write Second for FIFO pointers to advance MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R/W 0x201F McBSP Receive FIFO Register MFFCT 22 R/W 0x0000 McBSP FIFO Control Register MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register FIFO Control Registers MFFST 24 R/W 0x0000 McBSP FIFO Status Register † DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode. ‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers. December 2004 − Revised September 2006 SGUS053B 61 Peripherals 4.6 Serial Communications Interface (SCI) Module The F2812 device include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. Features of each SCI module include: • Two external pins: − SCITXD: SCI transmit-output pin − SCIRXD: SCI receive-input pin NOTE: • Both pins can be used as GPIO if not used for SCI. Baud rate programmable to 64K different rates† − Baud rate = = • LSPCLK , when BRR ≠ 0 (BRR ) 1) * 8 LSPCLK , when BRR = 0 16 Data-word format − One start bit − Data-word length programmable from one to eight bits − Optional even/odd/no parity bit − One or two stop bits • Four error-detection flags: parity, overrun, framing, and break detection • Two wake-up multiprocessor modes: idle-line and address bit • Half- or full-duplex operation • Double-buffered receive and transmit functions • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. − Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) − Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) • Separate enable bits for transmitter and receiver interrupts (except BRKDT) • Max bit rate + 150 MHz + 9.375 2 8 10 6 bńs † Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum. 62 SGUS053B December 2004 − Revised September 2006 Peripherals • NRZ (non-return-to-zero) format • Ten SCI module control registers located in the control register frame beginning at address 7050h NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7 −0), and the upper byte (15 −8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 16-level transmit/receive FIFO The SCI port operation is configured and controlled by the registers listed in Table 4−8 and Table 4−9. Table 4−8. SCI-A Registers† NAME ADDRESS SIZE (x16) SCICCRA 0x00 7050 1 SCI-A Communications Control Register DESCRIPTION SCICTL1A 0x00 7051 1 SCI-A Control Register 1 SCIHBAUDA 0x00 7052 1 SCI-A Baud Register, High Bits SCILBAUDA 0x00 7053 1 SCI-A Baud Register, Low Bits SCICTL2A 0x00 7054 1 SCI-A Control Register 2 SCIRXSTA 0x00 7055 1 SCI-A Receive Status Register SCIRXEMUA 0x00 7056 1 SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x00 7057 1 SCI-A Receive Data Buffer Register SCITXBUFA 0x00 7059 1 SCI-A Transmit Data Buffer Register SCIFFTXA 0x00 705A 1 SCI-A FIFO Transmit Register SCIFFRXA 0x00 705B 1 SCI-A FIFO Receive Register SCIFFCTA 0x00 705C 1 SCI-A FIFO Control Register SCIPRIA 0x00 705F 1 SCI-A Priority Control Register † Shaded registers are new registers for the FIFO mode. Table 4−9. SCI-B Registers†‡ NAME ADDRESS SIZE (x16) DESCRIPTION SCICCRB 0x00 7750 1 SCI-B Communications Control Register SCICTL1B 0x00 7751 1 SCI-B Control Register 1 SCIHBAUDB 0x00 7752 1 SCI-B Baud Register, High Bits SCILBAUDB 0x00 7753 1 SCI-B Baud Register, Low Bits SCICTL2B 0x00 7754 1 SCI-B Control Register 2 SCIRXSTB 0x00 7755 1 SCI-B Receive Status Register SCIRXEMUB 0x00 7756 1 SCI-B Receive Emulation Data Buffer Register SCIRXBUFB 0x00 7757 1 SCI-B Receive Data Buffer Register SCITXBUFB 0x00 7759 1 SCI-B Transmit Data Buffer Register SCIFFTXB 0x00 775A 1 SCI-B FIFO Transmit Register SCIFFRXB 0x00 775B 1 SCI-B FIFO Receive Register SCIFFCTB 0x00 775C 1 SCI-B FIFO Control Register SCIPRIB 0x00 775F 1 SCI-B Priority Control Register † Shaded registers are new registers for the FIFO mode. ‡ Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. December 2004 − Revised September 2006 SGUS053B 63 Peripherals Figure 4−10 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode Parity Even/Odd Enable TXSHF Register TXENA 8 SCICCR.6 SCICCR.5 TXRDY TXWAKE SCICTL1.3 1 Transmitter−Data Buffer Register 8 TX INT ENA SCICTL2.7 SCICTL2.0 TX FIFO Interrupts TX FIFO _0 SCITXD TX EMPTY SCICTL2.6 TXINT TX Interrupt Logic TX FIFO _1 −−−−− To CPU TX FIFO _15 WUT SCI TX Interrupt select logic SCITXBUF.7−0 TX FIFO registers SCIFFENA AutoBaud Detect logic SCIFFTX.14 SCIHBAUD. 15 − 8 Baud Rate MSbyte Register SCIRXD RXSHF Register SCIRXD RXWAKE LSPCLK SCIRXST.1 SCILBAUD. 7 − 0 Baud Rate LSbyte Register RXENA 8 SCICTL1.0 SCICTL2.1 Receive Data Buffer register SCIRXBUF.7−0 RXRDY SCIRXST.6 8 RX FIFO _15 BRKDT −−−−− SCIRXST.5 RX FIFO_1 RX FIFO _0 SCIRXBUF.7−0 RX/BK INT ENA RX FIFO Interrupts RX Interrupt Logic To CPU RX FIFO registers SCIRXST.7 SCIRXST.4 − 2 RX Error FE OE PE RXINT RXFFOVF SCIFFRX.15 RX Error RX ERR INT ENA SCICTL1.6 SCI RX Interrupt select logic Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram 64 SGUS053B December 2004 − Revised September 2006 Peripherals 4.7 Serial Peripheral Interface (SPI) Module The F2812 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: • Four external pins: − SPISOMI: SPI slave-output/master-input pin − SPISIMO: SPI slave-input/master-output pin − SPISTE: SPI slave transmit-enable pin − SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO, if the SPI module is not used. • Two operational modes: master and slave • Baud rate: 125 different programmable rates − LSPCLK , when BRR ≠ 0 (SPIBRR ) 1) when BRR = 0, 1, 2, 3 = LSPCLK , 4 Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum. Baud rate = • Data word length: one to sixteen data bits • Four clocking schemes (controlled by clock polarity and clock phase bits) include: − Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. − Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. − Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. • Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. • Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7 −0), and the upper byte (15 −8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control December 2004 − Revised September 2006 SGUS053B 65 Peripherals The SPI port operation is configured and controlled by the registers listed in Table 4−10. Table 4−10. SPI Registers NAME ADDRESS SIZE (x16) DESCRIPTION SPICCR 0x00 7040 1 SPI Configuration Control Register SPICTL 0x00 7041 1 SPI Operation Control Register SPISTS 0x00 7042 1 SPI Status Register SPIBRR 0x00 7044 1 SPI Baud Rate Register SPIRXEMU 0x00 7046 1 SPI Receive Emulation Buffer Register SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register SPIDAT 0x00 7049 1 SPI Serial Data Register SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register SPIFFRX 0x00 704B 1 SPI FIFO Receive Register SPIFFCT 0x00 704C 1 SPI FIFO Control Register SPIPRI 0x00 704F 1 SPI Priority Control Register NOTE: The above registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. 66 SGUS053B December 2004 − Revised September 2006 Peripherals Figure 4−11 is a block diagram of the SPI in slave mode. SPIFFENA Overrun INT ENA Receiver Overrun Flag SPIFFTX.14 RX FIFO registers SPISTS.7 SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 −−−−− SPIINT/SPIRXINT RX FIFO Interrupt RX Interrupt Logic RX FIFO _15 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.15 To CPU TX FIFO registers SPITXBUF TX FIFO _15 −−−−− TX Interrupt Logic TX FIFO Interrupt TX FIFO _1 TX FIFO _0 SPITXINT 16 SPI INT FLAG SPITXBUF Buffer Register 16 SPI INT ENA SPISTS.6 SPICTL.0 16 M M SPIDAT Data Register S S SW1 SPISIMO M M SPIDAT.15 − 0 S S SW2 SPISOMI Talk SPICTL.1 SPISTE† State Control Master/Slave SPI Char SPICCR.3 − 0 3 2 1 0 SW3 M SPI Bit Rate LSPCLK SPICTL.2 S S SPIBRR.6 − 0 6 5 4 3 2 1 0 Clock Polarity Clock Phase SPICCR.6 SPICTL.3 SPICLK M † SPISTE is driven low by the master for a slave device. Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) December 2004 − Revised September 2006 SGUS053B 67 Peripherals 4.8 GPIO MUX The GPIO Mux registers, are used to select the operation of shared pins on the F2812 device. The pins can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers). Table 4−11 lists the GPIO Mux Registers. Table 4−11. GPIO Mux Registers†‡§ NAME ADDRESS SIZE (x16) GPAMUX 0x00 70C0 1 GPIO A Mux Control Register REGISTER DESCRIPTION GPADIR 0x00 70C1 1 GPIO A Direction Control Register GPAQUAL 0x00 70C2 1 GPIO A Input Qualification Control Register reserved 0x00 70C3 1 GPBMUX 0x00 70C4 1 GPIO B Mux Control Register GPBDIR 0x00 70C5 1 GPIO B Direction Control Register GPBQUAL 0x00 70C6 1 GPIO B Input Qualification Control Register reserved 0x00 70C7 1 reserved 0x00 70C8 1 reserved 0x00 70C9 1 reserved 0x00 70CA 1 reserved 0x00 70CB 1 GPDMUX 0x00 70CC 1 GPIO D Mux Control Register GPDDIR 0x00 70CD 1 GPIO D Direction Control Register GPDQUAL 0x00 70CE 1 GPIO D Input Qualification Control Register reserved 0x00 70CF 1 GPEMUX 0x00 70D0 1 GPIO E Mux Control Register GPEDIR 0x00 70D1 1 GPIO E Direction Control Register GPEQUAL 0x00 70D2 1 GPIO E Input Qualification Control Register reserved 0x00 70D3 1 GPFMUX 0x00 70D4 1 GPIO F Mux Control Register GPFDIR 0x00 70D5 1 GPIO F Direction Control Register reserved 0x00 70D6 1 reserved 0x00 70D7 1 GPGMUX 0x00 70D8 1 GPIO G Mux Control Register GPGDIR 0x00 70D9 1 GPIO G Direction Control Register reserved 0x00 70DA 1 reserved 0x00 70DB 1 reserved 0x00 70DC 0x00 70DF 4 † Reserved locations returns undefined values and writes is ignored. ‡ Not all inputs supports input signal qualification. § These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system. 68 SGUS053B December 2004 − Revised September 2006 Peripherals If configured for Digital I/O mode, additional registers are provided for setting individual I/O signals (via the GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT registers). Table 4−12 lists the GPIO Data Registers. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078). Table 4−12. GPIO Data Registers†‡ NAME ADDRESS SIZE (x16) REGISTER DESCRIPTION GPADAT 0x00 70E0 1 GPIO A Data Register GPASET 0x00 70E1 1 GPIO A Set Register GPACLEAR 0x00 70E2 1 GPIO A Clear Register GPATOGGLE 0x00 70E3 1 GPIO A Toggle Register GPBDAT 0x00 70E4 1 GPIO B Data Register GPBSET 0x00 70E5 1 GPIO B Set Register GPBCLEAR 0x00 70E6 1 GPIO B Clear Register GPBTOGGLE 0x00 70E7 1 GPIO B Toggle Register reserved 0x00 70E8 1 reserved 0x00 70E9 1 reserved 0x00 70EA 1 reserved 0x00 70EB 1 GPDDAT 0x00 70EC 1 GPIO D Data Register GPDSET 0x00 70ED 1 GPIO D Set Register GPDCLEAR 0x00 70EE 1 GPIO D Clear Register GPDTOGGLE 0x00 70EF 1 GPIO D Toggle Register GPEDAT 0x00 70F0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register GPECLEAR 0x00 70F2 1 GPIO E Clear Register GPETOGGLE 0x00 70F3 1 GPIO E Toggle Register GPFDAT 0x00 70F4 1 GPIO F Data Register GPFSET 0x00 70F5 1 GPIO F Set Register GPFCLEAR 0x00 70F6 1 GPIO F Clear Register GPFTOGGLE 0x00 70F7 1 GPIO F Toggle Register GPGDAT 0x00 70F8 1 GPIO G Data Register GPGSET 0x00 70F9 1 GPIO G Set Register GPGCLEAR 0x00 70FA 1 GPIO G Clear Register GPGTOGGLE 0x00 70FB 1 GPIO G Toggle Register reserved 0x00 70FC 0x00 70FF 4 † Reserved locations returns undefined values and writes is ignored. ‡ These registers are NOT EALLOW protected. The above registers are typically accessed regularly by the user. December 2004 − Revised September 2006 SGUS053B 69 Peripherals Figure 4−12 shows how the various register bits select the various modes of operation for GPIO function. GPxDAT/SET/CLEAR/TOGGLE Register Bit(s) GPxQUAL Register Digital I/O GPxMUX Register Bit 0 Peripheral I/O HighImpedance Control GPxDIR Register Bit 0 1 MUX 1 MUX SYSCLKOUT Input Qualification High-Impedance Enable (1) XRS Internal (Pullup or Pulldown) PIN NOTES: A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the corresponding direction bit is zero (input mode). B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0’s or all 1’s). This feature removes unwanted spikes from the input signal. Figure 4−12. GPIO/Peripheral Pin Multiplexing NOTE: The input function of the GPIO pin and the input path to the peripheral are always enabled. It is the output function of the GPIO pin that is multiplexed with the output path of the primary (peripheral) function. Since the output buffer of a pin connects back to the input buffer, any GPIO signal present at the pin is propagated to the peripheral module as well. Therefore, when a pin is configured for GPIO operation, the corresponding peripheral functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) puts PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins also puts the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1. 70 SGUS053B December 2004 − Revised September 2006 Development Support 5 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of F2812-based applications: Software Development Tools • Code Composer Studio Integrated Development Environment (IDE) − C/C++ Compiler − Code generation tools − Assembler/Linker − Cycle Accurate Simulator • Application algorithms • Sample applications code Hardware Development Tools 5.1 • 2812 eZdsp • JTAG-based emulators − SPI515, XDS510PP, XDS510PP Plus, XDS510 USB • Universal 5-V dc power supply • Documentation and cables Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all [TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F2812GHH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/ TMDX) through fully qualified production devices/tools (TMS / TMDS). TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS/SM Fully qualified production device SMJ Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development−support tools are shipped against the following disclaimer: Developmental product is intended for internal evaluation purposes. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. TMS320 is a trademark of Texas Instruments. December 2004 − Revised September 2006 SGUS053B 71 Development Support Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PBK) and temperature range (for example, A). Figure 5−1 provides a legend for reading the complete device name for any TMS320x28x family member. SM PREFIX TMX = TMP = TMS = SM = SMJ = 320 F 2812 HFG M TEMPERATURE RANGE A = −40°C to 85°C S = −40°C to 125°C M = −55°C to 125°C experimental device prototype device qualified device commercial processing MIL-PRF-38535 (QML) DEVICE FAMILY 320 = TMS320 DSP Family TECHNOLOGY F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O) C = ROM (1.8-V/1.9-V Core/3.3-V I/O) PACKAGE TYPE†‡ GHH = 179-ball MicroStar BGA PGF = 176-pin LQFP PBK = 128-pin LQFP HFG = 172-pin CQFP DEVICE 2810 2811 2812 † Not all combinations of processing options, temperature ranges and packages are available. ‡ BGA = Ball Grid Array LQFP = Low-Profile Quad Flatpack CQFP = Ceramic Quad Flatpack Figure 5−1. 28x Device Nomenclature 5.2 Documentation Support Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. Useful reference documentation includes: TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) describes the ADC module. The module is a 12−bit pipelined ADC. The analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample−and−hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits, referred to as the wrapper in this document, include programmable conversion sequencer, result registers, interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules. TMS320x281x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. TMS320x281x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV modules that provide a broad range of functions and features that are particularly useful in motion control and motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. 72 SGUS053B December 2004 − Revised September 2006 Development Support TMS320x281x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the external interface (XINTF) of the 281x digital signal processors (DSPs). TMS320x281x Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number SPRU061) describes the McBSP) available on the 281x devices. The McBSPs allow direct interface between a DSP and other devices in a system. TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078) describes the various interrupts and system control features of the 281x digital signal processors (DSPs). TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074) describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x DSP is compatible with the CAN 2.0B standard (active). TMS320x281x, 280x Peripheral Reference Guide (literature number SPRU566) describes the peripheral reference guides of the 28x digital signal processors (DSPs). TMS320x281x, 280x Serial Communication Interface (SCI) Reference Guide (literature number SPRU051) describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059) describes the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit−transfer rate. The SPI is used for communications between the DSP controller and external peripherals or another controller. 3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no additional system cost and no significant complication in interfacing with TTL and CMOS compatible components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based designs, good engineering practice should be exercised to minimize noise and EMI effects by proper component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal environment, with high and low voltage analog and switching signals, such as a motor control system. In addition, software techniques such as Random PWM method can be used by special features of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation. This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications. The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V − 5-V interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system’s noise and EMI effects are summarized in the last section. The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608) describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core. TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number SPRU625) describes development using DSP/BIOS. December 2004 − Revised September 2006 SGUS053B 73 Development Support TMS320C28x Assembly Language Tools User’s Guide (literature number SPRU513) describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. TMS320C28x Optimizing C Compiler User’s Guide (literature number SPRU514) describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com. To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number SPRS174), use the commentsatbooks.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site. 74 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the SM/SMJ320F2812 DSP. 6.1 Absolute Maximum Ratings Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. Supply voltage range, VDDIO , VDDA1, VDDA2, VDDAIO, and AVDDREFBG . . . . . . . . . . . . . − 0.3 V to 4.6 V Supply voltage range, VDD, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.5 V VDD3VFL range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO)† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Operating ambient temperature range, TA: M version (HFG)‡ . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C Storage temperature range, Tstg† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C † Continuous clamp current per pin is± 2 mA ‡ Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963). § Replaced by Q temperature option from silicon revision E onwards December 2004 − Revised September 2006 SGUS053B 75 Electrical Specifications Recommended Operating Conditions† 6.2 MIN VDDIO Device supply voltage, I/O NOM MAX UNIT 3.14 3.3 3.47 1.8 V (135 MHz) 1.71 1.8 1.89 1.9 V (150 MHz) 1.81 1.9 2 V VDD , VDD1 Device supply voltage, CPU VSS VDDA1 , VDDA2 , AVDDREFBG, VDDAIO Supply ground ADC supply voltage 3.14 3.3 3.47 V VDD3VFL Flash programming supply voltage 3.14 3.3 3.47 V fSYSCLKOUT Device clock frequency (system clock) VDD = 1.9 V ± 5% VDD = 1.8 V ± 5% VIH High-level input voltage XCLKIN (at 50 µA max) VIL Low-level input voltage IOH High-level output source current, VOH = 2.4 V Group 2‡ Low-level output sink current, VOL = VOL MAX All I/Os except Group 2 4 IOL Group 2‡ 8 TA Ambient temperature 0 All inputs except XCLKIN V V 2 150 2 135 2 VDDIO VDD 0.7VDD All inputs except XCLKIN MHz V 0.8 XCLKIN (at 50 µA max) 0.3VDD −4 All I/Os except Group 2 −8 M version − 55 V mA mA 125 °C MAX UNIT † See Section 6.7 for power sequencing of VDDIO , VDDAIO , VDD , VDDA1 / VDDA2 /AVDDREFBG , and VDD3VFL . ‡ Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1. In Revision C, EVA (GPIOA0−GPIOA15) and GPIOD0 are 4 mA drive. § Replaced by Q temperature option from silicon revision E onwards 6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIL Input current (low level) With pullup TEST CONDITIONS MIN IOH = IOHMAX TYP 2.4 IOH = 50 µA V VDDIO − 0.2 IOL = IOLMAX VDDIO = 3.3 V, VIN = 0 V 0.4 All I/Os† (including XRS) except EVB −80 −140 −190 GPIOB/EVB −13 −25 −35 With pulldown VDDIO = 3.3 V, VIN = 0 V ±2 With pullup VDDIO = 3.3 V, VIN = VDD ±2 With pulldown‡ VDDIO = 3.3 V, VIN = VDD V µA A IIH Input current (high level) IOZ Output current, high-impedance state (off-state) Ci Input capacitance 7 pF Co Output capacitance 7 pF µA 28 50 80 ±2 VO = VDDIO or 0 V µA † The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5. ‡ The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST. 76 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT MODE TEST CONDITIONS IDD IDDIO IDD3VFL IDDA† TYP MAX‡ TYP MAX‡ TYP MAX‡ TYP MAX‡ Operational All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is continuously transmitted out of the SCIA, SCIB, and CAN ports. The hardware multiplier is exercised. Code is running out of flash with 5 wait-states. 195 mA 230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA IDLE − Flash is powered down − XCLKOUT is turned off − All peripheral clocks are on, except ADC 125 mA 150 mA 5 mA 10 mA 2 µA 4 µA 1 µA 20 µA STANDBY − Flash is powered down − Peripheral clocks are turned off − Pins without an internal PU/PD are tied high/low 5 mA 10 mA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA HALT − Flash is powered down − Peripheral clocks are turned off − Pins without an internal PU/PD are tied high/low − Input clock is disabled 70 µA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA † IDDA includes current into VDDA1, VDDA2, VDD1, AVDDREFBG , and VDDAIO pins. ‡ MAX numbers are at 125°C, and max voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V). NOTE: HALT and STANDBY modes cannot be used when the PLL is disabled. December 2004 − Revised September 2006 SGUS053B 77 Electrical Specifications 6.5 Current Consumption Graphs 250 Current (mA) 200 150 100 50 0 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) IDD NOTES: A. B. C. D. IDDIO IDD3VFL IDDA Total 3.3−V current Test conditions are as defined in Table 6−5 for operational currents. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a trivial amount of current (<1 mA) drawn by VDD1. IDDA represents the current drawn by VDDA1 and VDDA2 rails. Total 3.3-V current is the sum of IDDIO, IDD3VFL, and IDDA. It includes a trivial amount of current (<1 mA) drawn by VDDAIO. . Figure 6−1. Typical Current Consumption Over Frequency 700 Power (mW) 600 500 400 300 200 100 0 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) TOTAL POWER Figure 6−2. Typical Power Consumption Over Frequency 78 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.6 Reducing Current Consumption 28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 6−1 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz)† PERIPHERAL MODULE IDD CURRENT REDUCTION (mA) eCAN 12 EVA 6 EVB 6 ADC 8‡ SCI 4 SPI 5 McBSP 13 † All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks are turned on. ‡ This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (ICCA) as well. 6.7 Power Sequencing Requirements SM320F2812 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. The current F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power sequencing circuit. • Option 1: In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG ) modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the recommended approach. • Option 2: Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins. 1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device. See Figure 6−8 for power-on reset timing. • Power-Down Sequencing: During power-down, the device reset should be asserted low (8 µs, minimum) before the VDD supply reaches 1.5 V. This helps to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. See www.spectrumdigital.com for F2812 eZdsp schematics and updates. Table 6−2. Recommended Low-Dropout Regulators SUPPLIER PART NUMBER Texas Instruments TPS767D301 eZdsp is a trademark of Spectrum Digital Incorporated. December 2004 − Revised September 2006 SGUS053B 79 Electrical Specifications NOTE: The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V. 2.5 V (see Note A) See Note C 3.3 V 3.3 V VDD_3.3V† <10 ms 1.8 V (or 1.9 V) 1.5 V 1.8 V (or 1.9 V) VDD_1.8V‡ >1 ms See Note B > 8 µs XRS See Note D XRS Power-Up Sequence Power-Down Sequence † VDD_3.3V − VDDIO , VDD3VFL , VDDAIO , VDDA1 , VDDA2 , AVDDREFBG ‡ VDD_1.8V − VDD , VDD1 NOTES: A. 1.8-V (or 1.9 V) supply should ramp after the 3.3-V supply reaches at least 2.5 V. B. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 6−8, Power-on Reset in Microcomputer Mode (XMP/MC = 0), for minimum requirements. C. Voltage supervisor or LDO reset control trips reset (XRS) first when the 3.3-V supply is off regulation. Typically, this occurs a few milliseconds before the 1.8-V (or 1.9 V) supply reaches 1.5 V. D. Keeping reset low (XRS) at least 8 µs prior to the 1.8-V (or 1.9 V) supply reaching 1.5 V keeps the flash module in complete reset before the supplies ramp down. E. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9 V) supply reaches at least 1 V, this supply should be ramped as quickly as possible (after the 3.3-V supply reaches at least 2.5 V). F. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up. Figure 6−3. F2812 Typical Power-Up and Power-Down Sequence − Option 2 80 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.8 Signal Transition Levels Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.4 V. Figure 6−4 shows output levels. 2.4 V (VOH) 80% 20% 0.4 V (VOL) Figure 6−4. Output Levels Output transition times are specified as follows: • For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower. • For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher. Figure 6−5 shows the input levels. 2.0 V (VIH) 90% 10% 0.8 V (VIL) Figure 6−5. Input Levels Input transition times are specified as follows: • For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower. • For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher. NOTE: See the individual timing diagrams for levels used for testing timing parameters. December 2004 − Revised September 2006 SGUS053B 81 Electrical Specifications 6.9 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don’t care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.10 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.11 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6−6. 3.3-V Test Load Circuit 82 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.12 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP. Table 6−3 lists the cycle times of various clocks. Table 6−3. Clock Table and Nomenclature MIN tc(OSC) , Cycle time On-chip oscillator clock Frequency tc(CI) , Cycle time XCLKIN tc(SCO) , Cycle time tc(XCO) , Cycle time tc(HCO) , Cycle time 35 MHz ns 4 150 MHz 6.67 500 ns 2 150 MHz 6.67 2000 ns 0.5 150 MHz 13.3‡ 6.67 Frequency LSPCLK 150 26.6‡ 13.3 tc(ADCCLK) , Cycle time† 75 40 tc(SPC) , Cycle time tc(CKG) , Cycle time MHz 20 MHz 20 MHz ns 50 ns Frequency tc(XTIM) , Cycle time XTIMCLK 25 50 Frequency McBSP MHz ns Frequency SPI clock MHz ns 37.5‡ Frequency ADC clock ns 75‡ tc(LCO) , Cycle time ns 250 Frequency HSPCLK UNIT 50 20 Frequency XCLKOUT MAX 6.67 Frequency SYSCLKOUT NOM 28.6 6.67 ns Frequency 150 MHz † The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT. ‡ This is the default reset value if SYSCLKOUT = 150 MHz. 6.13 Clock Requirements and Characteristics 6.13.1 Input Clock Requirements The clock provided at the XCLKIN pin generates the internal CPU clock cycle. Table 6−4. Input Clock Frequency PARAMETER fx fl Input clock frequency Limp mode clock frequency December 2004 − Revised September 2006 MIN TYP MAX Resonator 20 Crystal 20 35 XCLKIN 4 150 UNIT 35 2 SGUS053B MHz MHz 83 Electrical Specifications Table 6−5. XCLKIN Timing Requirements − PLL Bypassed or Enabled NO. C8 tc(CI) Cycle time, XCLKIN MIN MAX UNIT 6.67 250 ns Up to 30 MHz 6 30 MHz to 150 MHz 2 Up to 30 MHz 6 30 MHz to 150 MHz 2 C9 tf(CI) Fall time, XCLKIN ns C10 tr(CI) Rise time, XCLKIN C11 tw(CIL) Pulse duration, X1/XCLKIN low as a percentage of tc(CI) 40 60 % C12 tw(CIH) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) 40 60 % MIN MAX UNIT 6.67 250 ns ns Table 6−6. XCLKIN Timing Requirements − PLL Disabled NO. C8 tc(CI) Cycle time, XCLKIN C9 tf(CI) Fall time, XCLKIN C10 tr(CI) Rise time, XCLKIN C11 tw(CIL) Pulse duration, X1/XCLKIN low as a percentage of tc(CI) C12 tw(CIH) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) Up to 30 MHz 6 30 MHz to 150 MHz 2 Up to 30 MHz 6 30 MHz to 150 MHz 2 XCLKIN ≤ 120 MHz 40 60 120 < XCLKIN ≤ 150 MHz 45 55 XCLKIN ≤ 120 MHz 40 60 120 < XCLKIN ≤ 150 MHz 45 55 ns ns % % Table 6−7. Possible PLL Configuration Modes PLL MODE SYSCLKOUT PLL Disabled Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin. PLL Bypassed Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed. However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before feeding it to the CPU. PLL Enabled 84 REMARKS SGUS053B Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU. XCLKIN XCLKIN/2 (XCLKIN x n) / 2 December 2004 − Revised September 2006 Electrical Specifications 6.13.2 Output Clock Characteristics Table 6−8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)†‡ No. PARAMETER C1 MIN Cycle time, XCLKOUT tr(XCO) tw(XCOL) Rise time, XCLKOUT C5 Pulse duration, XCLKOUT low H−2 C6 tw(XCOH) Pulse duration, XCLKOUT high H−2 C7 tp PLL lock time¶ C4 MAX UNIT 6.67§ tc(XCO) tf(XCO) C3 TYP ns Fall time, XCLKOUT 2 ns 2 ns H+2 ns H+2 ns 131072tc(CI) ns † A load of 40 pF is assumed for these parameters. ‡ H = 0.5tc(XCO) § The PLL must be used for maximum frequency operation. ¶ This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon. C10 C9 C8 XCLKIN (see Note A) C6 C3 C1 C4 C5 XCLKOUT (see Note B) NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6−7 is intended to illustrate the timing parameters only and may differ based on configuration. B. XCLKOUT configured to reflect SYSCLKOUT. Figure 6−7. Clock Timing 6.14 Reset Timing Table 6−9. Reset (XRS) Timing Requirements† MIN tw(RSL1) NOM MAX 8tc(CI) Pulse duration, stable XCLKIN to XRS high Warm reset UNIT cycles 8tc(CI) tw(RSL2) Pulse duration, XRS low tw(WDRS) Pulse duration, reset pulse generated by watchdog td(EX) Delay time, address/data valid after XRS high tOSCST‡ Oscillator start-up time tsu(XPLLDIS) Setup time for XPLLDIS pin 16tc(CI) cycles th(XPLLDIS) Hold time for XPLLDIS pin 16tc(CI) cycles th(XMP/MC) Hold time for XMP/MC pin 16tc(CI) 2520tc(CI)§ cycles WD-initiated reset cycles 512tc(CI) 1 512tc(CI) cycles 32tc(CI) cycles 10 ms th(boot-mode) cycles Hold time for boot-mode pins † If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V. ‡ Dependent on crystal/resonator and board design. § The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the TMS320x281x Boot ROM Reference Guide (literature number SPRU095) and TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078) for further information. December 2004 − Revised September 2006 SGUS053B 85 Electrical Specifications VDDIO,VDD3VFL VDDAn†,VDDAIO (3.3 V) (See Note B) VDD, VDD1 (1.8 V (or 1.9 V)) 2.5 V 0.3 V XCLKIN X1 XCLKIN/8 (See Note C) XCLKOUT User-Code Dependent tOSCST tw(RSL1) XRS Address/Data Valid. Internal Boot-ROM Code Execution Phase Address/Data/ Control td(EX) tsu(XPLLDIS) XPLLDIS Sampling XF/XPLLDIS XMP/MC See NOTE User-Code Dependent th(XPLLDIS) (Don’t Care) GPIOF14 th(XMP/MC) th(boot-mode) (see Note D) Boot-Mode Pins User-Code Execution Phase (Don’t Care) User-Code Dependent GPIO Pins as Input Peripheral/GPIO Function Based on Boot Code Boot-ROM Execution Starts I/O Pins GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V and 3.3-V supply reaches 2.5 V. B. VDDAn − VDDA1/VDDA2 and AVDDREFBG C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase. D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled. Figure 6−8. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A) 86 SGUS053B December 2004 − Revised September 2006 Electrical Specifications VDDIO, VDD3VFL VDDAn, VDDAIO (3.3 V) VDD, VDD1 (1.8 V (or 1.9 V)) 2.5 V 0.3 V XCLKIN X1 tOSCST XCLKOUT XCLKIN/8 (See Note A) User-Code Dependent tw(RSL) XRS td(EX) Address/Data/ Control (Don’t Care) XF/XPLLDIS (Don’t Care) XPLLDIS Sampling Address/Data/Control Valid Execution Begins From External Boot Address 0x3FFFC0 th(XPLLDIS) GPIOF14/XF (User-Code Dependent) tsu(XPLLDIS) XMP/MC th(XMP/MC) I/O Pins (Don’t Care) User-Code Dependent See Note B Input Configuration (State Depends on Internal PU/PD) NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase. B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V and 3.3-V supply reaches 2.5 V.. Figure 6−9. Power-on Reset in Microprocessor Mode (XMP/MC = 1) December 2004 − Revised September 2006 SGUS053B 87 Electrical Specifications XCLKIN X1 XCLKIN/8 XCLKOUT (XCLKIN * 5) User-Code Dependent tw(RSL2) XRS td(EX) Address/Data/ Control User-Code Execution (Don’t Care) tsu(XPLLDIS) XF/XPLLDIS XMP/MC GPIOF14/XF (Don’t Care) Peripheral/GPIO Function th(XPLLDIS) (Don’t Care) XPLLDIS Sampling th(XMP/MC) Boot-ROM Execution Starts Boot-Mode Pins User-Code Execution Phase GPIO Pins as Input GPIOF14 User-Code Dependent (Don’t Care) th(boot-mode)† Peripheral/GPIO Function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent † After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled. Figure 6−10. Warm Reset in Microcomputer Mode 88 SGUS053B December 2004 − Revised September 2006 Electrical Specifications X1/XCLKIN Write to PLLCR SYSCLKOUT XCLKIN x 2 XCLKIN/2 XCLKIN x 4 (Current CPU Frequency) (CPU Frequency While PLL is Stabilizing With the Desired Frequency. This Period (PLL Lock-up Time, tp) is 131 072 XCLKIN Cycles Long.) (Changed CPU Frequency) Figure 6−11. Effect of Writing Into PLLCR Register December 2004 − Revised September 2006 SGUS053B 89 Electrical Specifications 6.15 Low-Power Mode Wakeup Timing Table 6−10 is also the IDLE Mode Wake-Up Timing Requirements table. Table 6−10. IDLE Mode Switching Characteristics PARAMETER tw(WAKE-INT) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualifier 2 x tc(SCO) 1 x tc(SCO) + IQT† Cycles 8 x tc(SCO) Cycles 8 x tc(SCO) + IQT† Cycles 1050 x tc(SCO) Cycles 1050 x tc(SCO) +IQT† Cycles 8 x tc(SCO) 8 x tc(SCO) + IQT† Cycles With input qualifier TYP MAX UNIT Cycles Delay time, external wake signal to program execution resume‡ td(WAKE-IDLE) − Wake-up from Flash − Flash module in active state Without input qualifier − Wake-up from Flash − Flash module in active state With input qualifier − Wake-up from Flash − Flash module in sleep state Without input qualifier − Wake-up from Flash − Flash module in sleep state With input qualifier − Wake-up from SARAM Without input qualifier − Wake-up from SARAM With input qualifier Cycles † Input Qualification Time (IQT) = [5 x QUALPRD x 2] x tc(SCO) ‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up) signal involves additional latency. td(WAKE−IDLE) A0−A15 XCLKOUT† tw(WAKE−INT) WAKE INT‡ † XCLKOUT = SYSCLKOUT ‡ WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. Figure 6−12. IDLE Entry and Exit Timing Table 6−11 is also the STANDBY Mode Wake-Up Timing Requirements table. 90 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Table 6−11. STANDBY Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN Delay time, IDLE instruction td(IDLE-XCOH) executed to XCLKOUT high TYP 32 x tc(SCO) Without input qualifier Pulse duration, external tw(WAKE-INT) wake-up signal With input qualifier MAX 12 x tc(CI) UNIT Cycles 12 x tc(CI) (2 + QUALSTDBY)† x tc(CI) Cycles 12 x tc(CI) Cycles 12 x tc(CI) + tw(WAKE-INT) Cycles 1125 x tc(SCO) Cycles 1125 x tc(SCO) + tw(WAKE-INT) Cycles Cycles Delay time, external wake signal to program execution resume‡ td(WAKE-STBY) − Wake-up from Flash − Flash module in active state Without input qualifier − Wake-up from Flash − Flash module in active state With input qualifier − Wake-up from Flash − Flash module in sleep state Without input qualifier − Wake-up from Flash − Flash module in sleep state With input qualifier − Wake-up from SARAM Without input qualifier − Wake-up from SARAM With input qualifier 12 x tc(CI) 12 x tc(CI) + tw(WAKE-INT) Cycles Cycles † QUALSTDBY is a 6-bit field in the LPMCR0 register. ‡ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up) signal involves additional latency. A C E B Device Status STANDBY D F STANDBY Normal Execution Flushing Pipeline Wake−up Signal tw(WAKE-INT) td(WAKE-STBY) X1/XCLKIN td(IDLE−XCOH) XCLKOUT† 32 SYSCLKOUT Cycles NOTES: A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. The device is now in STANDBY mode. D. The external wake-up signal is driven active (negative edge triggered shown as an example). E. After a latency period, the STANDBY mode is exited. F. Normal operation resumes. The device responds to the interrupt (if enabled). Figure 6−13. STANDBY Entry and Exit Timing December 2004 − Revised September 2006 SGUS053B 91 Electrical Specifications Table 6−12. HALT Mode Switching Characteristics PARAMETER MIN TYP 32 x tc(SCO) MAX UNIT td(IDLE-XCOH) Delay time, IDLE instruction executed to XCLKOUT high tw(WAKE-XNMI) Pulse duration, XNMI wakeup signal 2 x tc(CI) 45 xtc(SCO) Cycles Cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal 8 x tc(CI) Cycles tp PLL lock-up time 131 072 x tc(CI) Cycles Delay time, PLL lock to program execution resume − Wake-up from flash − Flash module in sleep state td(wake) 1125 x tc(SCO) Cycles 35 x tc(SCO) Cycles − Wake-up from SARAM A C E B Device Status D HALT Flushing Pipeline G F HALT PLL Lock−up Time Wake−up Latency Normal Execution XNMI tw(WAKE−XNMI) tp td(INT) X1/XCLKIN td(IDLE−XCOH) Oscillator Start-up Time XCLKOUT† 32 SYSCLKOUT Cycles † XCLKOUT = SYSCLKOUT NOTES: A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and consumes absolute minimum power. D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not activated. E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles. F. When CLKIN to the core is enabled, the device responds to the interrupt (if enabled), after a latency. The HALT mode is now exited. G. Normal operation resumes. Figure 6−14. HALT Wakeup Using XNMI 92 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.16 Event Manager Interface 6.16.1 PWM Timing PWM refers to all PWM outputs on EVA and EVB. Table 6−13. PWM Switching Characteristics†‡ PARAMETER tw(PWM)§ TEST CONDITIONS MIN MAX 25 Pulse duration, PWMx output high/low td(PWM)XCO XCLKOUT = SYSCLKOUT/4 Delay time, XCLKOUT high to PWMx output switching † See the GPIO output timing for fall/rise times for PWM pins. ‡ PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz). § PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period. UNIT ns 10 ns Table 6−14. Timer and Capture Unit Timing Requirements¶# MIN Without input qualifier MAX 2 x tc(SCO) UNIT tw(TDIR) Pulse duration, TDIRx low/high tw(CAP) Pulse duration, CAPx input low/high tw(TCLKINL) Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time 40 60 % Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time 40 60 % tw(TCLKINH) With input qualifier 1 x tc(SCO) + IQT|| Without input qualifier 2 x tc(SCO) 1 x tc(SCO) + IQT|| With input qualifier cycles cycles tc(TCLKIN) 4 x tc(HCO) ns Cycle time, TCLKINx ¶ The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is 2n SYSCLKOUT cycles, where n is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples are taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition. # Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz] || Input Qualification Time (IQT) = [5 x QUALPRD x 2] x tc(SCO) XCLKOUT† td(PWM)XCO tw(PWM) PWMx † XCLKOUT = SYSCLKOUT Figure 6−15. PWM Output Timing XCLKOUT† tw(TDIR) TDIRx † XCLKOUT = SYSCLKOUT Figure 6−16. TDIRx Timing December 2004 − Revised September 2006 SGUS053B 93 Electrical Specifications Table 6−15. External ADC Start-of-Conversion − EVA − Switching Characteristics† PARAMETER td(XCOH-EVASOCL) MIN Delay time, XCLKOUT high to EVASOC low tw(EVASOCL) Pulse duration, EVASOC low † XCLKOUT = SYSCLKOUT MAX UNIT 1 x tc(SCO) cycle 32 x tc(HCO) ns XCLKOUT td(XCOH-EVASOCL) tw(EVASOCL) EVASOC Figure 6−17. EVASOC Timing Table 6−16. External ADC Start-of-Conversion − EVB − Switching Characteristics† PARAMETER td(XCOH-EVBSOCL) MIN Delay time, XCLKOUT high to EVBSOC low tw(EVBSOCL) Pulse duration, EVBSOC low † XCLKOUT = SYSCLKOUT 32 x tc(HCO) MAX UNIT 1 x tc(SCO) cycle ns XCLKOUT td(XCOH-EVBSOCL) tw(EVBSOCL) EVBSOC Figure 6−18. EVBSOC Timing 94 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.16.2 Interrupt Timing Table 6−17. Interrupt Switching Characteristics PARAMETER td(PDP-PWM)HZ td(TRIP-PWM)HZ MIN MAX Without input Delay time, PDPINTx low to PWM qualifier high-impedance state With input qualifier Delay time, CxTRIP/TxCTRIP signals low to PWM high-impedance state 12 ns 1 x tc(SCO) + IQT + 12† Without input qualifier 3 x tc(SCO) ns [2 x tc(SCO)] + IQT† With input qualifier td(INT) Delay time, INT low/high to interrupt-vector fetch † Input Qualification Time (IQT) = [5 x QUALPRD x 2] x tc(SCO) UNIT tqual + 12tc(XCO) ns Table 6−18. Interrupt Timing Requirements MIN with no qualifier tw(INT) Pulse duration, INT input low/high tw(PDP) Pulse duration, PDPINTx input low tw(CxTRIP) Pulse duration, CxTRIP input low tw(TxCTRIP) Pulse duration, TxCTRIP input low with qualifier with no qualifier with qualifier with no qualifier with qualifier with no qualifier with qualifier MAX 2 x tc(SCO) 1 x tc(SCO) + IQT† 2 x tc(SCO) 1 x tc(SCO) + IQT† 2 x tc(SCO) 1 x tc(SCO) + IQT† 2 x tc(SCO) 1 x tc(SCO) + IQT† UNIT cycles cycles cycles cycles † Input Qualification Time (IQT) = [5 x QUALPRD x 2] x tc(SCO) December 2004 − Revised September 2006 SGUS053B 95 Electrical Specifications XCLKOUT† tw(PDP), tw(CxTRIP), tw(TxCTRIP) TxCTRIP, CxTRIP, PDPINTx‡ td(PDP-PWM)HZ , td(TRIP-PWM)HZ PWM§ tw(INT) XNMI, XINT1, XINT2 td(INT) Interrupt Vector A0−A15 † XCLKOUT = SYSCLKOUT ‡ TxCTRIP − T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP CxTRIP − C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP PDPINTx − PDPINTA or PDPINTB § PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit. Figure 6−19. External Interrupt Timing 6.17 General-Purpose Input/Output (GPIO) − Output Timing Table 6−19. General-Purpose Output Switching Characteristics PARAMETER MIN MAX UNIT cycle td(XCOH-GPO) Delay time, XCLKOUT high to GPIO low/high tr(GPO) Rise time, GPIO switching low to high All GPIOs 1 x tc(SCO) All GPIOs 10 ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 10 ns fGPO Toggling frequency, GPO pins 20 MHz XCLKOUT td(XCOH-GPO) GPIO tr(GPO) tf(GPO) Figure 6−20. General-Purpose Output Timing 96 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.18 General-Purpose Input/Output (GPIO) − Input Timing See Note A GPIO Signal 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 QUALPRD Sampling Window SYSCLKOUT QUALPRD = 1 (2 x SYSCLKOUT cycles) x 5 Output From Qualifier NOTES: A. This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value n, the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin is sampled). Six consecutive samples must be of the same value for a given input to be recognized. B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur. Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6−21. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 Table 6−20. General-Purpose Input Timing Requirements MIN With no qualifier tw(GPI) Pulse duration, GPIO low/high All GPIOs With qualifier MAX 2 x tc(SCO) 1 x tc(SCO) + IQT† UNIT cycles † Input Qualification Time (IQT) = [5 x QUALPRD x 2] x tc(SCO) XCLKOUT GPIOxn tw(GPI) Figure 6−22. General-Purpose Input Timing NOTE: The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC pins as well. December 2004 − Revised September 2006 SGUS053B 97 98 SGUS053B 0.5tc(SPC)M −10 0.5tc(SPC)M −10 0.5tc(SPC)M −10 0 Pulse duration, SPICLK low (clock polarity = 1) Pulse duration, SPICLK low (clock polarity = 0) Pulse duration, SPICLK high (clock polarity = 1) Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) Setup time, SPISOMI before SPICLK low (clock polarity = 0) Setup time, SPISOMI before SPICLK high (clock polarity = 1) Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) tw(SPCH)M tw(SPCL)M tw(SPCL)M tw(SPCH)M td(SPCH-SIMO)M td(SPCL-SIMO)M tv(SPCL-SIMO)M tv(SPCH-SIMO)M tsu(SOMI-SPCL)M tsu(SOMI-SPCH)M tv(SPCL-SOMI)M tv(SPCH-SOMI)M 0.25tc(SPC)M −10 0.25tc(SPC)M −10 0 0.5tc(SPC)M −10 − 10 − 10 0.5tc(SPC)M −10 0.5tc(SPC)M −10 Pulse duration, SPICLK high (clock polarity = 0) 4tc(LCO) Cycle time, SPICLK tc(SPC)M MIN 0.5tc(SPC)M −0.5tc(LCO)−10 0.5tc(SPC)M −0.5tc(LCO) −10 0 0 0.5tc(SPC)M + 0.5tc(LCO) −10 0.5tc(SPC)M + 0.5tc(LCO) −10 − 10 − 10 0.5tc(SPC)M + 0.5tc(LCO)−10 0.5tc(SPC)M + 0.5tc(LCO)−10 0.5tc(SPC)M −0.5tc(LCO) −10 0.5tc(SPC)M −0.5tc(LCO) −10 5tc(LCO) MIN 127tc(LCO) MAX 10 10 0.5tc(SPC)M + 0.5tc(LCO) 0.5tc(SPC)M + 0.5tc(LCO) 0.5tc(SPC)M − 0.5tc(LCO) 0.5tc(SPC)M −0.5tc(LCO) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 LSPCLK ‡ tc(SPC) = SPI clock cycle time = LSPCLK or 4 (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz). 10 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 128tc(LCO) MAX SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 Table 6−21. SPI Master Mode External Timing (Clock Phase = 0)†‡ † The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. 9§ 8§ 5§ 4§ 3§ 2§ 1 NO. 6.19 SPI Master Mode Timing ns ns ns ns ns ns ns UNIT Electrical Specifications December 2004 − Revised September 2006 Electrical Specifications 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid SPISTE† † In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−23. SPI Master Mode External Timing (Clock Phase = 0) December 2004 − Revised September 2006 SGUS053B 99 100 SGUS053B Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) Setup time, SPISOMI before SPICLK high (clock polarity = 0) tv(SPCH-SIMO)M tv(SPCL-SIMO)M tsu(SOMI-SPCH)M tv(SPCL-SOMI)M 0.5tc(SPC)M −10 Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) tsu(SIMO-SPCL)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M −10 Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M −10 Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) tsu(SIMO-SPCH)M tv(SPCH-SOMI)M 0.5tc(SPC)M −10 Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)M tsu(SOMI-SPCL)M 0.5tc(SPC)M −10 Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.5tc(SPC)M −10 Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)M 0.25tc(SPC)M −10 0.25tc(SPC)M −10 0 0 0.5tc(SPC)M −10 0.5tc(SPC)M −10 Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)M 4tc(LCO) Cycle time, SPICLK tc(SPC)M MIN 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(SPC)M 128tc(LCO) MAX SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 5tc(LCO) 0.5tc(SPC)M −10 0.5tc(SPC)M −10 0 0 0.5tc(SPC)M −10 0.5tc(SPC)M −10 0.5tc(SPC)M −10 0.5tc(SPC)M − 10 0.5tc(SPC)M + 0.5tc(LCO) −10 0.5tc(SPC)M + 0.5tc(LCO) −10 0.5tc(SPC)M −0.5tc (LCO)−10 0.5tc(SPC)M −0.5tc (LCO)−10 MIN 127tc(LCO) MAX 0.5tc(SPC)M + 0.5tc(LCO) 0.5tc(SPC)M + 0.5tc(LCO) 0.5tc(SPC)M − 0.5tc(LCO) 0.5tc(SPC)M − 0.5tc(LCO) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 LSPCLK ‡ tc(SPC) = SPI clock cycle time = LSPCLK or 4 (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz). † The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. 11§ 10§ 7§ 6§ 3§ 2§ 1 NO. Table 6−22. SPI Master Mode External Timing (Clock Phase = 1)†‡ ns ns ns ns ns ns ns UNIT Electrical Specifications December 2004 − Revised September 2006 Electrical Specifications 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Data Valid Master Out Data Is Valid SPISIMO 10 11 Master In Data Must Be Valid SPISOMI SPISTE† † In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE goes inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−24. SPI Master External Timing (Clock Phase = 1) December 2004 − Revised September 2006 SGUS053B 101 Electrical Specifications 6.20 SPI Slave Mode Timing Table 6−23. SPI Slave Mode External Timing (Clock Phase = 0)†‡ NO. 12 13§ 14§ 15§ tc(SPC)S tw(SPCH)S Cycle time, SPICLK tw(SPCL)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 0.375tc(SPC)S −10 td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375tc(SPC)S −10 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S 16§ 19§ MIN 4tc(LCO)‡ tsu(SIMO-SPCL)S tsu(SIMO-SPCH)S Pulse duration, SPICLK high (clock polarity = 0) Pulse duration, SPICLK low (clock polarity = 0) UNIT ns 0.5tc(SPC)S −10 0.5tc(SPC)S −10 0.5tc(SPC)S 0.5tc(SPC)S ns 0.5tc(SPC)S −10 0.5tc(SPC)S −10 0.5tc(SPC)S 0.5tc(SPC)S ns ns ns Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0 Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S 20§ MAX ns ns † The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. LSPCLK ‡ tc(SPC) = SPI clock cycle time = LSPCLK or 4 (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 102 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI Data Is Valid 19 20 SPISIMO Data Must Be Valid SPISIMO SPISTE† † In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−25. SPI Slave Mode External Timing (Clock Phase = 0) December 2004 − Revised September 2006 SGUS053B 103 Electrical Specifications Table 6−24. SPI Slave Mode External Timing (Clock Phase = 1)†‡ NO. 12 13§ 14§ 17§ MIN tc(SPC)S tw(SPCH)S Cycle time, SPICLK tw(SPCL)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) tw(SPCH)S tsu(SOMI-SPCH)S Pulse duration, SPICLK high (clock polarity = 1) tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) tv(SPCH-SOMI)S Valid time, SPIS OMI data valid after SPICLK high (clock polarity = 0) 0.75tc(SPC)S tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.75tc(SPC)S 18§ 21§ MAX tsu(SIMO-SPCH)S tsu(SIMO-SPCL)S Pulse duration, SPICLK high (clock polarity = 0) Pulse duration, SPICLK low (clock polarity = 0) Setup time, SPISOMI before SPICLK high (clock polarity = 0) 8tc(LCO) 0.5tc(SPC)S −10 0.5tc(SPC)S −10 0.5tc(SPC)S 0.5tc(SPC)S ns 0.5tc(SPC)S −10 0.5tc(SPC)S −10 0.5tc(SPC)S 0.5tc(SPC)S ns ns 0.125tc(SPC)S 0.125tc(SPC)S ns ns Setup time, SPISIMO before SPICLK high (clock polarity = 0) 0 Setup time, SPISIMO before SPICLK low (clock polarity = 1) 0 ns tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S 22§ UNIT ns † The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set. LSPCLK ‡ tc(SPC) = SPI clock cycle time = LSPCLK or 4 (SPIBRR ) 1) tc(LCO) = LSPCLK cycle time § The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 18 SPISOMI Data Valid SPISOMI Data Is Valid 21 22 SPISIMO SPISIMO Data Must Be Valid SPISTE† † In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−26. SPI Slave Mode External Timing (Clock Phase = 1) 104 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.21 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6−25 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles. Table 6−25. Relationship Between Parameters Configured in XTIMING and Duration of Pulse†‡ DURATION (ns) DESCRIPTION X2TIMING = 0 X2TIMING = 1 XRDLEAD x tc(XTIM) (XRDACTIVE + WS + 1) x tc(XTIM) (XRDLEAD x 2) x tc(XTIM) (XRDACTIVE x 2 + WS + 1) x tc(XTIM) LR Lead period, read access AR Active period, read access TR Trail period, read access XRDTRAIL x tc(XTIM) (XRDTRAIL x 2) x tc(XTIM) LW Lead period, write access AW Active period, write access XWRLEAD x tc(XTIM) (XWRACTIVE + WS + 1) x tc(XTIM) (XWRLEAD x 2) x tc(XTIM) (XWRACTIVE x 2 + WS + 1) x tc(XTIM) TW Trail period, write access XWRTRAIL x tc(XTIM) (XWRTRAIL x 2) x tc(XTIM) † tc(XTIM) − Cycle time, XTIMCLK ‡ WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0), then WS = 0. Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal device hardware is included to detect illegal settings. • If the XREADY signal is ignored (USEREADY = 0), then: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 1. Lead: These requirements result in the following XTIMING register configuration restrictions§: XRDLEAD XRDACTIVE ≥1 XRDTRAIL ≥0 XWRLEAD ≥0 XWRACTIVE ≥1 ≥0 XWRTRAIL X2TIMING ≥0 0, 1 § No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when not sampling XREADY§: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Valid 1 0 0 1 0 0 0, 1 § No hardware to detect illegal XTIMING configurations December 2004 − Revised September 2006 SGUS053B 105 Electrical Specifications • If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 1. Lead: AR ≥ 2 x tc(XTIM) AW ≥ 2 x tc(XTIM) NOTE: Restriction does not include external hardware wait states 2. Active: These requirements result in the following XTIMING register configuration restrictions†: XRDLEAD XRDACTIVE ≥1 XRDTRAIL ≥1 XWRLEAD ≥0 XWRACTIVE ≥1 XWRTRAIL ≥1 ≥0 X2TIMING 0, 1 † No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Synchronous XREADY†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Invalid 1 0 0 1 0 0 0, 1 Valid 1 1 0 1 1 0 0, 1 † No hardware to detect illegal XTIMING configurations • If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 1. Lead: AR ≥ 2 x tc(XTIM) AW ≥ 2 x tc(XTIM) NOTE: Restriction does not include external hardware wait states 2. Active: LR + AR ≥ 4 x tc(XTIM) LW + AW ≥ 4 x tc(XTIM) NOTE: Restriction does not include external hardware wait states 3. Lead + Active: These requirements result in the following XTIMING register configuration restrictions†: XRDLEAD XRDACTIVE ≥1 XRDTRAIL ≥2 XWRLEAD XWRACTIVE ≥1 0 XWRTRAIL ≥2 0 X2TIMING 0, 1 † No hardware to detect illegal XTIMING configurations or† XRDLEAD XRDACTIVE ≥2 XRDTRAIL ≥1 XWRLEAD XWRACTIVE ≥2 0 XWRTRAIL ≥1 0 X2TIMING 0, 1 † No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Asynchronous XREADY†: XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Invalid 1 0 0 1 0 0 0, 1 Invalid 1 1 0 1 1 0 0 Valid 1 1 0 1 1 0 1 Valid 1 2 0 1 2 0 0, 1 0 2 1 0 0, 1 Valid 2 1 † No hardware to detect illegal XTIMING configurations 106 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6−26. Table 6−26. XINTF Clock Configurations Mode SYSCLKOUT XTIMCLK XCLKOUT 1 Example: 150 MHz SYSCLKOUT 150 MHz SYSCLKOUT 150 MHz 2 Example: 150 MHz SYSCLKOUT 150 MHz 1/2 SYSCLKOUT 75 MHz 3 Example: 150 MHz 1/2 SYSCLKOUT 75 MHz 1/2 SYSCLKOUT 75 MHz 4 Example: 150 MHz 1/2 SYSCLKOUT 75 MHz 1/4 SYSCLKOUT 37.5 MHz The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6−27. XTIMING0 XTIMING1 XTIMING2 LEAD/ACTIVE/TRAIL XTIMING6 XTIMING7 XBANK C28x CPU SYSCLKOUT /2 1† XTIMCLK /2 1† 0 XCLKOUT 1 0 0 0 XINTCNF2 (XTIMCLK) XINTCNF2 (CLKMODE) XINTCNF2 (CLKOFF) † Default Value after reset Figure 6−27. Relationship Between XTIMCLK and SYSCLKOUT 6.22 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency of XTIMCLK. For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes changes state with respect to the rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes change state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the notation XCOH is used. December 2004 − Revised September 2006 SGUS053B 107 Electrical Specifications For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change is aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment is with respect to the rising edge of XCLKOUT. If this number is odd, then the signal changes with respect to the falling edge of XCLKOUT. Examples include the following: • Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is because all XINTF accesses begin with respect to the rising edge of XCLKOUT. Examples: • XR/W active low XRDL XRD active low XWEL XWE active low XRDH XRD inactive high XWEH XWE inactive high Strobes that change at the end of the access aligns to the rising edge of XCLKOUT if the total number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment is with respect to the falling edge of XCLKOUT. Examples: 108 XRNWL Strobes that change at the beginning of the trail period aligns to the rising edge of XCLKOUT if the total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment is with respect to the falling edge of XCLKOUT. Examples: • Zone chip-select active low Strobes that change at the beginning of the active period aligns to the rising edge of XCLKOUT if the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then the alignment is with respect to the falling edge of XCLKOUT. Examples: • XZCSL SGUS053B XZCSH Zone chip-select inactive high XRNWH XR/W inactive high December 2004 − Revised September 2006 Electrical Specifications 6.23 External Interface Read Timing Table 6−27. External Memory Interface Read Switching Characteristics PARAMETER MIN td(XCOH-XZCSL) td(XCOHL-XZCSH) Delay time, XCLKOUT high to zone chip-select active low td(XCOH-XA) td(XCOHL-XRDL) Delay time, XCLKOUT high to address valid Delay time, XCLKOUT high/low to XRD active low td(XCOHL-XRDH th(XA)XZCSH Delay time, XCLKOUT high/low to XRD inactive high Delay time, XCLKOUT high/low to zone chip-select inactive high MAX −2 −2 † Hold time, address valid after zone chip-select inactive high UNIT 1 ns 3 ns 2 ns 1 ns 1 ns ns † th(XA)XRD Hold time, address valid after XRD inactive high † During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. ns Table 6−28. External Memory Interface Read Timing Requirements MIN ta(A) ta(XRD) MAX UNIT (LR + AR) − 14‡ AR − 12‡ Access time, read data from address valid Access time, read data valid from XRD active low tsu(XD)XRD Setup time, read data valid before XRD strobe inactive high th(XD)XRD Hold time, read data valid after XRD inactive high ‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−25. ns 12 ns 0 ns Trail Active Lead ns XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK td(XCOH-XZCSL) XZCS0AND1, XZCS2, XZCS6AND7 td(XCOHL-XZCSH) td(XCOH-XA) XA[0:18] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD tsu(XD)XRD XWE XR/W ta(A) th(XD)XRD ta(XRD) DIN XD[0:15] XREADY NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. For USEREADY = 0, the external XREADY input signal is ignored. D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles. Figure 6−28. Example Read Access XTIMING register parameters used for this example: XRDLEAD ≥1 XRDACTIVE XRDTRAIL ≥0 ≥0 USEREADY 0 X2TIMING 0 XWRLEAD N/A† XWRACTIVE N/A† XWRTRAIL N/A† READYMODE N/A† † N/A = “Don’t care” for this example December 2004 − Revised September 2006 SGUS053B 109 Electrical Specifications 6.24 External Interface Write Timing Table 6−29. External Memory Interface Write Switching Characteristics PARAMETER MIN td(XCOH-XZCSL) td(XCOHL-XZCSH) Delay time, XCLKOUT high to zone chip-select active low td(XCOH-XA) td(XCOHL-XWEL) MAX UNIT 1 ns 3 ns Delay time, XCLKOUT high to address valid 2 ns Delay time, XCLKOUT high/low to XWE low 2 ns td(XCOHL-XWEH) td(XCOH-XRNWL) Delay time, XCLKOUT high/low to XWE high 2 ns 1 ns td(XCOHL-XRNWH) ten(XD)XWEL Delay time, XCLKOUT high/low to XR/W high 1 ns td(XWEL-XD) Delay time, data valid after XWE active low th(XA)XZCSH th(XD)XWE Hold time, address valid after zone chip-select inactive high Delay time, XCLKOUT high or low to zone chip-select inactive high −2 Delay time, XCLKOUT high to XR/W low −2 Enable time, data bus driven from XWE low 0 ns 4 Hold time, write data valid after XWE inactive high ns † ns TW−2‡ ns tdis(XD)XRNW Data bus disabled after XR/W inactive high 4 † During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. ‡ TW = Trail period, write access. See Table 6−25. ns Active Lead Trail XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK td(XCOHL-XZCSH) td(XCOH-XZCSL) XZCS0AND1, XZCS2, XZCS6AND7 td(XCOH-XA) XA[0:18] XRD td(XCOHL-XWEH) td(XCOHL-XWEL) XWE td(XCOHL-XRNWH) td(XCOH-XRNWL) XR/W tdis(XD)XRNW th(XD)XWEH td(XWEL-XD) ten(XD)XWEL DOUT XD[0:15] XREADY NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. For USEREADY = 0, the external XREADY input signal is ignored. D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles. Figure 6−29. Example Write Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE N/A† XRDTRAIL N/A† N/A† USEREADY 0 X2TIMING 0 XWRLEAD ≥1 XWRACTIVE ≥0 XWRTRAIL ≥0 READYMODE N/A† † N/A = “Don’t care” for this example 110 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.25 External Interface Ready-on-Read Timing With One External Wait State Table 6−30. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) PARAMETER td(XCOH-XZCSL) td(XCOHL-XZCSH) Delay time, XCLKOUT high to zone chip-select active low td(XCOH-XA) td(XCOHL-XRDL) Delay time, XCLKOUT high to address valid td(XCOHL-XRDH th(XA)XZCSH Delay time, XCLKOUT high/low to XRD inactive high MIN Delay time, XCLKOUT high/low to zone chip-select inactive high −2 Delay time, XCLKOUT high/low to XRD active low −2 † Hold time, address valid after zone chip-select inactive high MAX UNIT 1 ns 3 ns 2 ns 1 ns 1 ns ns † th(XA)XRD Hold time, address valid after XRD inactive high † During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. ns Table 6−31. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) MIN ta(A) ta(XRD) (LR + AR) − 14‡ AR − 12‡ Access time, read data from address valid Access time, read data valid from XRD active low tsu(XD)XRD Setup time, read data valid before XRD strobe inactive high th(XD)XRD Hold time, read data valid after XRD inactive high ‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−25. MAX UNIT ns ns 12 ns 0 ns Table 6−32. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)§ MIN tsu(XRDYsynchL)XCOHL th(XRDYsynchL) Setup time, XREADY (Synch) low before XCLKOUT high/low 15 Hold time, XREADY (Synch) low 12 te(XRDYsynchH) tsu(XRDYsynchH)XCOHL Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge Setup time, XREADY (Synch) high before XCLKOUT high/low MAX UNIT ns ns 3 15 ns ns th(XRDYsynchH)XZCSH Hold time, XREADY (Synch) held high after zone chip select high 0 ns § The first XREADY (Synch) sample occurs with respect to E in Figure 6−30: E = (XRDLEAD + XRDACTIVE) tc(XTIM) When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is sampled again each tc(XTIM) until it is found to be high. For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. Table 6−33. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)¶ MIN tsu(XRDYAsynchL)XCOHL th(XRDYAsynchL) Setup time, XREADY (Asynch) low before XCLKOUT high/low te(XRDYAsynchH) tsu(XRDYAsynchH)XCOHL Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge Hold time, XREADY (Asynch) low Setup time, XREADY (Asynch) high before XCLKOUT high/low MAX 11 UNIT ns 8 ns 3 11 ns ns th(XRDYasynchH)XZCSH Hold time, XREADY (Asynch) held high after zone chip select high 0 ns ¶ The first XREADY (Asynch) sample occurs with respect to E in Figure 6−31: E = (XRDLEAD + XRDACTIVE −2) tc(XTIM) When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it wis sampled again each tc(XTIM) until it is found to be high. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. December 2004 − Revised September 2006 SGUS053B 111 Electrical Specifications WS (Synch) See Notes A and B Active Lead Trail See Note C XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK td(XCOHL-XZCSH) td(XCOH-XZCSL) XZCS0AND1, XZCS2, XZCS6AND7 td(XCOH-XA) XA[0:18] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD tsu(XD)XRD XWE ta(XRD) XR/W ta(A) th(XD)XRD XD[0:15] DIN tsu(XRDYsynchL)XCOHL te(XRDYsynchH) th(XRDYsynchL) th(XRDYsynchH)XZCSH tsu(XRDHsynchH)XCOHL XREADY(Synch) See Note D See Note E Legend: = Don’t care. Signal can be high or low during this time. NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access (D) can be calculated as: D = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL E. Reference for the first sample is with respect to this point E = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number: n = 1, 2, 3, and so forth. Figure 6−30. Example Read With Synchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE ≥1 XRDTRAIL 3 ≥1 USEREADY 1 X2TIMING 0 XWRLEAD N/A† XWRACTIVE N/A† XWRTRAIL N/A† READYMODE 0 = XREADY (Synch) † N/A = “Don’t care” for this example 112 SGUS053B December 2004 − Revised September 2006 Electrical Specifications WS (Asynch) Active " # Lead See Note C Trail XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 td(XCOH-XZCSL) td(XCOHL-XZCSH) td(XCOH-XA) XA[0:18] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD tsu(XD)XRD XWE ta(XRD) XR/W ta(A) th(XD)XRD DIN XD[0:15] tsu(XRDYasynchL)XCOHL te(XRDYasynchH) th(XRDYasynchH)XZCSH th(XRDYasynchL) tsu(XRDYasynchH)XCOHL XREADY(Asynch) See Note D See Note E Legend: = Don’t care. Signal can be high or low during this time. NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. During inactive cycles, the XINTF address bus always hold sthe last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. E. Reference for the first sample is with respect to this point: E = (XRDLEAD + XRDACTIVE −2) tc(XTIM) Figure 6−31. Example Read With Asynchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD ≥1 XRDACTIVE XRDTRAIL 3 ≥1 USEREADY 1 X2TIMING 0 XWRLEAD N/A† XWRACTIVE N/A† XWRTRAIL N/A† READYMODE 1 = XREADY (Asynch) † N/A = “Don’t care” for this example December 2004 − Revised September 2006 SGUS053B 113 Electrical Specifications 6.26 External Interface Ready-on-Write Timing With One External Wait State Table 6−34. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) PARAMETER td(XCOH-XZCSL) td(XCOHL-XZCSH) Delay time, XCLKOUT high to zone chip-select active low td(XCOH-XA) td(XCOHL-XWEL) Delay time, XCLKOUT high to address valid MIN MAX UNIT 1 ns 3 ns 2 ns Delay time, XCLKOUT high/low to XWE low 2 ns td(XCOHL-XWEH) td(XCOH-XRNWL) Delay time, XCLKOUT high/low to XWE high 2 ns Delay time, XCLKOUT high to XR/W low 1 ns td(XCOHL-XRNWH) ten(XD)XWEL Delay time, XCLKOUT high/low to XR/W high 1 ns td(XWEL-XD) Delay time, data valid after XWE active low th(XA)XZCSH th(XD)XWE Delay time, XCLKOUT high or low to zone chip-select inactive high −2 −2 Enable time, data bus driven from XWE low 0 ns 4 Hold time, address valid after zone chip-select inactive high Hold time, write data valid after XWE inactive high ns † ns TW−2‡ ns tdis(XD)XRNW Data bus disabled after XR/W inactive high 4 † During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. ‡ TW = trail period, write access (see Table 6−25) ns Table 6−35. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)§ MIN MAX UNIT tsu(XRDYsynchL)XCOHL th(XRDYsynchL) Setup time, XREADY (Synch) low before XCLKOUT high/low 15 ns Hold time, XREADY (Synch) low 12 ns te(XRDYsynchH) tsu(XRDYsynchH)XCOHL Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge Setup time, XREADY (Synch) high before XCLKOUT high/low 3 15 ns ns th(XRDYsynchH)XZCSH Hold time, XREADY (Synch) held high after zone chip select high 0 ns § The first XREADY (Synch) sample occurs with respect to E in Figure 6−32: E =(XWRLEAD + XWRACTIVE) tc(XTIM) When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is sampled again each tc(XTIM) until it is found to be high. For each sample, setup time from the beginning of the access can be calculated as: D =(XWRLEAD + XWRACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. Table 6−36. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)¶ MIN tsu(XRDYasynchL)XCOHL th(XRDYasynchL) Setup time, XREADY (Asynch) low before XCLKOUT high/low te(XRDYasynchH) tsu(XRDYasynchH)XCOHL Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge Hold time, XREADY (Asynch) low Setup time, XREADY (Asynch) high before XCLKOUT high/low MAX 11 ns 8 ns 3 11 UNIT ns ns th(XRDYasynchH)XZCSH Hold time, XREADY (Asynch) held high after zone chip select high 0 ns ¶ The first XREADY (Synch) sample occurs with respect to E in Figure 6−33: E = (XWRLEAD + XWRACTIVE − 2) tc(XTIM) When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it is sampled again each tc(XTIM) until it is found to be high. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth. 114 SGUS053B December 2004 − Revised September 2006 Electrical Specifications WS (Synch) See NotesA and B SeeNoteC Trail Active Lead 1 XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK td(XCOHL-XZCSH) td(XCOH-XZCSL) XZCS0AND1, XZCS2, XZCS6AND7 th(XRDYsynchH)XZCSH td(XCOH-XA) XA[0:18] XRD td(XCOHL-XWEH) td(XCOHL-XWEL) XWE td(XCOHL-XRNWH) td(XCOH-XRNWL) XR/W tdis(XD)XRNW td(XWEL-XD) th(XD)XWEH ten(XD)XWEL XD[0:15] DOUT tsu(XRDYsynchL)XCOHL te(XRDYsynchH) th(XRDYsynchL) tsu(XRDHsynchH)XCOHL XREADY(Synch) See Note D See Note E Legend: = Don’t care. Signal can be high or low during this time. NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access can be calculated as D = (XWRLEAD + XWRACTIVE + n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3 and so forth. E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE) tc(XTIM) Figure 6−32. Write With Synchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD N/A† XRDACTIVE N/A† XRDTRAIL N/A† December 2004 − Revised September 2006 USEREADY 1 X2TIMING 0 XWRLEAD ≥1 XWRACTIVE 3 XWRTRAIL ≥1 READYMODE 0 = XREADY (Synch) SGUS053B 115 Electrical Specifications WS (Asynch) " # " Trail Active Lead 1 XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK td(XCOH-XZCSL) td(XCOHL-XZCSH) XZCS0AND1, XZCS2, XZCS6AND7 th(XRDYasynchH)XZCSH td(XCOH-XA) XA[0:18] XRD td(XCOHL-XWEH) td(XCOHL-XWEL) XWE td(XCOH-XRNWL) td(XCOHL-XRNWH) XR/W tdis(XD)XRNW td(XWEL-XD) th(XD)XWEH ten(XD)XWEL XD[0:15] DOUT tsu(XRDYasynchL)XCOHL th(XRDYasynchL) te(XRDYasynchH) tsu(XRDYasynchH)XCOHL XREADY(Asynch) See Note D See Note E Legend: = Don’t care. Signal can be high or low during this time. NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals transitions to their inactive state. C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE −3 + n) tc(XTIM) − tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3 and so forth. E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE −2) tc(XTIM) Figure 6−33. Write With Asynchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE N/A† XRDTRAIL N/A† N/A† USEREADY 1 X2TIMING 0 XWRLEAD ≥1 XWRACTIVE 3 XWRTRAIL ≥1 READYMODE 1 = XREADY (Asynch) † N/A = “Don’t care” for this example 116 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.27 XHOLD and XHOLDA If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode. On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low. When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD signal is removed. An external DMA request, when granted, places the following signals in a high-impedance mode: XA[18:0] XZCS0AND1 XD[15:0] XZCS2 XWE, XRD XZCS6AND7 XR/W All other signals not listed in this group remain in their default or functional operational modes during these signal events. Detailed timing diagram is released in a future revision of this data sheet. December 2004 − Revised September 2006 SGUS053B 117 Electrical Specifications 6.28 XHOLD/XHOLDA Timing Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)†‡ MIN td(HL-HiZ) td(HL-HAL) Delay time, XHOLD low to Hi-Z on all Address, Data, and Control MAX 4tc(XTIM) 5tc(XTIM) Delay time, XHOLD low to XHOLDA low UNIT ns ns td(HH-HAH) Delay time, XHOLD high to XHOLDA high 3tc(XTIM) ns td(HH-BV) Delay time, XHOLD high to Bus valid 4tc(XTIM) ns † When a low signal is detected on XHOLD, all pending XINTF accesses is completed before the bus is placed in a high-impedance state. ‡ The state of XHOLD is latched on the rising edge of XTIMCLK. XCLKOUT (/1 Mode) td(HL-Hiz) XHOLD td(HH-HAH) XHOLDA td(HL-HAL) XR/W, XZCS0AND1, XZCS2, XZCS6AND7 XA[18:0] XD[15:0] td(HH-BV) High-Impedance Valid Valid High-Impedance Valid See Note A See Note B NOTES: A. All pending XINTF accesses are completed. B. Normal XINTF operation resumes. Figure 6−34. External Interface Hold Waveform 118 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Table 6−38. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)†‡§ MIN td(HL-HiZ) td(HL-HAL) Delay time, XHOLD low to Hi-Z on all Address, Data, and Control Delay time, XHOLD low to XHOLDA low MAX UNIT 4tc(XTIM)+tc(XCO) 4tc(XTIM+2tc(XCO) ns ns td(HH-HAH) Delay time, XHOLD high to XHOLDA high 4tc(XTIM) ns td(HH-BV) Delay time, XHOLD high to Bus valid 6tc(XTIM) ns † When a low signal is detected on XHOLD, all pending XINTF accesses is completed before the bus is placed in a high-impedance state. ‡ The state of XHOLD is latched on the rising edge of XTIMCLK. § After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occurs with respect to the rising edge of XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified. XCLKOUT (1/2 XTIMCLK) td(HL-HAL) XHOLD td(HH-HAH) XHOLDA td(HL-HiZ) td(HH-BV) XR/W, XZCS0AND1, XZCS2, XZCS6AND7 XA[18:0] High-Impedance High-Impedance Valid Valid XD[15:0] See Note A NOTES: Valid High-Impedance See Note B A All pending XINTF accesses are completed. B Normal XINTF operation resumes. Figure 6−35. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) December 2004 − Revised September 2006 SGUS053B 119 Electrical Specifications 6.29 On-Chip Analog-to-Digital Converter 6.29.1 ADC Absolute Maximum Ratings † Supply voltage range, VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG . . . . . . . . . . . . . . . −0.3 V to 4.6 V VSS1 to VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V Analog Input (ADCIN) Clamp Current, total (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA‡ † Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The continuous clamp current per pin is ± 2 mA. 120 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions Table 6−39. DC Specifications (See Note 1) PARAMETER MIN Resolution TYP MAX UNIT 12 Bits 1 ADC clock (See Note 2) kHz 25 MHz ACCURACY INL (Integral nonlinearity) (See Note 3) 1−18.75 MHz ADC clock ±1.5 LSB DNL (Differential nonlinearity) (See Note 3) 1−18.75 MHz ADC clock ±1 LSB −80 80 LSB −200 200 LSB −50 50 LSB Offset error (See Note 4) Overall gain error with internal reference (See Note 5) Overall gain error with external reference (See Note 6) If ADCREFP−ADCREFM = 1 V ±0.1% Channel-to-channel offset variation ±8 LSB Channel-to-channel Gain variation ±8 LSB ANALOG INPUT Analog input voltage (ADCINx to ADCLO) (See Note 7) ADCLO 0 −5 Input capacitance 0 3 V 5 mV ±5 µA 10 Input leakage current 3 pF INTERNAL VOLTAGE REFERENCE (See Note 5) Accuracy, ADCVREFP 1.9 2 2.1 V Accuracy, ADCVREFM 0.95 1 1.05 V Voltage difference, ADCREFP − ADCREFM Temperature coefficient Reference noise 1 V 50 PPM/°C 100 µV EXTERNAL VOLTAGE REFERENCE (See Note 6) Accuracy, ADCVREFP 1.9 2 2.1 V Accuracy, ADCVREFM 0.95 1 1.05 V Input voltage difference, ADCREFP − ADCREFM 0.99 1 1.01 V NOTES: 1. Tested at 12.5-MHz ADCCLK 2. If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2 3. The INL degrades for frequencies beyond 18.75 MHz − 25 MHz. Applications that require these sampling rates should use a 20-kΩ resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the ADC is a few mA more than 24.9 kΩ bias. 4. 1 LSB has the weighted value of 3.0/4096 = 0.732 mV. 5. A single internal band gap reference (±5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these voltages track together. The ADC converter uses the difference between these two as its reference. The total gain error is the combination of the gain error shown here and the voltage reference accuracy (ADCREFP − ADCREFM). A software-based calibration procedure is recommended for better accuracy. See F2812 ADC Calibration Application Note (literature number SPRA989) and Section 5.2, Documentation Support, for relevant documents. 6. In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP−ADCREFM) determines the overall accuracy. 7. Voltages above VDDA + 0.3 V or below VSS − 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin. To avoid this, the analog inputs should be kept within these limits. December 2004 − Revised September 2006 SGUS053B 121 Electrical Specifications Table 6−40. AC Specifications PARAMETER MIN TYP MAX UNIT SINAD Signal-to-noise ratio + distortion 62 dB SNR Signal-to-noise ratio 62 dB THD (100 kHz) Total harmonic distortion −68 dB ENOB (SNR) Effective number of bits 10.1 Bits SFDR Spurious free dynamic range 69 dB 6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)‡ IDDA (TYP)§ IDDAIO (TYP) IDD1 (TYP) ADC OPERATING MODE/CONDITIONS Mode A (Operational Mode): − BG and REF enabled − PWD disabled 40 mA 1 µA 0.5 mA 7 mA 0 5 µA Mode B: − ADC clock enabled − BG and REF enabled − PWD enabled 5 µA Mode C: − ADC clock enabled − BG and REF disabled − PWD enabled 0 Mode D: − ADC clock disabled − BG and REF disabled − PWD enabled 1 µA 1 µA 0 0 ‡ Test Conditions: SYSCLKOUT = 150 MHz ADC module clock = 25 MHz ADC performing a continuous conversion of all 16 channels in Mode A § IDDA − includes current into VDDA1 / VDDA2 and AVDDREFBG 122 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Rs Source Signal ADCIN0 Ron 1 kΩ Switch Cp 10 pF ac Ch 1.25 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): Sampling Capacitor (Ch): Parasitic Capacitance (Cp): Source Resistance (Rs): 1 kΩ 1.25 pF 10 pF 50 Ω Figure 6−36. ADC Analog Input Impedance Model 6.29.4 ADC Power-Up Control Bit Timing ADC Power Up Delay ADC Ready for Conversions PWDNBG PWDNREF td(BGR) PWDNADC td(PWD) Request for ADC Conversion Figure 6−37. ADC Power-Up Control Bit Timing Table 6−41. ADC Power-Up Delays† td(BGR) Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register (PWDNBG and PWDNREF) are to be set to 1 before the ADCPWDN bit is enabled. td(PWD) Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register (ADCPWDN) is to be set to 1 before any ADC conversions are initiated. MIN TYP MAX UNIT 7 8 10 ms 20 50 1 ms µs † These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions are started without these delays, the ADC results shows a higher gain. For power down, all three bits can be cleared at the same time. December 2004 − Revised September 2006 SGUS053B 123 Electrical Specifications 6.29.5 Detailed Description 6.29.5.1 Reference Voltage The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP is set to 2 V and ADCVREFM is set to 1 V. 6.29.5.2 Analog Inputs The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time. These inputs are software-selectable. 6.29.5.3 Converter The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low power consumption. 6.29.5.4 Conversion Modes The conversion can be performed in two different conversion modes: • • Sequential sampling mode (SMODE = 0) Simultaneous sampling mode (SMODE = 1) 6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC does conversions on the selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels is sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be one ADC clock wide (minimum) or 16 ADC clocks wide (maximum). 124 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Sample n+2 Sample n+1 Analog Input on Channel Ax or Bx Sample n ADC Clock Sample and Hold SH Pulse SMODE Bit td(SH) tdschx_n+1 tdschx_n ADC Event Trigger from EV or Other Sources tSH Figure 6−38. Sequential Sampling Mode (Single-Channel) Timing Table 6−42. Sequential Sampling Mode Timing SAMPLE n SAMPLE n + 1 AT 25-MHz ADC CLOCK, tc(ADCCLK) = 40 ns td(SH) Delay time from event trigger to sampling tSH Sample/Hold width/ Acquisition width (1 + Acqps) x tc(ADCCLK) 40 ns with Acqps = 0 td(schx_n) Delay time for first result to appear in the Result register 4tc(ADCCLK) 160 ns td(schx_n+1) Delay time for successive results to appear in the Result register December 2004 − Revised September 2006 REMARKS 2.5tc(ADCCLK) (2 + Acqps) x tc(ADCCLK) Acqps value = 0−15 ADCTRL1[8:11] 80 ns SGUS053B 125 Electrical Specifications 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels is sampled simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum). NOTE: In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, and not in other combinations (such as A1/B3, etc.). Sample n Sample n+1 Analog Input on Channel Ax Analog Input on Channel Bv Sample n+2 ADC Clock Sample and Hold SH Pulse SMODE Bit td(SH) tdschA0_n+1 tSH ADC Event Trigger from EV or Other Sources tdschA0_n tdschB0_n+1 tdschB0_n Figure 6−39. Simultaneous Sampling Mode Timing Table 6−43. Simultaneous Sampling Mode Timing SAMPLE n SAMPLE n + 1 AT 25-MHz ADC CLOCK, tc(ADCCLK) = 40 ns td(SH) Delay time from event trigger to sampling tSH Sample/Hold width/ Acquisition Width (1 + Acqps) x tc(ADCCLK) 40 ns with Acqps = 0 td(schA0_n) Delay time for first result to appear in Result register 4tc(ADCCLK) 160 ns td(schB0_n) Delay time for first result to appear in Result register 5tc(ADCCLK) 200 ns td(schA0_n+1) Delay time for successive results to appear in Result register (3 + Acqps) x tc(ADCCLK) 120 ns td(schB0_n+1) Delay time for successive results to appear in Result register (3 + Acqps) x tc(ADCCLK) 120 ns 126 SGUS053B REMARKS 2.5tc(ADCCLK) Acqps value = 0−15 ADCTRL1[8:11] December 2004 − Revised September 2006 Electrical Specifications 6.29.8 Definitions of Specifications and Terminology Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. Zero Offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N+ (SINAD * 1.76) 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. December 2004 − Revised September 2006 SGUS053B 127 Electrical Specifications 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing Table 6−44. McBSP Timing Requirements†‡ NO. MIN MAX UNIT 20§ MHz 1 McBSP module clock (CLKG, CLKX, CLKR) range kHz 50 McBSP module cycle time (CLKG, CLKX, CLKR) range M11 M12 M13 M14 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X ext 2P Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P−7 tr(CKRX) tf(CKRX) Rise time, CLKR/X CLKR/X ext Fall time, CLKR/X CLKR/X ext M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low M18 th(CKRL-DRV) Hold time, DR valid after CLKR low M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns 1 CLKR int 18 CLKR ext 2 CLKR int 0 CLKR ext 6 CLKR int 18 CLKR ext 2 CLKR int 0 CLKR ext 6 CLKX int 18 CLKX ext 2 CLKX int 0 CLKX ext 6 ms ns ns 7 ns 7 ns ns ns ns ns ns ns † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. CLKSRG ‡ 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = . (1 ) CLKGDV) CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. § Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (20 MHz). 128 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Table 6−45. McBSP Switching Characteristics†‡ NO. M1 PARAMETER MIN MAX UNIT tc(CKRX) tw(CKRXH) Cycle time, CLKR/X CLKR/X int 2P M2 Pulse duration, CLKR/X high CLKR/X int tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int D + 5§ C + 5§ ns M3 D − 5§ C − 5§ CLKR int 0 4 ns CLKR ext 3 27 ns CLKX int 0 4 CLKX ext 3 27 M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. M7 td(CKXH-DXV) Delay time, CLKX high to DX valid DXENA = 0 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY= 01b or 10b) modes DXENA = 1 Enable time, CLKX high to DX driven M8 M9 M10 DXENA = 0 ten(CKXH-DX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY= 01b or 10b) modes DXENA = 1 Delay time, FSX high to DX valid DXENA = 0 td(FXH-DXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY= 00b) mode. DXENA = 1 Enable time, FSX high to DX driven DXENA = 0 ten(FXH-DX) ns CLKX int 8 CLKX ext 14 CLKX int 9 CLKX ext 28 CLKX int 8 CLKX ext 14 CLKX int P+8 CLKX ext ns ns ns ns P + 14 CLKX int 0 CLKX ext 6 CLKX int P CLKX ext P+6 ns FSX int 8 FSX ext 14 FSX int P+8 FSX ext P + 14 FSX int 0 FSX ext 6 FSX int P ns ns Only applies to first bit transmitted when in Data DXENA = 1 FSX ext P+6 Delay 0 (XDATDLY= 00b) mode † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ 2P = 1/CLKG in ns § C=CLKRX low pulse width = P D=CLKRX high pulse width = P December 2004 − Revised September 2006 SGUS053B 129 Electrical Specifications M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY= 00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY= 01b) Bit (n−1) (n−2) M17 (n−3) M18 DR (RDATDLY= 10b) Bit (n−1) (n−2) Figure 6−40. McBSP Receive Timing M1, M11 M2, M12 M13 M3, M12 M14 CLKX M5 M5 FSX (int) M19 M20 FSX (ext) M9 M7 M10 DX (XDATDLY= 00b) Bit 0 Bit (n−1) (n−2) (n−3) (n−4) (n−2) (n−3) M7 M8 DX (XDATDLY= 01b) Bit 0 Bit (n−1) M7 M6 DX (XDATDLY= 10b) M8 Bit 0 Bit (n−1) (n−2) Figure 6−41. McBSP Transmit Timing 130 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.30.2 McBSP as SPI Master or Slave Timing Table 6−46. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) MASTER NO. M30 MIN SLAVE MAX MIN MAX UNIT tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low P − 10 8P − 10 ns M31 Hold time, DR valid after CLKX low P − 10 8P − 10 ns M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns M33 tc(CKX) Cycle time, CLKX 16P ns 2P Table 6−47. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)† MASTER NO. M24 M25 M28 PARAMETER th(CKXL-FXL) td(FXL-CKXH) tdis(FXH-DXHZ) MIN SLAVE MAX MIN MAX UNIT Hold time, FSX low after CLKX low 2P ns Delay time, FSX low to CLKX high P ns Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns † 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns. M32 LSB M33 MSB CLKX M25 M24 FSX M28 DX M29 Bit 0 Bit(n-1) M30 DR Bit 0 (n-2) (n-3) (n-4) M31 Bit(n-1) (n-2) (n-3) (n-4) Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 December 2004 − Revised September 2006 SGUS053B 131 Electrical Specifications Table 6−48. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)† MASTER NO. M39 MIN MAX Setup time, DR valid before CLKX high P − 10 M40 tsu(DRV-CKXH) th(CKXH-DRV) Hold time, DR valid after CLKX high P − 10 M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high M42 tc(CKX) Cycle time, CLKX 2P SLAVE MIN MAX UNIT 8P − 10 ns 8P − 10 ns 16P + 10 ns 16P ns Table 6−49. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)† MASTER NO. M34 PARAMETER M35 th(CKXL-FXL) td(FXL-CKXH) M37 tdis(CKXL-DXHZ) MIN MAX SLAVE MIN UNIT MAX Hold time, FSX low after CLKX low P ns Delay time, FSX low to CLKX high 2P ns Disable time, DX high impedance following last data bit from CLKX low P+6 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns † 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns. LSB M42 MSB M41 CLKX M34 M35 FSX M37 DX M38 Bit 0 Bit(n-1) M39 DR Bit 0 (n-2) (n-3) (n-4) M40 Bit(n-1) (n-2) (n-3) (n-4) Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 132 SGUS053B December 2004 − Revised September 2006 Electrical Specifications Table 6−50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)† MASTER NO. M49 MIN Setup time, DR valid before CLKX high P − 10 M50 tsu(DRV-CKXH) th(CKXH-DRV) Hold time, DR valid after CLKX high P − 10 M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low M52 tc(CKX) Cycle time, CLKX SLAVE MAX MIN MAX UNIT 8P − 10 ns 8P − 10 ns 8P + 10 ns 16P ns 2P Table 6−51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)† MASTER NO. M43 PARAMETER M44 th(CKXH-FXL) td(FXL-CKXL) M47 tdis(FXH-DXHZ) MIN Hold time, FSX low after CLKX high MAX SLAVE MIN MAX UNIT 2P ns Delay time, FSX low to CLKX low P ns Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns † 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns. M52 MSB M51 LSB CLKX M43 M44 FSX M47 DX M48 Bit 0 Bit(n-1) M49 DR Bit 0 (n-2) (n-3) (n-4) M50 Bit(n-1) (n-2) (n-3) (n-4) Figure 6−44. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 December 2004 − Revised September 2006 SGUS053B 133 Electrical Specifications Table 6−52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)† NO. M58 MASTER SLAVE MIN MIN Setup time, DR valid before CLKX low P − 10 M59 tsu(DRV-CKXL) th(CKXL-DRV) Hold time, DR valid after CLKX low P − 10 M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low M61 tc(CKX) Cycle time, CLKX MAX MAX UNIT 8P − 10 ns 8P − 10 ns 16P + 10 ns 16P ns 2P Table 6−53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)† MASTER‡ NO. PARAMETER M53 M54 th(CKXH-FXL) td(FXL-CKXL) M56 tdis(CKXH-DXHZ) MIN Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low Disable time, DX high impedance following last data bit from CLKX high SLAVE MAX MIN MAX UNIT P ns 2P ns P+6 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns † 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns. ‡ C = CLKX low pulse width = P D = CLKX high pulse width = P M60 LSB M61 MSB CLKX M53 M54 FSX M56 DX M55 M57 Bit 0 Bit(n-1) M58 DR Bit 0 (n-2) (n-3) (n-4) M59 Bit(n-1) (n-2) (n-3) (n-4) Figure 6−45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 134 SGUS053B December 2004 − Revised September 2006 Electrical Specifications 6.31 Flash Timing 6.31.1 Recommended Operating Conditions Nf Flash endurance for the array (Write/erase cycles) 0°C to 85°C NOTP Maximum One-Time Programmable (OTP) endurance for the array (Write cycles) 0°C to 85°C MIN NOM 100 1000 MAX UNIT cycles 1 write † Flash Timing Endurance is the minimum number of write/erase or write cycles specified over a programming temperature range of 0°C to 85°C. Flash may be read over the operating temperature range of the device. Table 6−54. Flash Parameters at 150-MHz SYSCLKOUT† PARAMETER MIN Erase Time UNIT 35 µs 170 ms 16K Sector 320 ms 8K Sector 10 s 16K Sector 11 s 75 mA Erase IDD3VFLP MAX 8K Sector 16-Bit Word Program Time TYP VDD3VFL current consumption during the Erase/Program cycle Program IDDP VDD current consumption during Erase/Program cycle IDDIOP VDDIO current consumption during Erase/Program cycle † Typical parameters as seen at room temperature using flash API V1 including function call overhead. 35 mA 140 mA 20 mA Table 6−55. Flash/OTP Access Timing PARAMETER ta(fp) ta(fr) MIN TYP MAX UNIT Paged Flash access time 36 ns Random Flash access time 36 ns 60 ns ta(OTP) OTP access time NOTE: For 150 MHz, PAGE WS = 5 and RANDOM WS = 5 For 135 MHz, PAGE WS = 4 and RANDOM WS = 4 Table 6−56. Minimum Required Wait-States at Different Frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE‡ RANDOM WAIT STATE‡§ 150 6.67 5 5 120 8.33 4 4 100 10 3 3 75 13.33 2 2 50 20 1 1 30 33.33 1 1 25 40 0 1 15 66.67 0 1 0 1 4 250 ‡ Formulas to compute page wait state and random wait state: Page Wait State + ƪǒ Ǔ ƫ ƪǒ Ǔ ƫ Random Wait State + t a(fp) t c(SCO) *1 t a(fr) t c(SCO) (round up to the next highest integer), or 0 whichever is larger *1 (round up to the next highest integer), or 1 whichever is larger § Random wait state must be greater than or equal to 1 December 2004 − Revised September 2006 SGUS053B 135 Mechanical Data 7 Mechanical Data The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). 136 SGUS053B December 2004 − Revised September 2006 PACKAGE OPTION ADDENDUM www.ti.com 14-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-0620801QXC ACTIVE CFP HFG 172 1 TBD Call TI N / A for Pkg Type SM320F2812HFGM150 ACTIVE CFP HFG 172 1 TBD Call TI N / A for Pkg Type SMJ320F2812HFGM150 ACTIVE CFP HFG 172 1 TBD Call TI N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1