TI SN65CML100D

SN65CML100
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SLLS547 – NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
FEATURES
DESCRIPTION
D Provides Level Translation From LVDS or
LVPECL to CML, Repeating From CML to
CML
D Signaling Rates1 up to 1.5 Gbps
D CML Compatible Output Directly Drives
Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
D Total Jitter < 70 ps
D Low 100 ps (Max) Part-To-Part Skew
D Wide Common-Mode Receiver Capability
Allows Direct Coupling of Input Signals
D 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
D Propagation Delay Times, 800 ps Maximum
D 3.3-V Supply Operation
D Available in SOIC and MSOP Packages
APPLICATIONS
D
D
D
D
D
Level Translation
622-MHz Central Office Clock Distribution
High-Speed Network Routing
Wireless Basestations
EYE PATTERN
FUNCTIONAL DIAGRAM
A
B
8
4
2
7
6
3
The VBB pin is an internally generated voltage supply to
allow operation with a single-ended LVPECL input. For
single-ended LVPECL input operation, the unused
differential input is connected to VBB as a switching
reference voltage. When used, decouple VBB with a
0.01-µF capacitor and limit the current sourcing or sinking
to 400 µA. When not used, VBB should be left open.
This device is characterized for operation from –40°C to
85°C.
Low Jitter Clock Repeater
VCC
This high-speed translator/repeater is designed for
signaling rates up to 1.5 Gbps to support various
high-speed network routing applications. The driver output
is compatible with current-mode logic (CML) levels, and
directly drives 50-Ω or 25-Ω loads connected to 1.8-V,
2.5-V, or 3.3-V nominal supplies. The capability for direct
connection to the loads may eliminate the need for
coupling capacitors. The receiver input is compatible with
LVDS (TIA/EIA–644), LVPECL, and CML signaling levels.
The receiver tolerates a wide common-mode voltage
range, and may also be directly coupled to the signal
source. The internal data path from input to output is fully
differential for low noise generation and low pulse-width
distortion.
VBB
1.5 Gbps
223–1 PRBS
Y
Z
Vertical Scale = 500 mV/div
750 MHz
Horizontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50 Ω
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
SN65CML100
www.ti.com
SLLS547 – NOVEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PART MARKING
PACKAGE
STATUS
CML100
SOIC
Production
NWB
MSOP
Production
SN65CML100D
SN65CML100DGK
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage range,(2) VCC
–0.5 V to 4 V
±0.5 mA
Sink/source, IBB
Voltage range, (A, B, Y, Z)
Electrostatic discharge
0 V to 4.3 V
Human Body Model(3)
Charged-Device Model(4)
A, B, Y, Z, and GND
±5 kV
All pins
±2 kV
±1500 V
All pins
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
3
3.3
3.6
3.3-V nominal supply at terminator
3
3.3
3.6
2.5-V nominal supply at terminator
2.375
2.5
2.625
1.8-V nominal supply at terminator
1.7
1.9
V
0.1
1
V
0
4
V
400
µA
85
°C
Supply voltage, VCC
Terminator su
supply
ly voltage, VTT
Magnitude of differential input voltage |VID|
Input voltage (any combination of common-mode or input signals)
Output current, VBB
Operating free-air temperature, TA
2
–40
MAX UNIT
V
V
SN65CML100
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SLLS547 – NOVEMBER 2002
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DGK
425 mW
D
725 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
3.4 mW/°C
TA = 85°C
POWER RATING
221 mW
5.8 mW/°C
377 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
DEVICE CHARACTERISTICS
PARAMETER
ICC
VBB
MIN
Supply current, device only
Switching reference voltage(1)
1890
NOM
MAX
9
12
UNIT
mA
1950
2010
mV
(1) VBB parameter varies 1:1 with VCC
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+
MIN TYP(1)
TEST CONDITIONS
Positive-going differential input voltage
threshold
mV
Negative-going differential input voltage
threshold
VID(HYS)
Differential input voltage hysteresis,
VIT+ – VIT–
II
Input current (A or B inputs)
II(OFF)
Power off in
input
ut current (A or B in
inputs)
uts)
VCC = 1.5 V, VI = 0 V or 2.4 V,
Second input at 1.2 V
Input offset current (|IIA – IIB|)
VCC = 1.5 V, VI = 4 V, Second input at 1.2 V
VIA = VIB, 0 ≤ VIA ≤ 4 V
Ci
Differential input capacitance
UNIT
100
See Figure 1 and Table 1
VIT–
IIO
MAX
–100
25
VI = 0 V or 2.4 V, Second input at 1.2 V
VI = 4 V, Second input at 1.2 V
–20
mV
20
33
–20
20
µA
A
µA
33
–6
6
VI = 0.4 sin (4E6πt) + 0.5 V
VCC = 0 V
µA
3
pF
3
(1) All typical values are at 25°C and with a 3.3-V supply.
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
VOH
VOL
|VOD|
VOH
VOL
|VOD|
VOH
VOL
|VOD|
VOH
VOL
|VOD|
Co
PARAMETER
Output high voltage(2)
Output low voltage(2)
Differential output voltage magnitude
Output high voltage(3)
Output low voltage(3)
Differential output voltage magnitude
Output high voltage(2)
Output low voltage(2)
Differential output voltage magnitude
Output high voltage(3)
Output low voltage(3)
MIN
TYP(1)
MAX
RT = 50 Ω
Ω, VTT = 3 V to 3.6
3 6 V or
VTT = 2.5 V ±5%,
S Figure
See
Fi
2
VTT–60
VTT–1100
VTT–10
VTT–800
VTT
VTT–640
mV
640
780
1000
mV
RT = 25 Ω
Ω, VTT = 3 V to 3.6
3 6 V or
VTT = 2.5 V ±5%,
S Figure
See
Fi
2
VTT–60
VTT–550
VTT–10
VTT–400
VTT
VTT–320
mV
320
390
500
mV
VTT–170
VTT–1100
VTT–10
VTT–800
VTT
VTT–640
mV
570
780
1000
mV
VTT–85
VTT–500
VTT–10
VTT–400
VTT
VTT–320
mV
285
390
500
mV
TEST CONDITIONS
RT = 50 Ω, VTT = 1.8 V ±5%,
See Figure 2
RT = 25 Ω, VTT = 1.8 V ±5%,
See Figure 2
Differential output voltage magnitude
Differential output capacitance
VI = 0.4 sin (4E6πt) + 0.5 V
VCC = 0 V
UNIT
mV
mV
mV
mV
3
3
pF
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) Outputs are terminated through 50-Ω resistors to VTT, CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT.
(3) Outputs are terminated through 25-Ω resistors to VTT; CML level specifications are referenced to VTT and tracks 1:1 with variation of VTT.
3
SN65CML100
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SLLS547 – NOVEMBER 2002
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time (20% – 80%)
tsk(p)
tsk(pp)
tjit(per)
tjit(cc)
Propagation delay time, high-to-low-level output
TEST CONDITIONS
RT = 50 Ω or RT = 25 Ω,
See Figure
g
4
Differential output signal fall time (20% – 80%)
Pulse skew (|tPHL – tPLH|)(2)
Part-to-part skew(3)
Period jitter, rms (1 standard deviation)(4)
Cycle-to-cycle jitter (peak)(4)
Peak-to-peak jitter(4)
MIN
NOM(1)
MAX
UNIT
250
800
ps
250
800
ps
300
ps
300
ps
50
ps
0
VID = 0.2 V
750 MHz clock input(5)
750 MHz clock input(6)
1.5 Gbps 223–1 PRBS input(7)
1.5 Gbps 27–1 PRBS input(8)
100
ps
1
5
ps
8
27
ps
tjit(pp)
30
70
ps
tjit(det)
Deterministic jitter, peak-to-peak(4)
25
65
ps
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(4) Jitter parameters are ensured by design and characterization. Measurements are made with a Tektronix TDS6604 oscilloscope running
Tektronix TDSJIT3 software. Agilent E4862B stimulus system jitter 2 ps tjit(per), 16 ps tjit(cc), 25 ps tjit(pp), and 10 ps tjit(det) has been
subtracted from the values.
(5) VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf ≤ 25 ns (20% to 80%), measured over 1000 samples.
(6) VID = 200 mV, 50% duty cycle, VIC = 1.2 V, tr = tf ≤ 25 ns (20% to 80%).
(7) VID = 200 mV, VIC = 1.2 V, tr = tf ≤ 0.25 ns (20% to 80%), measured over 100k samples.
(8) VID = 200 mV, VIC = 1.2 V, tr = tf ≤ 0.25 ns (20% to 80%). Deterministic jitter is sum of pattern dependent jitter and pulse width distortion.
4
SN65CML100
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SLLS547 – NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
IIA
VIA+VIB
2
VIC
A
Y
B
Z
VID
VIA
VIB
VOD
VOY
VOY+VOZ
2
VOZ
IIB
Figure 1. Voltage and Current Definitions
Table 1. Maximum Receiver Input Voltage Threshold
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
OUTPUT
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
H
1.15 V
1.25 V
–100 mV
1.2 V
L
H
4.0 V
3.9 V
100 mV
3.95 V
3.9 V
4. 0 V
–100 mV
3.95 V
L
0.1 V
0.0 V
100 mV
0.5 V
H
0.0 V
0.1 V
–100 mV
0.5 V
L
1.7 V
0.7 V
1000 mV
1.2 V
H
0.7 V
1.7 V
–1000 mV
1.2 V
L
4.0 V
3.0 V
1000 mV
3.5 V
H
3.0 V
4.0 V
–1000 mV
3.5 V
L
1.0 V
0.0 V
1000 mV
0.5 V
H
0.0 V
1.0 V
–1000 mV
0.5 V
L
H = high level, L = low level
Y
RT
VOD
RT
Z
+
_
VTT
VOY VOZ
Figure 2. Output Voltage Test Circuit
Y
VOD
Driver Device
Receiver Device
Z
RT1
RT2
RT1 = RT2 = RT
VTT
Figure 3. Typical Termination for Output Driver
5
SN65CML100
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SLLS547 – NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
RT1
A
VIA
VID
B
VIB
Y
1 pF
Z
VTT
VOY R
T2
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
–0.4 V
RT1 = RT2 = RT
VOZ
tPHL
tPLH
100%
0V
80%
VOY – VOZ
20%
tf
0%
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 4. Timing Test Circuit and Waveforms
PIN ASSIGNMENTS
D AND DGK PACKAGE
(TOP VIEW)
NC
A
B
VBB
1
8
VCC
2
7
Y
3
6
Z
4
5
GND
PIN DESCRIPTIONS
PIN
FUNCTION
A, B
Differential inputs
Y, Z
Differential outputs
VBB
VCC
GND
Reference voltage output
NC
No connect
Power supply
Ground
FUNCTION TABLE
DIFFERENTIAL INPUT
OUTPUTS
VID = VA – VB
VID ≥ 100 mV
Y
Z
H
L
–100 mV < VID < 100 mV
?
?
VID ≤ –100 mV
Open
L
H
?
?
H = high level, L = low level, ? = intermediate
6
SN65CML100
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SLLS547 – NOVEMBER 2002
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
OUTPUT
INPUT
VCC
A
VCC
VCC
VCC
B
Y
7V
Z
7V
7V
7V
7
SN65CML100
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SLLS547 – NOVEMBER 2002
TYPICAL CHARACTERISTICS
10
10
8
6
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 50 Ω,
VTT = 2.5 V
2
8
6
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
f = 750 MHz,
RT = 50 Ω,
VTT = 2.5 V
4
2
250
500
750
–40
1000
–20
0
Figure 5
VTT = 2.5 V
VTT = 1.7 V
300 400 500 600
f – Frequency – MHz
700
450
tPHL
400
375
0
0.5
1
2
2.5
3
3.5
25
tPHL
550
tPLH
525
20
0
20
300 400 500 600
f – Frequency – MHz
40
60
80
Figure 11
100
700
800
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
f = 25 MHz,
RT = 50 Ω,
VTT = 2.5 V
tPHL
tPLH
400
375
–20
20
40
60
80
100
Figure 10
PEAK-TO-PEAK JITTER
vs
DATA RATE
35
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
RT = 50 Ω,
VTT = 2.5 V,
Input = Clock
30
VID = 0.3 V
10
0
100
0
TA– Free-Air Temperature – °C
15
5
–20
425
350
–40
4
30
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
RT = 50 Ω,
VTT = 1.7 V,
f = 25 MHz
575
450
PEAK-TO-PEAK JITTER
vs
FREQUENCY
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
600
200
Figure 9
Peak-To-Peak Jitter – ps
t pd – Propagation Delay Time – ps
1.5
475
VIC – Common Mode Input Voltage – V
TA– Free-Air Temperature – °C
8
tPLH
425
Figure 8
625
600
500
VCC = 3.3 V,
TA = 25°C,
VID = 200 mV
f = 25 MHz,
RT = 50 Ω,
VTT = 2.5 V
475
800
VTT = 2.5 V
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
350
200
VTT = 1.7 V
Figure 7
t pd – Propagation Delay Time – ps
t pd – Propagation Delay Time – ps
V OD – Differential Output Voltage – mV
VTT = 3.3 V
300
500
–40
100
500
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 25 Ω
400
650
80
700
PROPAGATION DELAY TIME
vs
COMMON-MODE INPUT VOLTAGE
500
250
100
60
VTT = 3.3 V
800
Figure 6
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
350
40
900
TA – Free-Air Temperature – °C
f – Frequency – MHz
450
20
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 50 Ω
500
100
0
0
Peak-To-Peak Jitter – ps
0
1000
V OD – Differential Output Voltage – mV
12
I CC – Supply Current – mA
I CC – Supply Current – mA
12
4
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREQUENCY
VID = 0.5 V
VID = 0.8 V
25
20
15
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 0.8 V
RT = 50 Ω,
VTT = 2.5 V
Input = 223–1 PRBS
VID = 0.5 V
10
VID = 0.3 V
5
200
300
400
500
600
700
800
0
200
400
600
800
1000 1200 1400 1600
f – Frequency – MHz
Data Rate – Mbps
Figure 12
Figure 13
SN65CML100
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SLLS547 – NOVEMBER 2002
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK JITTER
vs
COMMON MODE INPUT VOLTAGE
PEAK-TO-PEAK JITTER
vs
COMMON MODE INPUT VOLTAGE
60
20
50
Peak-To-Peak Jitter – ps
Peak-To-Peak Jitter – ps
25
30
VCC = 3.3 V,
TA = 25°C,
RT = 50 Ω,
VTT = 2.5 V
Input = 223–1 PRBS
VID = 0.8 V
15
VID = 0.5 V
10
VID = 0.5 V
30
VID = 0.8 V
20
10
VID = 0.3 V
5
40
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
VIC – Common Mode Input Voltage – V
0
0.5 1
1.5 2
2.5 3
3.5
VIC – Common Mode Input Voltage – V
Figure 14
Peak-To-Peak Jitter – ps
25
20
15
VCC = 3.3 V, TA = 25°C,
VIC = 1.2 V, |VID| = 200 mV,
Input = 223–1 PRBS, RT = 50 Ω
VID = 0.3 V
Peak-To-Peak Jitter – ps
30
VCC = 3.3 V,
TA = 25°C,
RT = 50 Ω,
VTT = 2.5 V
Input = Clock
PEAK-TO-PEAK JITTER
vs
DATA RATE
4
25
VTT = 1.7 V
20
15
VTT = 2.5 V
10
VTT = 3.3 V
5
200
400
600
800
1000 1200 1400 1600
Data Rate – Mbps
Figure 15
Figure 16
PEAK-TO-PEAK JITTER
vs
DATA RATE
VCC = 3.3 V, TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
Input = 223–1 PRBS,
RT = 25 Ω
1.5 Gbps
223–1 PRBS
Vertical Scale = 250 mV/div
VTT = 1.7 V
VTT = 2.5 V
10
750 MHz
VTT = 3.3 V
5
200
400
600
800
Horizontal Scale = 200 ps/div
1000 1200 1400 1600
Data Rate – Mbps
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 25 Ω
Figure 17
Figure 18
1.5 Gbps
223–1 PRBS
1.5 Gbps
223–1 PRBS
Vertical Scale = 250 mV/div
Vertical Scale = 500 mV/div
750 MHz
750 MHz
Horizontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 50 Ω
Figure 19
Horizontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 25 Ω
Figure 20
9
SN65CML100
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SLLS547 – NOVEMBER 2002
TYPICAL CHARACTERISTICS
1.5 Gbps
223–1 PRBS
1.5 Gbps
223–1 PRBS
Vertical Scale = 500 mV/div
Vertical Scale = 250 mV/div
750 MHz
750 MHz
Horizoontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 50 Ω
Figure 21
10
Horizoontal Scale = 200 ps/div
VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 25 Ω
Figure 22
SN65CML100
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SLLS547 – NOVEMBER 2002
TYPICAL CHARACTERISTICS
Power Supply 1
+
3.3 V
–
Power Supply 2
+
VTT
–
J3
DUT
GND
J2
EVM
GND
J4
J5
J1
VCC
J6
100 Ω
J7
50 Ω
DUT
Pattern
Generator
Matched
Cables
SMA to SMA
50 Ω
Matched
Cables
SMA to SMA
EVM
Oscilloscope
Figure 23. Jitter Setup Connections for SN65CML100
11
SN65CML100
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SLLS547 – NOVEMBER 2002
APPLICATION INFORMATION
For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.
When VBB is used, decouple VBB via a 0.01-µF capacitor and limit the current sourcing or sinking to 0.4 mA. When
not used, VBB should be left open.
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.)
3.3 V or 5 V
50 Ω
3.3 V
SN65CML100
A
ECL
B
50 Ω
50 Ω
50 Ω
VTT = VCC –2 V
VTT
Figure 24. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
3.3 V
SN65CML100
A
CML
B
50 Ω
VTT
Figure 25. Current–Mode Logic (CML)
3.3 V
3.3 V
50 Ω
SN65CML100
A
ECL
VBB
B
50 Ω
VTT
VTT = VCC –2 V
Figure 26. Single-Ended (LVPECL)
3.3 V or 5 V
50 Ω
3.3 V
SN65CML100
A
100 Ω
LVDS
B
50 Ω
Figure 27. Low-Voltage Differential Signaling (LVDS)
12
SN65CML100
www.ti.com
SLLS547 – NOVEMBER 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES:A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
13
SN65CML100
www.ti.com
SLLS547 – NOVEMBER 2002
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,08 M
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°–ā6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073329/C 08/01
NOTES:A.
B.
C.
D.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-187
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