TI SN65LVDT41

SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
MEMORY STICK INTERCONNECT EXTENDER CHIPSET WITH LVDS
SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS
SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER
FEATURES
D Integrated 110-Ω Nominal Receiver Line
D
D
D
D
D
D
D
Termination Resistor
Operates From a Single 3.3-V Supply
Greater Than 125 Mbps Data Rate
Flow-Through Pin-Out
LVTTL Compatible Logic I/Os
ESD Protection On Bus Pins Exceeds 16 kV
Meets or Exceeds the Requirements of
ANSI/TIA/EIA-644A Standard for LVDS
20-Pin PW Thin Shrink Small-Outline Package
With 26-Mil Terminal Pitch
APPLICATIONS
D Memory Stick Interface Extensions With Long
Interconnects Between Host and Memory
Stick
D Serial Peripheral Interface (SPI) Interface
Extension to Allow Long Interconnects
Between Master and Slave
D MultiMediaCard  Interface in SPI Mode
D General-Purpose Asymmetric Bidirectional
Communication
DESCRIPTION
The SN65LVDT14 combines one LVDS line driver with
four terminated LVDS line receivers in one package. It
is designed to be used at the Memory Stick end of an
LVDS based Memory Stick interface extension.
SN65LVDT41 LOGIC DIAGRAM
(POSITIVE LOGIC)
1D
2D
3D
4D
The SN65LVDT41 combines four LVDS line drivers with
a single terminated LVDS line receiver in one package.
It is designed to be used at the host end of an LVDS
based Memory Stick interface extension.
SN65LVDT14 LOGIC DIAGRAM
(POSITIVE LOGIC)
1Y
1A
1Z
2Y
1B
1R
2A
2Z
3Y
2B
3Z
4Y
3B
4A
4Z
4B
5A
5Y
5B
5Z
3A
5R
2R
3R
4R
5D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Memory Stick is a trademark of Sony.
Serial Peripheral Interface and SPI are trademarks of Motorola.
MultiMediaCard is a trademark of the MultiMediaCard Association.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
TYPICAL MEMORY STICK INTERFACE EXTENSION
SN65LVDT41
1D
SCLK
Memory
BS
Stick
Host SDIO
Controller
DIR
2D
3D
4D
SN65LVDT14
1Y
SCLK
BS
2Z
3Y
DIR
3Z
4Y
1R
2A
2B
3A
SCLK
Memory
BS Stick
2R
SDIO
3R
3B
SD1
4A
4R
CBT
4B
4Z
CBT
1A
1B
1Z
2Y
5A
SD2
5R
5Y
5D
5Z
5B
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Supply voltage range(2)
Input voltage range
Electrostatic discharge
SN65LVDT14,
SN65LVDT41
UNIT
VCC
D or R
–0.5 to 4
V
–0.5 to 6
V
A, B, Y, or Z
–0.5 to 4
V
±16
KV
±8
KV
±500
V
Human body model(3), A, B, Y, Z, and GND
Human body model(3), all pins
Charged device model(4), all pins
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range
°C
–65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114–A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA <25°C
POWER RATING
PW
774 mW
OPERATING FACTOR
ABOVE TA = 25°C
6.2 mW/°C
TA = 85°C
POWER RATING
402 mW
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
Magnitude of differential input voltage, VID
Common-mode input voltage, VIC (See Figure 1)
Operating free-air temperature, TA
2
0.1
ŤV Ť
ID
2
–40
MAX
3.6
UNIT
V
V
0.8
V
0.6
V
ŤV Ť
ID
2
V
VCC – 0.8
85
V
2.4 *
°C
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
VIC – Common-Mode Input Voltage – V
Max at VCC > 3.15 V
Max at VCC = 3 V
2
1.5
1
0.5
Minimum
0
0
0.1
0.2
0.3
0.4
0.5
0.6
|VID|– Differential Input Voltage – V
Figure 1. VIC vs VID and VCC
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
VITH+
VITH–
Positive-going differential input voltage threshold
VOH
VOL
High-level output voltage
Negative-going differential input voltage threshold
TEST CONDITIONS
See Figure 2 and Table 1
Low-level output voltage
IOH = –8 mA
IOL = 8 mA
II
Input current (A or B inputs)
VI = 0 V and VI = 2.4 V,
other input open
II(OFF)
Ci
Power-off input current (A or B inputs)
Input capacitance, A or B input to GND
Zt
Terminationimpedance
(1) All typical values are at 25°C and with a 3.3-V supply.
MIN TYP(1)
MAX
100
–100
2.4
VCC = 0 V, VI = 2.4 V
VI = A sin 2πft + CV
VID = 0.4 sin2.5E09 t V
UNIT
mV
V
0.4
V
±40
µA
±40
µA
5
88
pF
132
Ω
MAX
UNIT
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
IIH
Peak-to-peak common-mode output voltage
IIL
Low-level input current
IOS
High-level input current
Short circuit output current
Short-circuit
IO(OFF)
Power-off output current
(1) All typical values are at 25°C and with a 3.3-V supply.
TEST CONDITIONS
RL = 100 Ω,
Ω
See Figure 3 and Figure 5
See Figure 6
MIN TYP(1)
247
340
VOY or VOZ = 0 V
VOD = 0 V
VCC = 1.5 V,
VO = 2.4 V
mV
–50
50
1.125
1.375
–50
50
mV
150
mV
20
µA
10
µA
50
VIH = 2 V
VIL = 0.8 V
454
±24
V
±12
mA
±1
µA
3
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
ICC
TEST CONDITIONS
SN65LVDT14
Supply current
SN65LVDT41
MIN TYP(1)
Driver RL = 100 Ω, Driver VI = 0.8 V or 2 V,
Receiver VI = ±0.4 V
MAX
25
35
UNIT
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output
1
2.6
3.8
ns
Propagation delay time, high-to-low-level output
1
2.6
3.8
ns
tr
tf
Output signal rise time
1.2
ns
1.2
ns
tsk(p)
tsk(o)
Pulse skew (|tPHL – tPLH|)
Output skew(1)
600
ps
Output signal fall time
0.15
CL = 10 pF,
F, See Figure 4
0.15
150
100
400
ps
tsk(pp) Part-to-part skew(2)
1
ns
(1) tsk(o) is the magnitude of the time difference between the tpLH or tpHL of all the receivers of a single device with all of their inputs connected
together.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
tr
tf
Differential output signal rise time
tsk(p)
tsk(o)
Pulse skew (|tPHL – tPLH|)
Output skew(1)
Propagation delay time, high-to-low-level output
TEST CONDITIONS
RL = 100 Ω,
Ω CL = 10 pF,
pF
See Figure 7
Differential output signal fall time
Part-to-part skew(2)
RL = 100 Ω, CL = 10 pF,
F,
See Figure 7
MIN
NOM
MAX
0.9
1.7
2.9
0.9
1.6
2.9
0.26
1
0.26
1
UNIT
ns
150
500
ps
80
150
ps
tsk(pp)
1.5
ns
(1) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
A
V
IA
)V
IB
R
VID
2
VIA
B
VIC
VO
VIB
Figure 2. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0.0 V
100 mV
0.05 V
0.0 V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0.0 V
600 mV
0.3 V
0.0 V
0.6 V
–600 mV
0.3 V
IOY
Y
II
D
IOZ
VOD
V
VOY
Z
VI
OY
)V
OZ
2
VOC
VOZ
Figure 3. Driver Voltage and Current Definitions
5
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
– 0.4 V
tPHL
VO
tPLH
VOH
80%
VCC/2
20%
VOL
tf
NOTE A:
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse
width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. Receiver Timing Test Circuit and Waveforms
6
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
3.75 kΩ
Y
+
_
100 Ω
VOD
Input
Z
0 V ≤ Vtest ≤ 2.4 V
3.75 kΩ
Figure 5. Driver VDO Test Circuit
49.9 Ω, ±1% (2 Places)
3V
Y
D
VIA
Input
Z
2 pF
0V
VOC
VOC(PP)
VOC(SS)
VOC
NOTE A:
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 6. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
VOD
Input
100 Ω
±1%
Z
CL
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
Output
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse
width = 0.5 ± 0.05 µs . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 7. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
SN65LVDT41 (Marked as LVDT41)
1D
GND
2D
VCC
3D
GND
4D
VCC
5R
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SN65LVDT14 (Marked as LVDT14)
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
5A
5B
1A
1B
2A
2B
3A
3B
4A
4B
5Y
5Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1R
GND
2R
VCC
3R
GND
4R
VCC
5D
GND
Function Tables
RECEIVER
DRIVER
INPUTS
OUTPUT
INPUT
VID = VA – VB
R
D
Y
VID ≥ 100 mV
H
H
H
L
–100 mV < VID < 100 mV
?
L
L
H
VID ≤ –100 mV
Open
L
Open
L
H
H
H = high level, L = low level , ? = indeterminate
8
OUTPUTS
H = high level, L = low level
Z
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
A
110 Ω
VCC
VCC
B
300 kΩ
300 kΩ
5Ω
A Input
R Output
B Input
7V
7V
7V
DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
50 Ω
D Input
10 kΩ
7V
5Ω
Y or Z
Output
300 kΩ
7V
9
SN65LVDT14, SN65LVDT41
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SLLS530 – APRIL 2002
TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
5
TA = 25°C,
VCC = 3.3 V
TA = 25°C,
VCC = 3.3 V
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
3.5
3
2.5
2
1.5
1
0.5
4
3.5
3
2.5
2
1.5
1
0.5
0
–70
–60
0
–50
–40
–30
–20
–10
0
0
10
IOH – High-Level Output Current – mA
20
t PHL – High-To-Low Propagation Delay Time – ns
t PLH – Low-To-High Propagation Delay Time – ns
10
60
70
80
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3
2.9
VCC = 3 V
2.8
VCC = 3.3 V
2.7
2.6
VCC = 3.6 V
2.4
2.3
–25
0
25
50
75
TA – Free-Air Temperature – °C
Figure 10
50
Figure 9
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.2
–50
40
IOL – Low-Level Output Current – mA
Figure 8
2.5
30
100
2.8
2.7
2.6
VCC = 3 V
2.5
VCC = 3.3 V
2.4
VCC = 3.6 V
2.3
2.2
2.1
2
–50
–25
0
25
50
TA – Free-Air Temperature – °C
Figure 11
75
100
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
TYPICAL CHARACTERISTICS
DRIVER
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.1
2
t PHL – High-To-Low Propagation Delay Time – ns
t PLH – Low-To-High Propagation Delay Time – ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
VCC = 3 V
1.9
1.8
VCC = 3.6 V
1.7
1.6
VCC = 3.3 V
1.5
–50
–25
0
25
50
75
TA – Free-Air Temperature – °C
Figure 12
100
2.2
2.1
VCC = 3 V
2
VCC = 3.3 V
1.9
1.8
1.7
VCC = 3.6 V
1.6
1.5
–50
–25
0
25
50
75
Ta – Free-Air Temperature – °C
100
Figure 13
11
SN65LVDT14, SN65LVDT41
www.ti.com
SLLS530 – APRIL 2002
APPLICATION INFORMATION
EXTENDING THE MEMORY STICK INTERFACE USING LVDS SIGNALING OVER DIFFERENTIAL
TRANSMISSION CABLES
SN65LVDT41
1D
SCLK
Memory
BS
Stick
Host SDIO
Controller
DIR
2D
3D
4D
SN65LVDT14
1Y
SCLK
2A
BS
2Z
3Y
DIR
3Z
4Y
5A
5R
5B
1R
2B
3A
SCLK
Memory
BS Stick
2R
SDIO
3R
3B
SD1
4A
4R
4B
4Z
CBT
1A
1B
1Z
2Y
SD2
CBT
5Y
5D
5Z
Figure 14. System Level Block Diagram
The Memory Stick signaling interface operates in a
master-slave architecture, with three active signal lines.
The host (master) supplies a clock (SCLK) and bus-state
(BS) signal to control the operation of the system. The
SCLK and BS signals are unidirectional (simplex) from the
host to the Memory Stick. The serial data input-output
(SDIO) signal is a bidirectional (half-duplex) signal used
to communicate both control and data information
between the host and the Memory Stick. The direction of
data control is managed by the host through a combination
of BS line states and control information delivered to the
Memory Stick.
The basic Memory Stick interface is capable of operating
only over short distances due to the single-ended nature
of the digital I/O signals. Such a configuration is entirely
suitable for compact and portable devices where there is
little if any separation between the host and the Memory
Stick. In applications where a greater distance is needed
between the host controller and the Memory Stick, it is
necessary to utilize a different signaling method such as
low voltage differential signaling, or LVDS. LVDS, as
12
specified by the TIA/EIA-644-A standard, provides several
benefits when compared to alternative long-distance
signaling technologies: low radiated emissions, high noise
immunity, low power consumption, inexpensive
interconnect cables.
This device pair provides the necessary LVDS drivers and
receivers specifically targeted at implementing a Memory
Stick interconnect extension. It utilizes simplex links for the
SCLK and BS signals, and two simplex links for the SDIO
data. The half-duplex SDIO data is split into two simplex
streams under control of the host processor by means of
the direction (DIR) signal. The DIR signal is also carried
from the host to the Memory Stick on a simplex LVDS link.
The switching of the SDIO signal flow direction in the
single-ended interfaces is managed by electronic switch
devices, identified by the CBT symbol in Figure 14. A
suggested CBT device for this application is the
SN74CBTLV1G125 from Texas Instruments Incorporated.
These devices are available in space saving SOT-23 or
SC-70 packages.
SN65LVDT14, SN65LVDT41
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SLLS530 – APRIL 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
13
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