SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages D, DGV, OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND description This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The SN74ALVC74 is characterized for operation from –40°C to 85°C. PRODUCT PREVIEW FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q L H X X H Q L H L X X H H† L L L X X L H† H H ↑ H H H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 5 S 3 1Q C1 2 1D 1 6 1Q R 10 9 11 2Q 12 8 13 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q PRODUCT PREVIEW CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 recommended operating conditions (see Note 4) Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 V 1.7 2 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOL ∆t/∆v 0.8 VCC VCC VCC = 1.65 V VCC = 2.3 V V V –4 –12 VCC = 2.7 V VCC = 3 V mA –12 –24 VCC = 1.65 V VCC = 2.3 V Low level output current Low-level V 0.7 VCC = 2.7 V to 3.6 V High level output current High-level V 0.65 × VCC VIL IOH UNIT 4 12 VCC = 2.7 V VCC = 3 V mA 12 24 Input transition rise or fall rate 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 2.3 V 0.4 2.3 V 0.7 V 2.7 V 0.4 3V 0.55 3.6 V ±5 µA 3.6 V 20 µA 3 V to 3.6 V 750 µA VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 UNIT VCC–0.2 1.2 0.45 IOL = 24 mA VI = VCC or GND IO = 0 Other inputs at VCC or GND MAX 1.65 V IOL = 4 mA IOL = 6 mA VI = VCC or GND, One input at VCC – 0.6 V, TYP† 1.65 V to 3.6 V IOL = 12 mA II ICC MIN 3.3 V • DALLAS, TEXAS 75265 pF 3 PRODUCT PREVIEW VCC SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX MHz PRE or CLR low ns CLK high or low Data before CLK↑ ns PRE or CLR inactive Data after CLK↑ ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PRODUCT PREVIEW PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN fmax tpd d UNIT MAX MHz CLK PRE or CLR ns Q or Q operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per flip-flop CL = 0, VCC = 1.8V TYP f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 2.5 V TYP VCC = 3.3 V TYP UNIT pF SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 tPZH tPHL VOH VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOL PRODUCT PREVIEW Timing Input Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 PRODUCT PREVIEW VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control (low-level enabling) 1.5 V Input 1.5 V 1.5 V 0V tPLH 1.5 V tPLZ 3V 1.5 V tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0V tPZL 2.7 V PRODUCT PREVIEW 2.7 V Data Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. 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