SN74LS166 8-Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. http://onsemi.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage 16 Min Typ Max Unit 1 4.75 5.0 5.25 V 0 25 70 °C SOIC D SUFFIX CASE 751B TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS166N 16 Pin DIP 2000 Units/Box SN74LS166D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS166/D SN74LS166 PARALLEL PARALLEL INPUTS SHIFT/ INPUT OUTPUT G H QH VCC LOAD 16 F E CLEAR 15 14 13 12 11 10 9 SHIFT/ LOAD H QH G F E SERIAL INPUT 1 SERIAL INPUT A B C D 2 A 3 B 4 C 5 D CLEAR CLOCK INHIBIT CK 8 6 7 CLOCK CLOCK GND INHIBIT PARALLEL INPUTS FUNCTION TABLE INPUTS CLEAR L H H H H H PARALLEL SHIFT/ LOAD CLOCK INHIBIT CLOCK X X L H H X X L L L L H X L ↑ ↑ ↑ ↑ INTERNAL OUTPUTS SERIAL X X X H L X A...H QA QB X X a...h X X X L QA0 a H L QA0 L QB0 b QAn QAn QB0 http://onsemi.com 2 OUTPUT QH L QH0 h QGn QGn QH0 SN74LS166 Typical Clear, Shift, Load, Inhibit, and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD PARALLEL INPUTS A H B L C H L D H L E F G H H H OUTPUT QH INHIBIT SERIAL SHIFT CLEAR H H L LOAD (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A R CK S QA B (3) R CK S QB C (4) R CK S QC D (5) R CK S QD E (10) R F CK S QE (11) R CK S QF (12) G R CK S QG H CLOCK CLOCK INHIBIT (14) (7) R (6) CK S (13) Q H http://onsemi.com 3 H L H L SERIAL SHIFT H SN74LS166 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 38 mA VCC = MAX – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 4 SN74LS166 TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT FOR TEST SHIFT/LOAD OUTPUT TESTED H 0V QH at tn+1 Serial Input 4.5 V QH at tn+8 AC WAVEFORMS tw(clear) CLEAR INPUT Vref 3V Vref 0V tn + 1 tn (SEE NOTE 1) tn tn + 1 3V Vref CLOCK INPUT tsu tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref Vref Vref 0V th tsu th 3V Vref Vref 0V tPHL (clear-Q) Vref OUTPUT Q tPHL (CLK-Q) tPLH (CLK-Q) VOH Vref Vref VOL NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 35 Max Unit fMAX Maximum Clock Frequency tPHL Clear to Output 19 30 ns tPLH tPHL Clock to Output 23 24 35 35 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW Clock Clear Pulse Width 30 ns ts Mode Control Setup Time 30 ns ts Data Setup Time 20 ns th Hold Time, Any Input 15 ns http://onsemi.com 5 Test Conditions VCC = 5 5.0 0V SN74LS166 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS166 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS166 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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