SN74LVC1G98-Q1 www.ti.com ........................................................................................................................................................ SCES562C – MARCH 2004 – REVISED APRIL 2008 CONFIGURABLE MULTIPLE-FUNCTION GATE FEATURES 1 • • • • • • • • Qualified for Automotive Applications Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 7.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DBV OR DCK PACKAGE (TOP VIEW) In1 GND In0 1 6 2 5 3 4 In2 VCC Y DESCRIPTION/ORDERING INFORMATION This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G98-Q1 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND. This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) (3) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) SOT (SOT-23) – DBV Tape and reel SN74LVC1G98QDBVRQ1 C98_ SOT (SC-70) – DCK Tape and reel SN74LVC1G98QDCKRQ1 CW_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2008, Texas Instruments Incorporated SN74LVC1G98-Q1 SCES562C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com FUNCTION TABLE INPUTS In2 In1 In0 OUTPUT Y L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L LOGIC DIAGRAM (POSITIVE LOGIC) In0 3 4 In1 In2 1 Y 6 FUNCTION SELECTION TABLE LOGIC FUNCTION 2 FIGURE NO. 2-to-1 data selector with inverted output 1 2-input NAND gate 2 2-input NOR gate with one inverted input 3 2-input AND gate with one inverted input 3 2-input NAND gate with one inverted input 4 2-input OR gate with one inverted input 4 2-input NOR gate 5 Noninverted buffer 6 Inverter 7 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 SN74LVC1G98-Q1 www.ti.com ........................................................................................................................................................ SCES562C – MARCH 2004 – REVISED APRIL 2008 LOGIC CONFIGURATIONS VCC VCC A/B A A Y B B 1 6 2 5 3 4 A/B A Y B B Y GND 1 6 2 5 3 4 A Y GND Figure 1. 2-to-1 Data Selector With Inverted Output Figure 2. 2-Input NAND Gate VCC VCC A A Y A Y B B Y B B 1 6 2 5 3 4 A B A Y B Y 1 6 2 5 3 4 A Y GND GND Figure 3. 2-Input NOR Gate With One Inverted Input 2-Input AND Gate With One Inverted Input Figure 4. 2-Input NAND Gate With One Inverted Input 2-Input OR Gate With One Inverted Input VCC VCC A Y B B 1 6 2 5 3 4 A A Y Y 1 6 2 5 3 4 A Y GND GND Figure 5. 2-Input NOR Gate Figure 6. Noninverted Buffer VCC A A Y 1 6 2 5 3 4 Y GND Figure 7. Inverter Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 Submit Documentation Feedback 3 SN74LVC1G98-Q1 SCES562C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DBV package 165 DCK package 259 –65 V °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) Operating MIN MAX 1.65 5.5 UNIT VCC Supply voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V Data retention only 1.5 VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V Low-level output current –24 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V (1) 4 mA 24 VCC = 4.5 V TA mA –24 VCC = 4.5 V IOL V 24 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 SN74LVC1G98-Q1 www.ti.com ........................................................................................................................................................ SCES562C – MARCH 2004 – REVISED APRIL 2008 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT– Negative-going input threshold voltage ΔVT Hysteresis (VT+ – VT–) IOH = –100 µA VOH (1) 1 1.8 3V 1.3 2.2 4.5 V 1.9 3.1 5.5 V 2.2 3.6 1.65 V 0.3 0.7 2.3 V 0.5 1 3V 0.7 1.4 4.5 V 1 2 5.5 V 1.2 2.3 1.65 V 0.3 0.8 2.3 V 0.4 0.9 3V 0.5 1 4.5 V 0.6 1.5 5.5 V 0.7 1.7 1.2 1.9 IOH = –16 mA 3V 2.4 3V 2.3 4.5 V 3.8 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 16 mA 3V 0.45 3V 0.55 4.5 V 0.58 VI or VO = 5.5 V VI = 5.5 V or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND V V V V 1.65 V to 5.5 V VI = 5.5 V or GND UNIT VCC – 0.2 2.3 V Ioff Ci 2.3 V IOH = –8 mA ICC ΔICC 1.4 1.65 V IOL = 24 mA II 0.6 1.65 V to 5.5 V IOL = 100 µA MAX 1.65 V IOH = –4 mA IOH = –24 mA VOL MIN TYP (1) VCC V 0 to 5.5 V ±5 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.5 V 500 µA 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 Submit Documentation Feedback 5 SN74LVC1G98-Q1 SCES562C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8) PARAMETER tpd FROM (INPUT) TO (OUTPUT) Any In Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 3.2 16.4 2 9.3 1.5 7.3 1.1 6.1 UNIT ns Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance Submit Documentation Feedback TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 23 23 23 26 UNIT pF Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 SN74LVC1G98-Q1 www.ti.com ........................................................................................................................................................ SCES562C – MARCH 2004 – REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 8. Load Circuit and Voltage Waveforms Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G98-Q1 Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 3-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G98QDBVRQ1 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G98QDCKRQ1 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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