SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) TSSOP – PW Reel of 2000 ORDERABLE PART NUMBER SN74LVC245AIPWREP TOP-SIDE MARKING C245AEP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation LOGIC DIAGRAM (POSITIVE LOGIC) DIR 1 19 A1 2 18 To Seven Other Channels 2 OE B1 SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) 83 °C/W 150 °C impedance (4) –65 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) TA = 25°C VCC Supply voltage VIH High-level input voltage Operating Data retention only –40°C to 85°C MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.5 1.5 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V UNIT V V 2 0.35 × VCC 0.35 × VCC 0.7 0.7 VIL Low-level input voltage VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V VCC = 2.7 V to 3.6 V VCC = 1.65 V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate (1) 0.8 –4 V 0.8 –4 VCC = 2.3 V –8 –8 VCC = 2.7 V –12 –12 VCC = 3 V –24 –24 VCC = 1.65 V 4 4 VCC = 2.3 V 8 8 VCC = 2.7 V 12 12 VCC = 3 V 24 24 10 10 mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH MIN 1.65 V to 3.6 V –40°C to 85°C TYP MAX MIN MAX VCC – 0.2 VCC – 0.2 IOH = –4 mA 1.65 V 1.29 1.2 IOH = –8 mA 2.3 V 1.9 1.7 2.7 V 2.2 2.2 2.4 IOH = –12 mA VOL TA = 25°C VCC UNIT V 3V 2.4 IOH = –24 mA 3V 2.3 IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 IOL = 4 mA 1.65 V 0.24 0.45 IOL = 8 mA 2.3 V 0.3 0.7 IOL = 12 mA 2.7 V 0.4 0.4 IOL = 24 mA 3V 0.55 0.55 2.2 V 3.6 V ±1 ±5 µA Ioff VI or VO = 5.5 V 0 ±1 ±10 µA IOZ (1) VO = 0 to 5.5 V 3.6 V ±1 ±10 µA 1 10 1 10 500 500 II Control inputs VI = 0 to 5.5 V VI = VCC or GND ICC IO = 0 3.6 V ≤ VI ≤ 5.5 V (2) One input at VCC – 0.6 V, Other inputs at VCC or GND ∆ICC 3.6 V 2.7 V to 3.6 V µA µA Ci Control inputs VI = VCC or GND 3.3 V 4 pF Cio A or B port VI = VCC or GND 3.3 V 5.5 pF (1) (2) For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC 4 MIN –40°C to 85°C TYP MAX MIN MAX 1.8 V ± 0.15 V 1 6 12.2 1 12.7 2.5 V ± 0.2 V 1 3.9 7.8 1 8.3 2.7 V 1 4.2 7.1 1 7.3 3.3 V ± 0.3 V 1.5 3.8 6.1 1.5 6.3 1.8 V ± 0.15 V 1 7 14.8 1 15.3 2.5 V ± 0.2 V 1 4.5 10 1 10.5 2.7 V 1 5.4 9.3 1 9.5 3.3 V ± 0.3 V 1.5 4.4 8.3 1.5 8.5 1.8 V ± 0.15 V 1 7.8 16.5 1 17 2.5 V ± 0.2 V 1 4 9 1 9.5 2.7 V 1 4.4 8.3 1 8.5 1.7 4.1 7.3 1.7 7.5 3.3 V ± 0.3 V tsk(o) TA = 25°C 3.3 V ± 0.3 V 1 UNIT ns ns ns ns SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Outputs enabled Cpd Power dissipation capacitance per transceiver f = 10 MHz Outputs disabled VCC TYP 1.8 V 42 2.5 V 43 3.3 V 45 1.8 V 1 2.5 V 1 3.3 V 2 UNIT pF 5 SN74LVC245A-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS741B – DECEMBER 2003 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LVC245AIPWREP ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples V62/04737-01XE ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVC245A-EP : • Catalog: SN74LVC245A NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Oct-2010 • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC245AIPWREP Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC245AIPWREP TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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