SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 D Member of the Texas Instruments D D D D D Typical VOHV (Output VOH Undershoot) Widebus+ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D D >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) description/ordering information This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA LFBGA − GKE −40°C to 85°C TOP-SIDE MARKING SN74LVC32244GKER LFBGA − ZKE (Pb-free) Tape and reel SN74LVC32244ZKER NC244 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 GKE OR ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 terminal assignments 1 2 3 4 5 6 A A 1Y2 1Y1 1OE 2OE 1A1 1A2 B B 1Y4 1Y3 GND GND 1A3 1A4 C C 2Y2 2Y1 2A2 D 2Y4 2Y3 VCC GND 2A1 D VCC GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 E F G H J K L M F 3Y4 3Y3 4Y1 VCC GND 3A4 4Y2 VCC GND 3A3 G 4A1 4A2 H 4Y3 4Y4 4OE 3OE 4A4 4A3 J 5Y2 5Y1 5OE 6OE 5A1 5A2 K 5Y4 5Y3 GND GND 5A3 5A4 L 6Y2 6Y1 6A2 6Y4 6Y3 VCC GND 6A1 M VCC GND 6A3 6A4 N 7Y2 7Y1 GND GND 7A1 7A2 N P 7Y4 7Y3 8Y2 8Y1 VCC GND 7A4 R VCC GND 7A3 P 8A1 8A2 R T 8Y3 8Y4 8OE 7OE 8A4 8A3 T FUNCTION TABLE (each 4-bit buffer) INPUTS 2 OE A OUTPUT Y L H H L L L H X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 POST OFFICE BOX 655303 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 • DALLAS, TEXAS 75265 8Y1 8Y2 8Y3 8Y4 3 SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): GKE/ZKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) Operating VCC Supply voltage VIH High-level input voltage VIL Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 0.65 × VCC 1.7 VO IOH Input voltage Output voltage High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate V 2 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V VI V 1.5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V Low-level input voltage UNIT V 0.8 0 5.5 V High or low state 0 3-state 0 VCC 5.5 V VCC = 1.65 V VCC = 2.3 V −4 VCC = 2.7 V VCC = 3 V −12 −8 mA −24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V 12 8 mA 24 10 ns/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 µA IOH = −4 mA VOH MIN 1.65 V to 3.6 V 1.65 V VCC−0.2 1.2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2.2 IOH = −8 mA IOH = −12 mA IOH = −24 mA IOL = 100 µA TYP† VCC MAX UNIT V 1.65 V to 3.6 V 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II Ioff VI = 0 to 5.5 V VI or VO = 5.5 V 3.6 V ±5 µA 0 ±10 µA IOZ VO = 0 to 5.5 V VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V‡ 3.6 V ±10 µA VOL ICC ∆ICC Ci Co 40 IO = 0 One input at VCC − 0.6 V, 3.6 V Other inputs at VCC or GND 40 2.7 V to 3.6 V VI = VCC or GND VO = VCC or GND 500 V µA A µA 3.3 V 5.5 pF 3.3 V 6 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This applies in the disabled state only. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX Y § § § OE Y § § OE Y § § VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX § 4.7 1.1 4.1 ns § § 5.8 1 4.6 ns § § 6.2 1.8 5.8 ns 1 ns tsk(o) § This information was not available at the time of publication. operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per buffer/driver VCC = 1.8 V TYP Outputs enabled Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP § § 34 § § 4 UNIT pF § This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES342C − OCTOBER 2000 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPLZ tPZL VLOAD/2 VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH VOH Output VI Output Control VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC32244GKER ACTIVE LFBGA GKE 96 1000 SN74LVC32244ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) None Lead/Ball Finish MSL Peak Temp (3) SNPB Level-3-220C-168 HR SNAGCU Level-3-250C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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