TI SN74LVC74

SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
D
D
D
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
D, DB, OR PW PACKAGE
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
description
This dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at the outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC74 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
L
X
X
L
H†
H
H†
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
logic symbol†
4
1PRE
1CLK
1D
1
1CLR
6
9
11
2CLK
1Q
R
10
2PRE
1Q
C1
2
1D
5
S
3
2Q
12
2D
8
13
2CLR
2Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . 1.25 W
DB or PW package . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
recommended operating conditions (see Note 4)
Operating
MIN
MAX
2
3.6
UNIT
VCC
Supply voltage
VIH
VIL
High-level input voltage
0.8
V
VI
VO
Input voltage
0
5.5
V
Output voltage
0
V
IOH
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
VCC
– 12
IOL
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
∆t /∆v
Input transition rise or fall rate
Data retention only
1.5
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
2
V
– 24
12
24
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
V
mA
mA
0
10
ns / V
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VCC†
MIN to MAX
TEST CONDITIONS
IOH = – 100 µA
VOH
MIN
IOH = – 24 mA
IOL = 100 µA
MAX
VCC – 0.2
2.2
2.7 V
IOH = – 12 mA
TYP‡
3V
2.4
3V
2.2
UNIT
V
MIN to MAX
0.2
VOL
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
3.6 V
±5
µA
10
µA
500
µA
nICC
One input at VCC – 0.6 V,
IO = 0
Other inputs at VCC or GND
3.6 V
2.7 V to 3.6 V
Ci
VI = VCC or GND
3.3 V
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
5
V
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 3.3 V
± 0.3 V
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
POST OFFICE BOX 655303
VCC = 2.7 V
MIN
MAX
MIN
MAX
0
100
0
83
PRE or CLR low
4
5
CLK high or low
5
6
Data
3
4
PRE or CLR inactive
2
3
1
2
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
3
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 3.3 V
± 0.3 V
TO
(OUTPUT)
MIN
fmax
tpd
MAX
VCC = 2.7 V
MIN
100
CLK
Q or Q
PRE or CLR
tsk(o)†
UNIT
MAX
83
MHz
1
6.5
7
1
8
9
1
ns
ns
† Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per flip-flop
POST OFFICE BOX 655303
TEST CONDITIONS
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 10 MHz
TYP
UNIT
27
pF
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
1.5 V
1.5 V
tsu
Input
Input
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
v
v
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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