SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 D D description The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC74A dual positiveedge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE (TOP VIEW) 1CLK NC 1PRE NC 1Q 2CLR D 1 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 2Q 2Q D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1CLR NC VCC D SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . D, DB, OR PW PACKAGE (TOP VIEW) 1D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and DIPs (J) 1Q GND NC D NC – No internal connection A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN54LVC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVC74A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X H H† L L X X L H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol‡ 4 1PRE 1CLK 1D 1 1CLR 6 9 11 2CLK 1Q R 10 2PRE 1Q C1 2 1D 5 S 3 2Q 12 2D 8 13 2CLR 2Q ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, PW, and W packages. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input-voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVC74A VCC Supply voltage VIH High-level input voltage Operating Data retention only VIL Low-level input voltage VI VO Input voltage IOH IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate MIN MAX 2 3.6 1.65 3.6 1.5 1.5 0.65×VCC 1.7 2 UNIT V V 2 0.35×VCC 0.7 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Output voltage High level output current High-level MAX VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V SN74LVC74A MIN 0.8 V 0.8 0 5.5 0 5.5 V 0 VCC 0 VCC –4 V VCC = 1.65 V VCC = 2.3 V –8 VCC = 2.7 V VCC = 3 V –12 –12 –24 –24 VCC = 1.65 V VCC = 2.3 V mA 4 8 VCC = 2.7 V VCC = 3 V 12 12 24 0 10 mA 24 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = –4 mA IOH = –8 mA II ICC ∆ICC 1.2 V 1.7 2.7 V 2.2 2.2 3V 2.4 2.4 3V 2.2 2.2 1.65 V to 3.6 V IOL = 100 µA UNIT VCC–0.2 2.3 V IOH = –24 mA SN74LVC74A TYP† MAX MIN VCC–0.2 1.65 V IOH = –12 12 mA VOL MIN 1.65 V to 3.6 V IOH = –100 100 µA VOH SN54LVC74A TYP† MAX VCC 0.2 2.7 V to 3.6 V 0.2 IOL = 4 mA IOL = 8 mA 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 VI = 5.5 V or GND VI = VCC or GND, 3.6 V ±5 ±5 µA 3.6 V 10 10 µA 500 500 µA IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 3.3 V 5 5 V pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC74A VCC = 2.7 V MIN 4 fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MAX VCC = 3.3 V ± 0.3 V MIN 83 POST OFFICE BOX 655303 3.3 3.3 CLK high or low 3.3 3.3 Data 3.4 3 PRE or CLR inactive 2.2 2 1 1 • DALLAS, TEXAS 75265 MAX 100 PRE or CLR low UNIT MHz ns ns ns SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) SN74LVC74A VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ MAX † VCC = 2.5 V ± 0.2 V MIN MAX † VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 100 † † 3.3 3.3 CLK high or low † † 3.3 3.3 Data † † 3.4 3 PRE or CLR inactive † † 2.2 2 † † 1 0 th Hold time, data after CLK↑ † This information was not available at the time of publication. MAX 83 PRE or CLR low UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC74A FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 2.7 V MIN fmax MAX 83 Q or Q PRE or CLR MIN UNIT MAX 100 CLK tpd d VCC = 3.3 V ± 0.3 V MHz 6 1 5.2 6.4 1 5.4 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) SN74LVC74A PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK PRE or CLR Q or Q VCC = 1.8 V ± 0.15 V MIN † MAX † † VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN † MAX † † † 6 1 5.2 † † † 6.4 1 5.4 83 MIN UNIT MAX 100 MHz tsk(o)‡ 1 ns ns † This information was not available at the time of publication. ‡ Skew between any two outputs of the same package switching in the same direction operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per flip-flop † This information was not available at the time of publication. VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP TYP † † 27 f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF 5 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1k Ω From Output Under Test Open GND CL = 30 pF (see Note A) 1k Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287H – JANUARY 1993 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output 1.5 V 1.5 V tsu Input 1.5 V Input tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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