TI SN75LBC180AD

SLLS378C − MAY 2000 − REVISED JUNE 2002
D High-Speed Low-Power LinBICMOS
Circuitry Designed for Signaling Rates† of
D
D
D
D
D
D
D
D
up to 30 Mbps
Bus-Pin ESD Protection Exceeds 12 kV
HBM
Very Low Disabled Supply-Current
Requirements . . . 700 µA Maximum
Designed for High-Speed Multipoint Data
Transmission Over Long Cables
Common-Mode Voltage Range of
−7 V to 12 V
Low Supply Current . . . 15 mA Max
Compatible With ANSI Standard
TIA/EIA-485-A and ISO 8482:1987(E)
Positive and Negative Output Current
Limiting
Driver Thermal Shutdown Protection
description
The SN65LBC180A and SN75LBC180A
differential driver and receiver pairs are monolithic
integrated circuits designed for bidirectional data
communication over long cables that take on the
characteristics of transmission lines. They are
balanced, or differential, voltage mode devices
that are compatible with ANSI standard
TIA/EIA-485-A and ISO 8482:1987(E). The A
version offers improved switching performance
over its predecessors without sacrificing
significantly more power.
SN65LBC180AD (Marked as BL180A)
SN65LBC180AN (Marked as 65LBC180A)
SN75LBC180AD (Marked as LB180A)
SN75LBC180AN (Marked as 75LBC180A)
(TOP VIEW)
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC −No internal connection
Function Tables
DRIVER
INPUT
D
H
L
X
Open
ENABLE
DE
H
H
L
H
OUTPUTS
Y
Z
H
L
L
H
Z
Z
H
L
RECEIVER
DIFFERENTIAL INPUTS
A −B
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
Open circuit
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
These devices combine a differential line driver and differential input line receiver and operate from a single 5-V
power supply. The driver differential outputs and the receiver differential inputs are connected to separate
terminals for full-duplex operation and are designed to present minimum loading to the bus when powered off
(VCC = 0). These parts feature wide positive and negative common-mode voltage ranges, making them suitable
for point-to-point or multipoint data bus applications. The devices also provide positive and negative current
limiting for protection from line fault conditions. The SN65LBC180A is characterized for operation from −40°C
to 85°C, and the SN75LBC180A is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit duration, and much higher signaling rates may be achieved
without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS378C − MAY 2000 − REVISED JUNE 2002
logic symbol†
DE
4
5
logic diagram (positive logic)
EN1
R
1
10
1
D
RE
9
3
2
12
EN2
11
2
DE
Y
Z
D
A
RE
B
R
4
5
2
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE†
(D)
PLASTIC
DUAL-IN-LINE
(N)
0°C to 70°C
SN75LBC180AD
SN75LBC180AN
−40°C to 85°C
SN65LBC180AD
SN65LBC180AN
† The D package is available taped and reeled. Add an R suffix to the part
number (i.e., SN65LBC180ADR).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10
3
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
9
12
11
Y
Z
A
B
SLLS378C − MAY 2000 − REVISED JUNE 2002
schematics of inputs and outputs
D, DE, and RE Inputs
VCC
100 kΩ
1 kΩ
Input
8V
A Input
B Input
VCC
16 V
100 kΩ
VCC
4 kΩ
4 kΩ
16 V
18 kΩ
Input
18 kΩ
Input
100 kΩ
16 V
16 V
4 kΩ
4 kΩ
Y AND Z Outputs
VCC
R Output
VCC
16 V
40 Ω
Output
Output
8V
16 V
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3
SLLS378C − MAY 2000 − REVISED JUNE 2002
absolute maximum ratings†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Input voltage range, VI (A, B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
Voltage range at D, R, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.5 V
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Electrostatic discharge: Bus terminals and GND, Class 3, A: (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
Bus terminals and GND, Class 3, B: (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . 400 V
All terminals, Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
All terminals, Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND except for differential input or output voltages.
2. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
3. Tested in accordance with MIL−STD−883C, Method 3015.7
PACKAGE
TA ≤ 25°C
POWER RATING
DISSIPATION RATING TABLE
DERATING FACTOR‡
TA = 70°C
ABOVE TA = 25°C
POWER RATING
TA = 85°C
POWER RATING
494 mW
D
950 mW
7.6 mW/°C
608 mW
N
1150 mW
9.2 mW/°C
736 mW
598 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
0.8
V
12
V
12
V
High-level input voltage, VIH
D, DE, and RE
2
Low-level input voltage, VIL
D, DE, and RE
0
−12§
Differential input voltage, VID (see Note 4)
Voltage at any bus terminal (separately or common mode), VO, VI, or VIC
A, B, Y, or Z
Y or Z
High-level output current, IOH
R
−7
−60
60
R
Operating free-air temperature, TA
8
SN65LBC180A
−40
85
SN75LBC180A
0
70
§ The algebraic convention where the least positive (more negative) limit is designated minimum, is used in this data sheet.
NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal with respect to the inverting terminal.
4
POST OFFICE BOX 655303
mA
−8
Y or Z
Low-level output current, IOL
• DALLAS, TEXAS 75265
V
mA
°C
SLLS378C − MAY 2000 − REVISED JUNE 2002
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
TEST CONDITIONS
II = − 18 mA
−1.5
−0.8
1
1.5
3
SN75LBC180A
1.1
1.5
3
RL = 60 Ω,,
See Figure 2
SN65LBC180A
1
1.5
3
SN75LBC180A
1.1
1.5
3
∆| VOD |
Change in magnitude of
differential output voltage
(see Note 5)
VOC(SS)
Steady-state common-mode
output voltage
Change in steady-state
common-mode output voltage
(see Note 5)
See Figure 1
∆ VOC
IO
IIH
Output current with power off
VCC = 0,
VI = 2 V
IIL
IOS
Low-level input current
ICC
See Figures 1 and 2
−0.2
VO = − 7 V to 12 V
V
V
V
2.8
V
−0.1
0.1
V
−10
10
µA
2.4
µA
−100
VI = 0.8 V
−7 V ≤ VO ≤ 12 V
UNIT
0.2
1.8
VI = 0 or VCC,
No load
Supply current
MAX
SN65LBC180A
Differential output voltage
magnitude
Short-circuit output current
TYP†
RL = 54 Ω,,
See Figure 1
| VOD |
High-level input current
MIN
µA
−100
± 70
250
Receiver disabled and
driver enabled
5.5
9
Receiver disabled and
driver disabled
0.5
1
Receiver enabled and driver
enabled
8.5
15
−250
mA
mA
† All typical values are at VCC = 5 V and TA = 25°C.
NOTE 5: ∆ | VOD | and ∆ | VOC | are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the input is changed
from a high level to a low level.
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tr
Pulse skew ( | tPLH − tPHL | )
tf
tPZH
Differential output signal fall time
Propagation delay time, high-impedance-to-high-level output
RL = 110 Ω, See Figure 4
tPZL
tPHZ
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
tPLZ
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-to-low-level output
TYP
MAX
2
6
12
ns
6
12
ns
1
ns
4
7.5
11
ns
4
7.5
11
ns
12
22
ns
RL = 110 Ω, See Figure 5
12
22
ns
RL = 110 Ω, See Figure 4
12
22
ns
RL = 110 Ω, See Figure 5
12
22
ns
• DALLAS, TEXAS 75265
2
UNIT
0.3
RL = 54 Ω,
Ω CL = 50 pF,
See Figure 3
Differential output signal rise time
POST OFFICE BOX 655303
MIN
5
SLLS378C − MAY 2000 − REVISED JUNE 2002
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIT +
Positive-going input threshold
voltage
IO = − 8 mA
VIT −
Negative-going input threshold
voltage
IO = 8 mA
Vhys
VIK
Hysteresis voltage ( VIT + − VIT −)
VOH
VOL
High-level output voltage
II = − 18 mA
VID = 200 mV,
Low-level output voltage
VID = − 200 mV,
High-impedance-state output
current
VO = 0 V to VCC
IOZ
IIH
IIL
Enable-input clamp voltage
High-level enable-input current
Low-level enable-input current
MIN
Bus input current
−0.2
IOH = − 8 mA
IOL = 8 mA
VI = 12 V,
VCC = 0 V
VI = − 7 V,
VCC = 5 V
VI = 0 or VCC,
No load
Supply current
V
mV
−1.5
−0.8
V
4
4.9
V
0.1
−1
VIH = 2.4 V
VIL = 0.4 V
UNIT
V
50
0.8
V
1
µA
−100
µA
−100
µA
0.4
1
0.5
1
Other input at 0 V
mA
VI = − 7 V,
VCC = 0 V
ICC
MAX
0.2
VI = 12 V,
VCC = 5 V
II
TYP†
−0.8
−0.4
−0.8
−0.3
Receiver enabled and driver disabled
4.5
Receiver disabled and driver disabled
0.5
7.5
1
Receiver enabled and driver enabled
8.5
15
mA
† All typical values are at VCC = 5 V and TA = 25°C.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7
13
20
ns
7
13
20
ns
Pulse skew ( tPHL − tPLH  )
0.5
1.5
ns
Output signal rise time
2.1
3.3
ns
2.1
3.3
ns
30
45
ns
30
45
ns
20
40
ns
20
40
ns
tPLH
tPHL
Propagation delay time, low- to high-level output
tsk(p)
tr
tf
tPZH
tPZL
Output enable time to high level
Output enable time to low level
tPHZ
tPLZ
Output disable time from high level
6
Propagation delay time, high- to low-level output
Output signal fall time
VID = −1.5 V to 1.5 V,
See Figure 7
See Figure 7
CL = 10 pF,
Output disable time from low level
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
See Figure 8
UNIT
SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
Vtest
R1
375 Ω
27 Ω
Y
VOD
0 or 3 V
D
27 Ω VOC
RL = 60 Ω
0 V or 3 V
VOD
Z
Figure 1. Driver VOD and VOC
R2
375 Ω
−7 V < Vtest < 12 V
Vtest
Figure 2. Driver VOD
3V
Input
Generator
(see Note A)
RL = 54 Ω
50 Ω
1.5 V
CL = 50 pF
(see Note B)
0V
tPLH
VO
Output
3V
1.5 V
tPHL
90%
50%
≈ 1.5 V
10%
≈ − 1.5 V
tf
VOLTAGE WAVEFORMS
tr
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3V
S1
Input
1.5 V
1.5 V
3V
Generator
(see Note A)
50 Ω
CL = 50 pF
(see Note B)
tPZH
RL = 110 Ω
0V
0.5 V
VOH
Output
TEST CIRCUIT
2.3 V
tPHZ
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
5V
S1
3V
RL = 110 Ω
1.5 V
1.5 V
0V
Output
0V
Generator
(see Note A)
Input
tPZL
tPLZ
CL = 50 pF
(see Note B)
50 Ω
5V
0.5 V
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
IO
VID
VO
Figure 6. Receiver VOH and VOL
3V
Input
Input
Generator
(see Note A)
1.5 V
1.5 V
Output
50 Ω
1.5 V
CL = 10 pF
(see Note B)
0V
tPLH
VOH
90%
Output
0V
tPHL
1.3 V
10%
1.3 V
tr
TEST CIRCUIT
VOL
tf
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
2 kΩ
−1.5 V
S2
5V
CL = 10 pF
(see Note B)
Input
Generator
(see Note A)
5 kΩ
50 Ω
S3
TEST CIRCUIT
Input
1.5 V
3V
S1 to 1.5 V
S2 Open
S3 Closed
0V
Input
1.5 V
tPZH
3V
S1 to −1.5 V
S2 Closed
S3 Open
0V
tPZL
VOH
≈ 4.5 V
1.5 V
Output
Output
1.5 V
0V
VOL
1.5 V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
0V
Input
tPHZ
3V
S1 to −1.5 V
S2 Closed
S3 Closed
0V
1.5 V
tPLZ
≈ 1.3 V
VOH
Output
0.5 V
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 8. Receiver Output Enable and Disable Times
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
Receiver Output
Driver Input
120 Ω
120 Ω
Driver Input
Receiver Output
Figure 9. Typical Waveform of Nonreturn-to-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at
100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable
TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition
of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length
perform quite well even though they do not meet the standard by definition.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
LOGIC INPUT CURRENT
vs
INPUT VOLTAGE
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
40
−30
I I − Logic Input Current − µ A
I CC − Average Supply Current − mA
VCC = 5 V
TA = 25°C
Driver
35
RL = 54 Ω
CL = 50 pF
30
25
VCC = 5 V
TA = 25°C
50% Duty Cycle
20
15
10
Receiver
CL = 10 pF
5
0
0.05
0.5
1
2
−25
−20
−15
−10
−5
5
10
20
0
30
0
1
2
f − Frequency − MHz
Figure 10
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Driver Low-Level Output Voltage − V
I I − Bus Input Current − µ A
800
VCC = 5 V
TA = 25°C
400
200
0
−200
−400
−600
−8
5
Figure 11
BUS INPUT CURRENT
vs
INPUT VOLTAGE
600
4
3
VI − Input Voltage − V
2
VCC = 5 V
TA = 25°C
1.75
1.50
1.25
1
0.75
0.50
0.25
−6
−4
−2
0
2
4
6
8
10
12
VI − Input Voltage − V
0
0
10
20
30
40
50
60
70
80
IOL − Low-Level Output Current − mA
Figure 13
Figure 12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
CASE TEMPERATURE
5
14
TA = 25°C
4.5
Receiver
13
4
VCC = 5.25 V
Propagation Delay Time − ns
VOH − Driver High-Level Output Voltage − V
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3
2.5
VCC = 5 V
2
VCC = 4.75 V
1.5
1
0.5
0
12
11
10
VCC = 5 V
Driver Tested Per Figure 3
Receiver Tested Per Figure 7
Square Wave Input at 50%
Duty Cycle
9
8
7
6
0
−10
−20
−30
−40
−50
−60
−70
−80
5
−50
I OH − High-Level Output Current − mA
0
50
Case Temperature − ° C
Figure 15
Figure 14
12
Driver
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
SLLS378C − MAY 2000 − REVISED JUNE 2002
APPLICATION INFORMATION
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
RT
RT
Up to 32
Unit Loads
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible. One SN65LBC180A typically represents less than one unit load.
Figure 16. Typical Application Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLLS378C − MAY 2000 − REVISED JUNE 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
14
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS378C − MAY 2000 − REVISED JUNE 2002
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.035 (0,89) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
0°−ā 15°
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LBC180AD
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LBC180ADR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LBC180AN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN75LBC180AD
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN75LBC180ADR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN75LBC180AN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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