SLLS500A − MAY 2001 − REVISED MARCH 2005
FEATURES
D One-Fourth Unit Load Allows up to 128
D
D
D
D
D
D
D
D
D
Devices on a Bus
ESD Protection for Bus Terminals:
− ±15-kV Human Body Model
− ±8-kV IEC61000-4-2, Contact Discharge
− ±15-kV IEC61000-4-2, Air-Gap Discharge
Meets or Exceeds the Requirements of ANSI
Standard TIA/EIA-485-A and ISO 8482: 1987(E)
Controlled Driver Output-Voltage Slew Rates
Allow Longer Cable Stub Lengths
Designed for Signaling Rates† Up to 250-kbps
Low Disabled Supply Current . . . 250 µA Max
Thermal Shutdown Protection
Open-Circuit Fail-Safe Receiver Design
Receiver Input Hysteresis . . . 70 mV Typ
Glitch-Free Power-Up and Power-Down
Protection
APPLICATIONS
D Utility Meters
D Industrial Process Control
D Building Automation
DESCRIPTION
The SN65LBC182 and SN75LBC182 are differential
data line transceivers with a high level of ESD protection
in the trade-standard footprint of the SN75176. They are
designed for balanced transmission lines and meet
ANSI standard TIA/EIA-485-A and ISO 8482. The
SN65LBC182 and SN75LBC182 combine a 3-state,
differential line driver and differential input line receiver,
both of which operate from a single 5-V power supply.
The driver and receiver have active-high and active-low
enables, respectively, which can be externally
connected together to function as a direction control.
The driver outputs and the receiver inputs connect
internally to form a differential input/output (I/O) bus port
that is designed to offer minimum loading to the bus.
This port operates over a wide range of common-mode
voltage, making the device suitable for party-line
applications. The device also includes additional
features for party-line data buses in electrically noisy
environment applications such as industrial process
control or power inverters.
The SN75LBC182 and SN65LBC182 bus pins also
exhibit a high input resistance equivalent to one-fourth
unit load allowing connection of up to 128 similar
devices on the bus. The high ESD tolerance protects
the device for cabled connections. (For an even higher
level of protection, see the SN65/75LBC184, literature
number SLLS236.)
The
differential
driver
design
incorporates
slew-rate-controlled outputs sufficient to transmit data
up to 250 kbps. Slew-rate control allows longer
unterminated cable runs and longer stub lengths from
the main backbone than possible with uncontrolled
voltage transitions. The receiver design provides a
fail-safe output of a high level when the inputs are left
floating (open circuit). Very low device supply current
can be achieved by disabling the driver and the receiver.
The SN65LBC182 is characterized for operation from
−40°C to 85°C, and the SN75LBC182 is characterized
for operation from 0°C to 70°C.
functional block diagram
DE
D
RE
R
3
6
4
7
2
A
B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
Copyright 2001, Texas Instruments Incorporated
www.ti.com
1
SLLS500A − MAY 2001 − REVISED MARCH 2005
schematic of inputs and outputs
SN65LBC182D (Marked as 6LB182)
SN75LBC182D (Marked as 7LB182)
SN65LBC182P (Marked as 65LBC182)
SN75LBC182P (Marked as 75LBC182)
(TOP VIEW)
R
RE
DE
D
1
2
8
3
7
6
4
5
VCC
VCC
B
A
GND
A Port
Only
16 kΩ
12 µA
Nominal
72 kΩ
A or B
I/O
16 kΩ
B Port
Only
12 µA
Nominal
Function Tables
DRIVER
INPUT
D
ENABLE
DE
H
H
OUTPUTS
A
B
H
L
L
H
L
H
X
L
Z
Z
Open
H
H
L
RECEIVER
DIFFERENTIAL
INPUTS
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
-0.2V < VID < 0.2 V
VID ≤ -0.2 V
X
Open
L
L
L
H
L
H
?
L
Z
H
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC SMALL-OUTLINE†
(JEDEC MS-012)
PLASTIC DUAL-IN-LINE PACKAGE
(JEDEC MS-001)
0°C to 70°C
SN75LBC182D
SN75LBC182P
−40°C to 85°C
SN65LBC182D
SN65LBC182P
† Add R suffix for taped and reel.
† For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
2
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SLLS500A − MAY 2001 − REVISED MARCH 2005
absolute maximum ratings† over operating free−air temperature range unless otherwise noted
Supply voltage range, (see Note 1) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V
Input voltage, VI (D, DE, R or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Electrostatic discharge: Human body model (see Note 2)
A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
Contact discharge (IEC61000-4-2)
A, B, GND . . . . . . . . . . . . . . . . . . . . . . . 8 kV
Air discharge (IEC61000-4-2)
A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
P
1150 mW
9.2 mW/°C
736 mW
PACKAGE
598 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
NOTE: The maximum operating junction temperature is internally limited. Use the dissipation rating table
to operate below this temperature
recommended operating conditions
Supply voltage, VCC
Voltage at any bus I/O terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
Low-level input voltage, VIL
MAX
UNIT
5
5.25
V
12
V
−7
D, DE, RE
0.8
−12
12
−60
60
−8
4
SN65LBC182
−40
85
SN75LBC182
0
70
Driver
Operating free-air temperature, TA
NOM
2
Differential input voltage, VID (see Note 3)
Output current, IO
MIN
4.75
Receiver
V
V
mA
°C
NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
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3
SLLS500A − MAY 2001 − REVISED MARCH 2005
driver electrical characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
VIK
VO
Input clamp voltage
|VOD|
Differential output voltage
∆VOD
VOC(SS)
Change in magnitude of differential output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage
VOC(PP)
II = −18 mA
IO = 0
Output voltage
Peak-to-peak change in common-mode output
voltage during state transitions
MAX
VCC
VCC
V
V
−0.2
VCC
0.2
1
3
−0.2
0.2
V
0
See Figure 1
1.5
2.2
See Figure 2
1.5
2.2
See Figure 1
V
V
See Figures 1 and 4
0.8
IOZ
IIH
High-impedance output current
See receiver input currents
High-level input current (D, DE)
IIL
IOS
Low-level input current (D, DE)
VI = 2.4 V
VI = 0.4 V
Short-circuit output current
VO = −7 V to 12 V
ICC
Supply current
V
50
µA
250
mA
µA
−50
−250
SN75LBC182
SN65LBC182
UNIT
−1.5
RL = 54 Ω,
Vtest = −7 V to 12 V,
Steady-state common-mode output voltage
TYP†
MIN
No load, DE at VCC,
RE at VCC
12
25
12
30
mA
† All typical values are at VCC = 5 V and TA = 25°C.
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tr
tf
Differential output signal rise time
0.25
0.72
1.2
Differential output signal fall time
0.25
0.73
1.2
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tPZH
Pulse skew (tPHL − tPLH)
tPHZ
tPZL
Output disable time from high level
tPLZ
Output disable time from low level
4
RL = 54 Ω,
See Figure 3
CL = 50 pF,
1.3
Propagation delay time, high-to-low-level output
Output enable time to high level
Output enable time to low level
UNIT
µs
1.3
0.075
3.5
RL = 110 Ω,
See Figure 5
RL = 110 Ω,
See Figure 6
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0.15
3.5
3.5
3.5
µss
µss
SLLS500A − MAY 2001 − REVISED MARCH 2005
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
VIT+
VIT−
Positive-going input threshold voltage
Vhys
VIK
Hysteresis voltage (VIT+ − VIT-)
VOH
VOL
High-level output voltage
IOZ
High-impedance-state output current
TEST CONDITIONS
Low-level output voltage
TYP†
70
II = −18 mA
VID = 200 mV, IO = −8 mA,
VID = 200 mV, IO = 4 mA,
VO = 0.4 to 2.4 V
VIH = 12 V, VCC = 5 V
VIH = 12 V, VCC = 0 V
VIH = −7 V, VCC = 5 V
Bus input current
IIH
IIL
High-level input current (RE)
VIH = −7 V, VCC = 0 V
VIH = 2 V
Low-level input current (RE)
VIL = 0.8 V
mV
−1.5
See Figure 7
V
2.8
V
See Figure 7
0.4
V
±1
µA
250
250
Other input at 0 V
−200
A
µA
−200
50
µA
3.5
mA
250
µA
µA
−50
DE at 0 V, RE at 0 V
Supply current
UNIT
V
−0.2
II
ICC
MAX
0.2
Negative-going input threshold voltage
Enable-input clamp voltage
MIN
No load
DE at 0 V, RE at VCC
175
† All typical values are at VCC = 5 V and TA = 25°C.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tr
tf
Differential output signal rise time
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
150
tPZH
tPZL
Output enable time to high level
100
tPHZ
tPLZ
Output disable time from high level
tsk(p)
Pulse skew tPHL − tPLH
Differential output signal fall time
Output enable time to low level
UNIT
20
20
CL = 50 pF,
See Figure 8
Output disable time from low level
See Figure 7
150
100
100
100
50
www.ti.com
ns
ns
ns
ns
5
SLLS500A − MAY 2001 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
IO
27 Ω
II
0 V or 3 V
IO
VO
50 pF†
VOD
27 Ω
VOC
VO
†Includes probe and jig capacitance
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
VOD
Input
60 Ω
VTEST = −7 V to 12 V
375 Ω
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V
RL = 54 Ω
Signal
Generator{
Input
CL = 50 pF}
1.5 V
1.5 V
0V
VOD
tPLH
50 Ω
Output
tPHL
90% 90%
10%
10%
tr
†PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡Includes probe and jig capacitance
tf
Figure 3. Driver Switching Test Circuit and Waveforms
VOC
VOC(PP)
∆VOC(SS)
Figure 4. VOC Definitions
6
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VOD(H)
0V
VOD(L)
SLLS500A − MAY 2001 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
Output
3V
S1
Input
1.5 V
1.5 V
0 or 3 V
Generator
(see Note A)
RL = 110 Ω
CL = 50 pF
(see Note B)
0V
0.5 V
tPZH
VOH
50 Ω
Output
2.3 V
tPHZ
TEST CIRCUIT
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms
5V
3V
Input
RL = 110 Ω
S1
1.5 V
0V
Output
0 or 3 V
Generator
(see Note A)
1.5 V
tPZL
tPLZ
CL = 50 pF
(see Note B)
50 Ω
2.3 V
Output
5V
0.5 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms
II
A
VID
Input
VI
B
1.5 V
Inputs
RE
50%
VO
50 pF
(see Note A)
Output
3V
1.5 V
0V
50%
tPLH
Output
IO
R
tPHL
90%
90%
10%
10%
tr
NOTE A: This value includes probe and jig capacitance (± 10%).
VOH
50%
VOL
tf
Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms
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7
SLLS500A − MAY 2001 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
5V
A
620 Ω
0 V or 3 V
R
1.5 V
B
620 Ω
50 pF
(see Note A)
RE
VO
Input
3V
A
0V
3V
Inputs
RE
3V
1.5 V
0V
tPHZ
Output
VO
tPZH
0.5 V
0V
tPLZ
0.5 V
tPZL
∼ 2.5 V
VOH
∼ 2.5 V
0.5 V
0.5 V
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms
8
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VOL
SLLS500A − MAY 2001 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
TEMPERATURE
DRIVER PROPAGATION DELAY TIME
vs
TEMPERATURE
800
RL = 54 Ω
2.5
tpd − Driver Propagation Delay Time − ns
VOD − Driver Differential Output Voltage − V
3.0
VCC = 5.25 V
VCC = 5 V
2.0
VCC = 4.75 V
1.5
1.0
−40
−20
0
20
40
60
780
760
tPHL
740
720
tPLH
700
680
660
640
−40
80
TA − Free-Air Temperature − °C
−20
DRIVER TRANSITION TIME
vs
TEMPERATURE
40
60
80
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
900
4.5
4.0
VOD − Differential Output Voltage − V
800
tt − Driver Transition Time − ns
20
Figure 10
Figure 9
tf
700
tr
600
500
400
300
−40
0
TA − Free-Air Temperature − °C
−20
0
20
40
60
3.5
3.0
VCC = 5.5 V
2.5
VCC = 4.5 V
2.0
1.5
VCC = 5 V
1.0
0.5
0.0
80
0
TA − Free-Air Temperature − °C
10
20
30
40
50
60
70
80
90 100
IO − Output Current − mA
Figure 11
Figure 12
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9
SLLS500A − MAY 2001 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
RECEIVER INPUT CURRENT
vs
INPUT VOLTAGE
0.25
I(I) − Receiver Input Current − mA
0.20
0.15
0.10
0.05
−0.00
A, B (VCC = 0 V)
−0.05
B (VCC = 5 V)
−0.10
A (VCC = 5 V)
−0.15
−0.20
−10
−5
0
5
10
15
VI − Input Voltage − V
Figure 13
APPLICATION INFORMATION
SN65LBC182
SN75LBC182
SN65LBC182
SN75LBC182
RT
RT
Up to 128
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 14. Typical Application Circuit
10
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LBC182D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC182DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC182DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC182DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC182P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65LBC182PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LBC182D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC182DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC182DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC182DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC182P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LBC182PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
20-Jun-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LBC182DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
SN65LBC182DR
D
8
FMX
330
0
6.4
5.2
2.1
8
12
Q1
SN75LBC182DR
D
8
TAI
330
12
6.4
5.2
2.1
8
12
Q1
SN75LBC182DR
D
8
FMX
330
0
6.4
5.2
2.1
8
12
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65LBC182DR
D
8
TAI
346.0
346.0
29.0
SN65LBC182DR
D
8
FMX
342.9
336.6
20.64
SN75LBC182DR
D
8
TAI
346.0
346.0
29.0
SN75LBC182DR
D
8
FMX
342.9
336.6
20.64
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jun-2007
Pack Materials-Page 3
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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