SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
SN8F2250B Series
USER’S MANUAL
SN8F2251B
SN8F22511B
SN8F22521B
SN8F2253B
SN8F22531B
SN8F2255B
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Page 1
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
AMENDMENT HISTORY
Version
VER1.0
VER1.1
Date
2009/3/14
2009/5/11
Description
version 1.0
Modify wakeup time’s description
SONiX TECHNOLOGY CO., LTD
Page 2
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
Table of Content
AMENDMENT HISTORY .............................................................................................................. 2
1
PRODUCT OVERVIEW ............................................................................................................ 7
1.1 FEATURES ............................................................................................................................. 7
1.2 SYSTEM BLOCK DIAGRAM ................................................................................................... 8
1.3 PIN ASSIGNMENT.................................................................................................................. 9
1.4 PIN DESCRIPTIONS............................................................................................................. 11
1.5 PIN CIRCUIT DIAGRAMS ..................................................................................................... 12
2
CENTRAL PROCESSOR UNIT (CPU) ................................................................................... 13
2.1 MEMORY MAP ..................................................................................................................... 13
2.1.1 PROGRAM MEMORY (ROM) ........................................................................................ 13
2.1.1.1 RESET VECTOR (0000H) ....................................................................................... 14
2.1.1.2 INTERRUPT VECTOR (0008H)............................................................................... 15
2.1.1.3 LOOK-UP TABLE DESCRIPTION ........................................................................... 17
2.1.1.4 JUMP TABLE DESCRIPTION ................................................................................. 19
2.1.1.5 CHECKSUM CALCULATION .................................................................................. 21
2.1.2 CODE OPTION TABLE .................................................................................................. 22
2.1.3 DATA MEMORY (RAM) ................................................................................................. 23
2.1.4 SYSTEM REGISTER ..................................................................................................... 24
2.1.4.1 SYSTEM REGISTER TABLE................................................................................... 24
2.1.4.2 SYSTEM REGISTER DESCRIPTION ..................................................................... 24
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER ............................................................... 25
2.1.4.4 ACCUMULATOR ..................................................................................................... 27
2.1.4.5 PROGRAM FLAG .................................................................................................... 28
2.1.4.6 PROGRAM COUNTER............................................................................................ 29
2.1.4.7 Y, Z REGISTERS..................................................................................................... 32
2.1.4.8 R REGISTERS......................................................................................................... 33
2.2 ADDRESSING MODE ........................................................................................................... 34
2.2.1 IMMEDIATE ADDRESSING MODE ............................................................................... 34
2.2.2 DIRECTLY ADDRESSING MODE ................................................................................. 34
2.2.3 INDIRECTLY ADDRESSING MODE.............................................................................. 34
2.3 STACK OPERATION ............................................................................................................ 35
2.3.1 OVERVIEW .................................................................................................................... 35
2.3.2 STACK REGISTERS...................................................................................................... 36
2.3.3 STACK OPERATION EXAMPLE.................................................................................... 37
3
RESET .................................................................................................................................... 38
3.1 OVERVIEW........................................................................................................................... 38
3.2 POWER ON RESET.............................................................................................................. 39
3.3 WATCHDOG RESET ............................................................................................................ 39
3.4 BROWN OUT RESET ........................................................................................................... 40
3.4.1 BROWN OUT DESCRIPTION........................................................................................ 40
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............................................... 41
3.4.3 BROWN OUT RESET IMPROVEMENT......................................................................... 42
3.5 EXTERNAL RESET............................................................................................................... 43
3.6 EXTERNAL RESET CIRCUIT ............................................................................................... 43
3.6.1 Simply RC Reset Circuit ................................................................................................. 43
SONiX TECHNOLOGY CO., LTD
Page 3
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
3.6.2 Diode & RC Reset Circuit ............................................................................................... 44
3.6.3 Zener Diode Reset Circuit .............................................................................................. 44
3.6.4 Voltage Bias Reset Circuit.............................................................................................. 45
3.6.5 External Reset IC ........................................................................................................... 45
4
SYSTEM CLOCK .................................................................................................................... 46
4.1 OVERVIEW........................................................................................................................... 46
4.2 CLOCK BLOCK DIAGRAM ................................................................................................... 46
4.3 OSCM REGISTER ................................................................................................................ 47
4.4 SYSTEM HIGH CLOCK......................................................................................................... 48
4.4.1 EXTERNAL HIGH CLOCK ............................................................................................. 48
4.4.1.1 CRYSTAL/CERAMIC............................................................................................... 49
4.1.1.2 EXTERNAL CLOCK SIGNAL................................................................................... 50
4.2 SYSTEM LOW CLOCK ......................................................................................................... 51
4.2.1 SYSTEM CLOCK MEASUREMENT............................................................................... 51
5
SYSTEM OPERATION MODE................................................................................................ 52
5.1 OVERVIEW........................................................................................................................... 52
5.2 SYSTEM MODE SWITCHING EXAMPLE ............................................................................. 53
5.3 WAKEUP............................................................................................................................... 55
5.3.1 OVERVIEW .................................................................................................................... 55
5.3.2 WAKEUP TIME .............................................................................................................. 55
6
INTERRUPT............................................................................................................................ 56
6.1 OVERVIEW........................................................................................................................... 56
6.2 INTEN INTERRUPT ENABLE REGISTER ............................................................................ 57
6.3 INTRQ INTERRUPT REQUEST REGISTER......................................................................... 58
6.4 GIE GLOBAL INTERRUPT OPERATION.............................................................................. 59
6.5 PUSH, POP ROUTINE .......................................................................................................... 59
6.6 INT0 (P0.0) & INT1 (P0.1) INTERRUPT OPERATION........................................................... 60
6.7 T0 INTERRUPT OPERATION............................................................................................... 62
6.8 T1 INTERRUPT OPERATION............................................................................................... 63
6.9 TC0 INTERRUPT OPERATION ............................................................................................ 64
6.10 TC1 INTERRUPT OPERATION .......................................................................................... 65
6.11 USB INTERRUPT OPERATION.......................................................................................... 66
6.12 WAKEUP INTERRUPT OPERATION.................................................................................. 67
6.13 SIO INTERRUPT OPERATION ........................................................................................... 68
6.14 MULTI-INTERRUPT OPERATION ...................................................................................... 69
7
I/O PORT................................................................................................................................. 70
7.1 I/O PORT MODE ................................................................................................................... 70
7.2 I/O PULL UP REGISTER....................................................................................................... 71
7.3 I/O PORT DATA REGISTER ................................................................................................. 72
7.4 I/O PORT1 WAKEUP CONTROL REGISTER ....................................................................... 73
8
TIMERS................................................................................................................................... 74
8.1 WATCHDOG TIMER ............................................................................................................. 74
8.2 TIMER 0 (T0)......................................................................................................................... 76
8.2.1 OVERVIEW .................................................................................................................... 76
8.2.2 T0M MODE REGISTER ................................................................................................. 76
8.2.3 T0C COUNTING REGISTER ......................................................................................... 77
8.2.4 T0 TIMER OPERATION SEQUENCE ............................................................................ 78
SONiX TECHNOLOGY CO., LTD
Page 4
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.3 TIMER T1 (T1)....................................................................................................................... 79
8.3.1 OVERVIEW .................................................................................................................... 79
8.3.2 T1M MODE REGISTER ................................................................................................. 79
8.3.3 T1C COUNTING REGISTER ......................................................................................... 80
8.3.4 T1 TIMER OPERATION SEQUENCE ............................................................................ 81
8.4 TIMER/COUNTER 0 (TC0).................................................................................................... 82
8.4.1 OVERVIEW .................................................................................................................... 82
8.4.2 TC0M MODE REGISTER............................................................................................... 83
8.4.3 TC0C COUNTING REGISTER....................................................................................... 84
8.4.4 TC0R AUTO-LOAD REGISTER ..................................................................................... 85
8.4.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)........................................................... 86
8.4.6 TC0 TIMER OPERATION SEQUENCE ......................................................................... 87
8.5 PWM0 MODE........................................................................................................................ 88
8.5.1 OVERVIEW .................................................................................................................... 88
8.5.2 TCxIRQ and PWM Duty ................................................................................................. 89
8.5.3 PWM Duty with TCxR Changing..................................................................................... 90
8.5.4 PWM PROGRAM EXAMPLE ......................................................................................... 91
8.6 TIMER/COUNTER 1 (TC1).................................................................................................... 92
8.6.1 OVERVIEW .................................................................................................................... 92
8.6.2 TC1M MODE REGISTER............................................................................................... 93
8.6.3 TC1C COUNTING REGISTER....................................................................................... 94
8.6.4 TC1R AUTO-LOAD REGISTER ..................................................................................... 95
8.6.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)........................................................... 96
8.6.6 TC1 TIMER OPERATION SEQUENCE ......................................................................... 97
8.7 PWM1 MODE........................................................................................................................ 98
8.7.1 OVERVIEW .................................................................................................................... 98
8.7.2 TCxIRQ and PWM Duty ................................................................................................. 99
8.7.3 PWM Duty with TCxR Changing................................................................................... 100
8.7.4 PWM PROGRAM EXAMPLE ....................................................................................... 101
9
UNIVERSAL SERIAL BUS (USB) ........................................................................................ 102
9.1 OVERVIEW......................................................................................................................... 102
9.2 USB MACHINE ................................................................................................................... 102
9.3 USB INTERRUPT................................................................................................................ 102
9.4 USB ENUMERATION.......................................................................................................... 103
9.5 USB REGISTERS ............................................................................................................... 104
9.5.1 USB DEVICE ADDRESS REGISTER .......................................................................... 104
9.5.2 USB STATUS REGISTER............................................................................................ 104
9.5.3 USB DATA COUNT REGISTER................................................................................... 105
9.5.4 USB ENABLE CONTROL REGISTER ......................................................................... 105
9.5.5 USB endpoint’s ACK handshaking flag REGISTER ..................................................... 105
9.5.6 USB endpoint’s NAK handshaking flag REGISTER ..................................................... 106
9.5.7 USB ENDPOINT 0 ENABLE REGISTER ..................................................................... 106
9.5.8 USB ENDPOINT 1 ENABLE REGISTER ..................................................................... 107
9.5.9 USB ENDPOINT 2 ENABLE REGISTER ..................................................................... 107
9.5.10 USB ENDPOINT 3 ENABLE REGISTER ................................................................... 108
9.5.11 USB DATA POINTER REGISTER ............................................................................. 108
9.5.12 USB DATA READ/WRITE REGISTER....................................................................... 108
9.5.13 USB ENDPOINT OUT TOKEN DATA BYTES COUNTER......................................... 109
9.5.14 UPID REGISTER........................................................................................................ 109
9.5.15 ENDPOINT TOGGLE BIT CONTROL REGISTER..................................................... 109
SONiX TECHNOLOGY CO., LTD
Page 5
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
10
SERIAL INPUT/OUTPUT TRANSCEIVER........................................................................ 110
10.1 OVERVIEW....................................................................................................................... 110
10.2 SIOM MODE REGISTER .................................................................................................. 113
10.3 SIOB DATA BUFFER ........................................................................................................ 114
10.4 SIOR REGISTER DESCRIPTION ..................................................................................... 114
11
FLASH............................................................................................................................... 115
11.1 OVERVIEW....................................................................................................................... 115
11.2 FLASH PROGRAMMING/ERASE CONTROL REGISTER................................................ 115
11.3 PROGRAMMING/ERASE ADDRESS REGISTER ............................................................ 116
11.4 PROGRAMMING/ERASE DATA REGISTER.................................................................... 117
11.4.1 FLASH IN-SYSTEM-PROGRAMMING MAPPING ADDRESS ......................................................... 117
12
INSTRUCTION TABLE ..................................................................................................... 118
13
DEVELOPMENT TOOL..................................................................................................... 119
13.1
13.2
13.3
14
14.1
14.2
ICE (IN CIRCUIT EMULATION) ............................................................................................ 119
SN8F2250 EV-KIT ........................................................................................................... 120
SN8F2250 TRANSITION BOARD ........................................................................................ 120
ELECTRICAL CHARACTERISTIC ................................................................................... 121
ABSOLUTE MAXIMUM RATING.................................................................................... 121
ELECTRICAL CHARACTERISTIC ................................................................................. 121
15
FLASH ROM PROGRAMMING PIN.................................................................................. 122
16
PACKAGE INFORMATION............................................................................................... 124
16.1
16.2
16.3
16.4
16.5
16.6
16.7
17
17.1
17.2
17.3
17.4
LQFP32 PIN ................................................................................................................... 124
SOP 24 PIN .................................................................................................................... 125
SOP 20 PIN .................................................................................................................... 125
SSOP 20 PIN.................................................................................................................. 127
QFN 24 PIN .................................................................................................................... 128
QFN 16 PIN .................................................................................................................... 129
SSOP 16 PIN.................................................................................................................. 130
MARKING DEFINITION .................................................................................................... 131
INTRODUCTION............................................................................................................ 131
MARKING INDETIFICATION SYSTEM.......................................................................... 131
MARKING EXAMPLE..................................................................................................... 132
DATECODE SYSTEM .................................................................................................. 132
SONiX TECHNOLOGY CO., LTD
Page 6
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
1
PRODUCT OVERVIEW
1.1 FEATURES
♦
Memory configuration
Flash ROM size: 10K x 16 bits, including in
system programming function.
20000 erase/write cycles.
RAM size: 512 x 8 bits.
♦
♦
8 levels stack buffer
♦
One SIO function for data transfer
(Serial Peripheral Interface)
♦
I/O pin configuration
Bi-directional: P0, P1, P2, P5
Wake-up: P0/P1 level change.
Pull-up resistors: P0, P1, P2, P5.
External interrupt: P0.0, P0.1 controlled by
PEDGE.
♦
One 16-bit timer counters. (T1)
♦
Three 8 bits timer counter (T0, TC0, TC1)
TC0, TC1. Each has 8 bit PWM function (duty/cycle
programmable).
♦
Two system clocks.
Internal low clock: RC type 24KHz which Fosc =
24KHz.
External X’tal: 6MHz/12MHz/16MHz X’tal which the
Fosc will be 12MHz.
♦
Four operating modes.
Normal mode: Both high and low clocks active.
Slow mode: Low clock only.
Sleep: Both high and low clocks stop.
Green mode: Periodical wakeup by timer.
♦
Package
QFN16, SSOP16,SOP20, SSOP20, SOP24, QFN24,
LQFP32
♦
On chip watchdog timer.
♦
In-system re-programmability
Allows easy firmware update
♦
Full Speed USB 2.0
Seven internal interrupts: T0, T1, TC0, TC1, USB,
SIO, Wakeup
Two external interrupt: INT0, INT1.
Conforms to USB specification, Version 2.0.
3.3V regulator output for USB D+ pin internal
1.5k ohm pull-up resistor.
Integrated USB transceiver.
Supports 1 Full speed USB device address,
1 control endpoint
3 interrupt IN/OUT endpoints, each has 16 bytes
FIFO
♦
)
Powerful instructions
One clocks per instruction cycle (1T)
Most of instructions are one cycle only.
All ROM area JMP instruction.
All ROM area CALL address instruction.
All ROM area lookup table function (MOVC)
9 interrupt sources.
Features Selection Table
CHIP
ROM RAM STACK
SN8F2251B 10K*16 512*8
SN8F22511B 10K*16 512*8
SN8F22521B 10K*16 512*8
SN8F2253B 10K*16 512*8
SN8F22531B 10K*16 512*8
SN8F2255B 10K*16 512*8
8
8
8
8
8
8
SONiX TECHNOLOGY CO., LTD
TIMER
WAKE-UP
SIO PWM
PIN NO.
T0 T1 TC0 TC1
V V
V
V
V
V
3
V V
V
V
V
V
3
V V
V
V
V
V
5
V V
V
V
V
V
7
V V
V
V
V
V
7
V V
V
V
V
V
13
Page 7
I/O
pin
8
8
12
16
16
24
PACKAGE
QFN
SSOP
SOP/SSOP
SOP
QFN
LQFP
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
1.2 SYSTEM BLOCK DIAGRAM
6MHz/12MHz/16MHz
PC
LVD
Oscillator
Flash
memory
IR
Internal
Low RC
P LL
WATCHDOG TIMER
FLAGS
3.3v REGULATOR
TIMING GENERATOR
2.5v REGULATOR
VREG33
VREG25
ALU
D+
RAM
Full speed USB SIE
D-
ACC
SYSTEM REGISTERS
INTERRUPT
CONTROL
P0
TIMER & COUNTER
P1
SONiX TECHNOLOGY CO., LTD
P2
SIO
PWM
BUZZER
P5
Page 8
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
1.3 PIN ASSIGNMENT
P5.1/SDI
P5.0/SCK
12 P5.2/SDO
11 VDD
10 P2.0
9 P2.1
VREG33
DN
DP
16 15 14 13
1 ●
2
F2251BJ
3
4
5 6 7 8
VSS
P0.1/INT1
XIN
XOUT
VREG25
P1.0
P1.1
SN8F2251BJ (QFN 16 pins)
SN8F22511BX (SSOP 16 pins)
P5.0/SCK
P5.2/SDO
P5.1/SDI
P1.0
P1.1
P0.1/INT1
XIN
XOUT
1
U
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SN8F22511BX
P2.1
P2.0
VDD
VREG33
DN
DP
VSS
VREG25
P5.0/SCK
P5.2/SDO
P5.1/SDI
P5.3/PWM1
P5.4/PWM0
P1.0
P1.1
P0.0/INT0
P0.1/INT1
P0.4/RST
1
U
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SN8F22521BS
SN8F22521BX
P2.1
P2.0
VDD
VREG33
DN
DP
VSS
VREG25
XOUT
XIN
SN8F22521BS (SOP 20 pins)
SN8F22521BX (SSOP 20 pins)
SONiX TECHNOLOGY CO., LTD
Page 9
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
SN8F2253BS (SOP 24 pins)
P5.0/SCK
P5.2/SDO
P5.1/SDI
P5.3/PWM1
P5.4/PWM0
P1.0
P1.1
P1.2
P1.3
P0.0/INT0
P0.1/INT1
P0.4/RST
1
U
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
SN8F2253BS
P2.3
P2.2
P2.1
P2.0
VDD
VREG33
DN
DP
VSS
VREG25
XOUT
XIN
VSS
DP
DN
VREG33
18 VREG25
17 XOUT
16 XIN
15 P0.4/RST
14 P0.1/INT1
13 P0.0/INT0
P1.3
P1.2
P1.1
P1.0
P5.4/PWM0
24 23 22 21 20 19
1 ●
2
3
SN8F22531BJ
4
5
6
7 8 9 10 11 12
P5.3/PWM1
P2.1
P2.2
P2.3
P5.0/SCK
P5.2/SDO
P5.1/SDI
VDD
P2.0
SN8F22531BJ (QFN 24 pins)
SONiX TECHNOLOGY CO., LTD
P5.4/PWM0
P1.0
P1.1
P1.2
P1.3
P1.4
Page 10
P2.1
P2.0
VDD
VREG33
DN
DP
VSS
32 31 30 29 28 27 26 25
1 ●
24 P5.3/PWM1
2
23 P5.1/SDI
3
22 P5.2/SDO
4
21 P5.0/SCK
SN8F2255BF
5
20 P2.5
6
19 P2.4
7
18 P2.3
8
17 P2.2
9 10 11 12 13 14 15 16
VREG25
P1.7
P0.0/INT0
P0.1/INT1
P0.2
P0.3
P0.4/RST
XIN
XOUT
P1.5
P1.6
SN8F2255BF (LQFP 32 pins)
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
1.4 PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
P0.0/INT0
I/O
P0.1/INT1
I/O
P0[3:2]
I/O
P0.4/RST
I
P1[7:0]
I/O
P2[5:0]
I/O
P5.0/SCK
I/O
P5.1 /SDI
I/O
P5.2/SDO
I/O
P5.3/PWM1
I/O
P5.4/PWM0
I/O
XOUT
XIN
VREG25
VREG33
D+, D-
I/O
I/O
P
P
I/O
Power supply input pins for digital circuit.
P0.0: Port 0.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT0: External interrupt 0 input pin.
P0.1: Port 0.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT1: External interrupt 1 input pin.
P0: Port 0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
RST is system external reset input pin under Ext_RST mode, Schmitt trigger
structure, active “low”, and normal stay to “high”.
P0.4 is input only pin with pull-up resistor under P0.4 mode.
Built wakeup function.
P1: Port 1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
P2: Port 2 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.0: Port 5.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SCK: SIO output clock pin.
P5.1: Port 5.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SDI: SIO data input pin.
P5.2: Port 5.2 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
SDO: SIO data output pin.
P5: Port 5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
PWM1: PMW 1 output pin.
P5: Port 5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
PWM0: PMW 0 output pin.
XOUT: Oscillator output pin while external crystal enable.
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
2.5V power pin. Please connect 1uF capacitor to GND.
3.3V power pin. Please connect XuF capacitor to GND. X=1~10.
USB differential data line.
SONiX TECHNOLOGY CO., LTD
Page 11
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
1.5 PIN CIRCUIT DIAGRAMS
Port 0, 1, 2, 5 structures:
Pull-Up
PnM
PnUR
Input Bus
Pin
Output
Latch
Output Bus
Port 0.4 structure:
Pull-Up
Ext. Reset
Code
Option
Int.
Bus
Int.
Rst
Pi
n
SONiX TECHNOLOGY CO., LTD
Page 12
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
)
10K words ROM
ROM
0000H
0001H
.
.
0007H
0008H
0009H
.
.
000FH
0010H
0011H
.
.
.
.
.
27F8H
.
.
27FFH
SONiX TECHNOLOGY CO., LTD
Reset vector
User reset vector
Jump to user start address
General purpose area
Interrupt vector
User interrupt vector
User program
General purpose area
End of user program
Reserved
Page 13
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
) Power On Reset (NT0=1, NPD=0).
) Watchdog Reset (NT0=0, NPD=0).
) External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
¾
Example: Defining Reset Vector
ORG
JMP
…
0
START
ORG
10H
START:
…
…
ENDP
SONiX TECHNOLOGY CO., LTD
; 0000H
; Jump to user program address.
; 0010H, The head of user program.
; User program
; End of program
Page 14
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note:”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
¾
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG
JMP
…
0
START
; 0000H
; Jump to user program address.
ORG
PUSH
…
…
POP
RETI
…
8
; Interrupt vector.
; Save ACC and PFLAG register to buffers.
; Load ACC and PFLAG register from buffers.
; End of interrupt service routine
START:
…
…
JMP
…
; The head of user program.
; User program
START
ENDP
SONiX TECHNOLOGY CO., LTD
; End of user program
; End of program
Page 15
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
¾
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
JMP
…
ORG
JMP
0
START
; 0000H
; Jump to user program address.
8
MY_IRQ
; Interrupt vector.
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
…
…
…
JMP
…
; 0010H, The head of user program.
; User program.
START
MY_IRQ:
PUSH
…
…
POP
RETI
…
ENDP
; End of user program.
;The head of interrupt service routine.
; Save ACC and PFLAG register to buffers.
; Load ACC and PFLAG register from buffers.
; End of interrupt service routine.
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
SONiX TECHNOLOGY CO., LTD
Page 16
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
¾
Example: To look up the ROM data located “TABLE1”.
@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
; Z+1
; Z is not overflow.
; Z overflow (FFH Æ 00), Æ Y=Y+1
;
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
¾
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
Y
; Y+1
; Not overflow
@@:
ENDM
SONiX TECHNOLOGY CO., LTD
Page 17
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
¾
Example: Modify above example by “INC_YZ” macro.
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INC_YZ
@@:
TABLE1:
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
¾
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
B0MOV
Y, #TABLE1$M
Z, #TABLE1$L
; To set lookup table’s middle address.
; To set lookup table’s low address.
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
; Check the carry flag.
; FC = 0
; FC = 1. Y+1.
GETDATA:
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
MOVC
…
TABLE1:
DW
DW
DW
…
0035H
5105H
2012H
SONiX TECHNOLOGY CO., LTD
; To define a word (16 bits) data.
Page 18
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
¾
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Note: “VAL” is the number of the jump table listing number.
SONiX TECHNOLOGY CO., LTD
Page 19
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
¾
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
¾
Example: “@JMP_A” operation.
; Before compiling program.
ROM address
0X00FD
0X00FE
0X00FF
0X0100
0X0101
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
0X0100
0X0101
0X0102
0X0103
0X0104
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
SONiX TECHNOLOGY CO., LTD
Page 20
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.1.5 CHECKSUM CALCULATION
The last ROM addresses are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
¾
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
B0MOV
MOV
B0MOV
CLR
CLR
A,#END_USER_CODE$L
END_ADDR1, A
; Save low end address to end_addr1
A,#END_USER_CODE$M
END_ADDR2, A
; Save middle end address to end_addr2
Y
; Set Y to 00H
Z
; Set Z to 00H
MOVC
B0BSET
ADD
MOV
ADC
JMP
FC
DATA1, A
A, R
DATA2, A
END_CHECK
; Clear C flag
; Add A to Data1
INCMS
JMP
JMP
Z
@B
Y_ADD_1
; Z=Z+1
; If Z != 00H calculate to next address
; If Z = 00H increase Y
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A, END_ADDR1
A, Z
AAA
A, END_ADDR2
A, Y
AAA
CHECKSUM_END
; If Yes, check if Y = middle end address
; If Not jump to checksum calculate
; If Yes checksum calculated is done.
INCMS
NOP
JMP
Y
; Increase Y
@B
; Jump to checksum calculate
@@:
; Add R to Data2
; Check if the YZ address = the end of code
AAA:
END_CHECK:
; Check if Z = low end address
; If Not jump to checksum calculate
Y_ADD_1:
CHECKSUM_END:
…
…
END_USER_CODE:
SONiX TECHNOLOGY CO., LTD
; Label of program end
Page 21
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.2 CODE OPTION TABLE
Code Option
Ext_OSC
Content
6MHz
12MHz
16MHz
Always_On
Watch_Dog
Fcpu
Reset_Pin
Security0
Security1
Enable
Disable
Fhosc/1
Fhosc/2
Fhosc/4
Reset
P04
Enable
Disable
Enable
Disable
Function Description
6MHz crystal /resonator for external oscillator.
12MHz crystal /resonator for external oscillator.
16MHz crystal /resonator for external oscillator.
Watchdog timer is always on enable even in power down and green
mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable Watchdog function.
Instruction cycle is 12 MHz clock.
Instruction cycle is 6 MHz clock.
Instruction cycle is 3 MHz clock.
Enable External reset pin.
Enable P0.4 input only, with pull-up resistor function.
Enable ROM code Security function.
Disable ROM code Security function.
Enable ROM code Lock Address (0x2000~0x27FF) Security function.
Disable ROM code Lock Address (0x2000~0x27FF) Security function.
Note: Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4.
SONiX TECHNOLOGY CO., LTD
Page 22
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.3 DATA MEMORY (RAM)
)
512 X 8-bit RAM
BANK 0
BANK1
BANK2
)
Address
000h
“
“
“
“
“
07Fh
080h
“
“
“
“
“
0FFh
100h
“
“
“
“
“
1FFh
200h
“
“
“
“
“
27Fh
RAM location
BANK 0
General purpose area
System register
80h~FFh of Bank 0 store
system registers (128
bytes).
End of bank 0 area
BANK1
General purpose area
BANK2
General purpose area
56 x 8-bit RAM for USB DATA FIFO
56 x 8 RAM (FIFO)
00h
~
07h
08h
~
17h
18h
~
27h
28h
~
37h
SONiX TECHNOLOGY CO., LTD
Endpoint 0 RAM (8 byte)
Endpoint 1 RAM (16 byte)
Endpoint 2 RAM (16byte)
Endpoint 3 RAM (16 byte)
Page 23
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4 SYSTEM REGISTER
2.1.4.1 SYSTEM REGISTER TABLE
0
8
-
9
UDA
A
-
1
2
3
R
Z
USTAT EP0OU USB_IN
US
T_CNT T_EN
-
-
UDP0
4
Y
EP
_ACK
-
5
6
7
8
9
PFLAG RBANK TC0M
TC0C
EP
UE0R
UE1R
UE2R
UE3R
_NAK
UDR0_ UDR0_ EP1OU EP2OU EP3OU
R
W
T_CNT T_CNT T_CNT
B
-
-
-
-
SIOM
SIOR
C
D
E
F
P1W
P1M
P2M
-
-
P5M
SIOB
-
P0M
INTRQ1 INTEN1 INTRQ
A
B
C
D
E
F
TC0R
TC1M
TC1C
TC1R
-
-
UPID
UToggle
-
-
PEROM PEROM PERAM PERAM
PECMD
L
H
L
CNT
INTEN OSCM
WDTR
PCL
PEDGE
PCH
P0
P1
P2
-
-
P5
-
-
T0M
T0C
T1M
T1C_L
T1C_H
-
-
P0UR
P1UR
P2UR
-
-
P5UR
-
@YZ
-
-
-
-
-
-
-
STKP
-
STK7L STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
2.1.4.2 SYSTEM REGISTER DESCRIPTION
R=
PFLAG =
UDA =
UDP0 =
UDR0_W =
EP_ACK =
UToggle =
USTATUS =
EPXOUT_CNT =
SIOM =
SIOB =
PnM =
INTRQ =
INTRQ1 =
OSCM =
TC0R =
Pn =
TnC =
PnUR =
P1W =
PEROM =
PERAMCNT =
Working register and ROM look-up data buffer.
ROM page and special flag register.
USB control register.
USB FIFO address pointer.
USB FIFO write data buffer by UDP0 point to.
Endpoint ACK flag register.
USB endpoint toggle bit control register.
USB status register.
USB endpoint 1~3 OUT token data byte counter
SIO mode control register.
SIO’s data buffer.
Port n input/output mode register.
Interrupt request register.
Interrupt1 request register.
Oscillator mode register.
TC0 auto-reload data buffer.
Port n data buffer.
T0 counting register. n = 0, 1, C0, C1
Port n pull-up resister control register.
Port 1 wakeup control register.
ISP ROM address.
ISP RAM programming counter register.
SONiX TECHNOLOGY CO., LTD
Y, Z =
RBANK =
UE0R~UE3R =
UDR0_R =
EP_NAK =
UDR0_W =
UPID =
USB_INT_EN =
SIOR =
PEDGE =
INTEN =
INTEN1 =
WDTR =
PCH, PCL =
TnM =
TnR =
STKP =
@YZ =
STK0~STK7 =
PECMD =
PERAM =
Page 24
Working, @YZ and ROM addressing register.
RAM bank selection register.
Endpoint 0~3 control registers.
USB FIFO read data buffer by UDP0 point to.
Endpoint NAK flag register.
USB FIFO write data buffer by UDP1 point to.
USB bus control register.
USB interrupt enable/disable control register.
SIO’s clock reload buffer
P0.0, P0.1 edge direction register.
Interrupt enable register.
Interrupt1 enable register.
Watchdog timer clear register.
Program counter.
Tn mode register. n = 0, 1, C0, C1
Tn register. n = C0, C1
Stack pointer buffer.
RAM YZ indirect addressing index pointer.
Stack 0 ~ stack 7 buffer.
ISP command register.
ISP RAM mapping address.
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER
Address
082H
083H
084H
086H
087H
088H
089H
08AH
08BH
08CH
08DH
090H
091H
092H
093H
094H
095H
096H
097H
098H
099H
0A3H
0A5H
0A6H
0A7H
0A8H
0A9H
0ABH
0ACH
0B4H
0B5H
0B6H
0B8H
0BAH
0BBH
0BCH
0BDH
0BEH
0BFH
0C0H
0C1H
0C2H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
0CCH
0CEH
0CFH
0D0H
0D1H
0D2H
0D5H
0D8H
0D9H
0DAH
0DBH
0DCH
0DFH
0E0H
0E1H
0E2H
Bit7
RBIT7
ZBIT7
YBIT7
NT0
Bit6
RBIT6
ZBIT6
YBIT6
NPD
Bit5
RBIT5
ZBIT5
YBIT5
Bit4
RBIT4
ZBIT4
YBIT4
TC0ENB
TC0C7
TC0R7
TC1ENB
TC1C7
TC1R7
UDE
TC0rate2
TC0C6
TC0R6
TC1rate2
TC1C6
TC1R6
UDA6
TC0rate1
TC0C5
TC0R5
TC1rate1
TC1C5
TC1R5
UDA5
SOF
TC0rate0
TC0C4
TC0R4
TC1rate0
TC1C4
TC1R4
UDA4
BUS_RST
Bit3
RBIT3
ZBIT3
YBIT3
Bit2
RBIT2
ZBIT2
YBIT2
C
TC0CKS
ALOAD0
TC0C3
TC0C2
TC0R3
TC0R2
TC1CKS
ALOAD0
TC1C3
TC1C2
TC1R3
TC1R2
UDA3
UDA2
SUSPEND EP0_SETUP
UEP0OC3
UEP0OC2
SOF_INT
EP3NAK
REG_EN
DP_PU_EN
_EN
_INT_EN
EP3_ACK
EP3_NAK
UE0M1
UE0M0
UE0C3
UE0C2
UE1E
UE1M1
UE1M0
UE1C4
UE1C3
UE1C2
UE2E
UE2M1
UE2M0
UE2C4
UE2C3
UE2C2
UE3E
UE3M1
UE3M0
UE3C4
UE3C3
UE3C2
UDP07
UDP06
UDP05
UDP04
UDP03
UDP02
UDR0_R7
UDR0_R6
UDR0_R5
UDR0_R4
UDR0_R3
UDR0_R2
UDR0_W7 UDR0_W6 UDR0_W5 UDR0_W4 UDR0_W3 UDR0_W2
UEP1OC4
UEP1OC3
UEP1OC2
UEP2OC4
UEP2OC3
UEP2OC2
UEP3OC4
UEP3OC3
UEP3OC2
UBDE
EP3_DATA0
/1
SENB
START
SRATE1
SRATE0
MLSB
SCKMD
SIOR7
SIOR6
SIOR5
SIOR4
SIOR3
SIOR2
SIOB7
SIOB6
SIOB5
SIOB4
SIOB3
SIOB2
P03M
P02M
PECMD7
PECMD6
PECMD5
PECMD4
PECMD3
PECMD2
PEROML7 PEROML6 PEROML5 PEROML4 PEROML3 PEROML2
PEORMH7 PEORMH6 PEORMH5 PEORMH4 PEORMH3 PEORMH2
PERAML7
PERAML6
PERAML5
PERAML4
PERAML3
PERAML2
PERAMCNT PERAMCNT PERAMCNT PERAMCNT PERAMCNT
4
3
2
1
0
P01G1
P01G0
P17W
P16W
P15W
P14W
P13W
P12W
P17M
P16M
P15M
P14M
P13M
P12M
P25M
P24M
P23M
P22M
P54M
P53M
P52M
SOFIRQ
SOFIEN
USBIRQ
USBIEN
T1IRQ
T1IEN
WDTR7
PC7
WDTR6
PC6
WDTR5
PC5
PC13
P17
P16
P15
P25
T0ENB
T0C7
T1ENB
T1C7
T1C15
GIE
T0rate2
T0C6
T1rate2
T1C6
T1C14
T0rate1
T0C5
T1rate1
T1C5
T1C13
T0IRQ
T0IEN
CPUM1
WDTR4
PC4
PC12
P04
P14
P24
P54
T0rate0
T0C4
T1rate0
T1C4
T1C12
P17R
P16R
P15R
P25R
P14R
P24R
SONiX TECHNOLOGY CO., LTD
Bit1
RBIT1
ZBIT1
YBIT1
DC
RBNKS1
TC0OUT
TC0C1
TC0R1
TC1OUT
TC1C1
TC1R1
UDA1
EP0_IN
UEP0OC1
EP2NAK
_INT_EN
EP2_ACK
EP2_NAK
UE0C1
UE1C1
UE2C1
UE3C1
UDP01
UDR0_R1
UDR0_W1
UEP1OC1
UEP2OC1
UEP3OC1
DDP
EP2_DATA0
/1
SEDGE
SIOR1
SIOB1
P01M
PECMD1
PEROML1
PEORMH1
PERAML1
Bit0
RBIT0
ZBIT0
YBIT0
Z
RBNKS0
PWM0OUT
TC0C0
TC0R0
PWM0OUT
TC1C0
TC1R0
UDA0
EP0_OUT
UEP0OC0
EP1NAK
_INT_EN
EP1_ACK
EP1_NAK
UE0C0
UE1C0
UE2C0
UE3C0
UDP00
UDR0_R0
UDR0_W0
UEP1OC0
UEP2OC0
UEP3OC0
DDN
EP1_DATA0
/1
SP
SIOR0
SIOB0
P00M
PECMD0
PEROML0
PEORMH0
PERAML0
R/W
USB_INT_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EP_ACK
EP_NAK
UE0R
UE1R
UE2R
UE3R
UDP0
UDR0_R
UDR0_W
EP1OUT_CNT
EP2OUT_CNT
EP3OUT_CNT
UPID
R/W
Utoggle
R/W
W
R/W
R/W
W
R/W
R/W
R/W
SIOM
SIOR
SIOB
P0M
PECMD
PEROML
PEORMH
PERAML
R/W
PERAMCNT
P00G0
P10W
P10M
P20M
P50M
TC0IRQ
TC0IEN
P00IRQ
P00IEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
PEDGE
P1W
P1M
P2M
P5M
INTRQ1
INTEN1
INTRQ
INTEN
OSCM
WDTR
PCL
PCH
P0
P1
P2
P5
T0M
T0C
T1M
T1C_L
T1C_H
STKP
P0UR
P1UR
P2UR
SIOIRQ
SIOIEN
CPUM0
WDTR3
PC3
PC11
P03
P13
P23
P53
WAKEIRQ
WAKEIEN
CLKMD
WDTR2
PC2
PC10
P02
P12
P22
P52
T0C3
T0C2
T0C1
T0C0
T1C3
T1C11
T1C2
T1C10
STKPB2
P02R
P12R
P22R
T1C1
T1C9
STKPB1
P01R
P11R
P21R
T1C0
T1C8
STKPB0
P00R
P10R
P20R
Page 25
Remarks
R
Z
Y
PFLAG
RBANK
TC0M
TC0C
TC0R
TC1M
TC1C
TC1R
UDA
USTATUS
EP0OUT_CNT
PERAML8
P00G1
P11W
P11M
P21M
P51M
TC1IRQ
TC1IEN
P01IRQ
P01IEN
STPHX
WDTR1
PC1
PC9
P01
P11
P21
P51
P03R
P13R
P23R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WDTR0
PC0
PC8
P00
P10
P10
P50
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
0E5H
0E7H
0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
@YZ7
S7PC7
@YZ6
S7PC6
S6PC7
S6PC6
S5PC7
S5PC6
S4PC7
S4PC6
S3PC7
S3PC6
S2PC7
S2PC6
S1PC7
S1PC6
S0PC7
S0PC6
@YZ5
S7PC5
S7PC13
S6PC5
S6PC13
S5PC5
S5PC13
S4PC5
S4PC13
S3PC5
S3PC13
S2PC5
S2PC13
S1PC5
S1PC13
S0PC5
S0PC13
P54R
@YZ4
S7PC4
S7PC12
S6PC4
S6PC12
S5PC4
S5PC12
S4PC4
S4PC12
S3PC4
S3PC12
S2PC4
S2PC12
S1PC4
S1PC12
S0PC4
S0PC12
P53R
@YZ3
S7PC3
S7PC11
S6PC3
S6PC11
S5PC3
S5PC11
S4PC3
S4PC11
S3PC3
S3PC11
S2PC3
S2PC11
S1PC3
S1PC11
S0PC3
S0PC11
P52R
@YZ2
S7PC2
S7PC10
S6PC2
S6PC10
S5PC2
S5PC10
S4PC2
S4PC10
S3PC2
S3PC10
S2PC2
S2PC10
S1PC2
S1PC10
S0PC2
S0PC10
P51R
@YZ1
S7PC1
S7PC9
S6PC1
S6PC9
S5PC1
S5PC9
S4PC1
S4PC9
S3PC1
S3PC9
S2PC1
S2PC9
S1PC1
S1PC9
S0PC1
S0PC9
P50R
@YZ0
S7PC0
S7PC8
S6PC0
S6PC8
S5PC0
S5PC8
S4PC0
S4PC8
S3PC0
S3PC8
S2PC0
S2PC8
S1PC0
S1PC8
S0PC0
S0PC8
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5UR
@YZ
STK7L
STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note:
1. To avoid system error, please be sure to put all the “0” and “1” as it indicates in the above table.
2.
3.
4.
5.
All of register names had been declared in SN8ASM assembler.
One-bit name had been declared in SN8ASM assembler with “F” prefix code.
“b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
For detail description, please refer to the “System Register Quick Reference Table”.
SONiX TECHNOLOGY CO., LTD
Page 26
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.4 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
¾
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory.
MOV
BUF, A
; Write a immediate data into ACC.
MOV
A, #0FH
; Write ACC data from BUF data memory.
MOV
A, BUF
B0MOV
A, BUF
; or
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.
¾
Example: Protect ACC and working registers.
INT_SERVICE:
PUSH
…
…
POP
; Save ACC and PFLAG to buffers.
.
RETI
SONiX TECHNOLOGY CO., LTD
; Load ACC and PFLAG from buffers.
; Exit interrupt service vector
Page 27
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.5 PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation.
086H
PFLAG
Read/Write
After reset
Bit [7:6]
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
NT0, NPD: Reset status flag.
NT0
0
0
1
1
NPD
0
1
0
1
Reset Status
Watch-dog time out
Reserved
Reset by LVD
Reset by external Reset Pin
Bit 2
C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
Bit 1
DC: Decimal carry flag
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
Bit 0
Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
SONiX TECHNOLOGY CO., LTD
Page 28
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.6 PROGRAM COUNTER
The program counter (PC) is a 14-bit binary counter separated into the high-byte 6 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 13.
PC
After
reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC13 PC12 PC11 PC10 PC9
-
-
0
0
0
0
0
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
PCH
)
PCL
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
…
…
NOP
A, BUF0
FZ
C1STEP
; Move BUF0 value to ACC.
; To skip, if Zero flag = 0.
; Else jump to C1STEP.
C1STEP:
B0MOV
B0BTS0
JMP
…
…
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
…
…
NOP
A, #12H
C0STEP
SONiX TECHNOLOGY CO., LTD
; To skip, if ACC = 12H.
; Else jump to C0STEP.
Page 29
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
INCMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
INCMS instruction:
C0STEP:
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
C0STEP:
DECS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
DECMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
DECMS instruction:
C0STEP:
SONiX TECHNOLOGY CO., LTD
Page 30
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
)
MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
MOV
B0MOV
…
A, #28H
PCL, A
; Jump to address 0328H
MOV
B0MOV
…
A, #00H
PCL, A
; Jump to address 0300H
; PC = 0328H
¾
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
…
…
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
SONiX TECHNOLOGY CO., LTD
; PCL = PCL + ACC, the PCH cannot be changed.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
Page 31
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.7 Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
z
can be used as general working registers
z
can be used as RAM data pointers with @YZ register
z
can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
-
Bit 6
YBIT6
R/W
-
Bit 5
YBIT5
R/W
-
Bit 4
YBIT4
R/W
-
Bit 3
YBIT3
R/W
-
Bit 2
YBIT2
R/W
-
Bit 1
YBIT1
R/W
-
Bit 0
YBIT0
R/W
-
083H
Z
Read/Write
After reset
Bit 7
ZBIT7
R/W
-
Bit 6
ZBIT6
R/W
-
Bit 5
ZBIT5
R/W
-
Bit 4
ZBIT4
R/W
-
Bit 3
ZBIT3
R/W
-
Bit 2
ZBIT2
R/W
-
Bit 1
ZBIT1
R/W
-
Bit 0
ZBIT0
R/W
-
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
B0MOV
B0MOV
Y, #00H
Z, #25H
A, @YZ
; To set RAM bank 0 for Y register
; To set location 25H for Z register
; To read a data into ACC
Example: Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Z = 7FH, the last address of the data memory area
CLR
@YZ
; Clear @YZ to be zero
DECMS
JMP
Z
CLR_YZ_BUF
; Z – 1, if Z= 0, finish the routine
; Not zero
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
…
SONiX TECHNOLOGY CO., LTD
Page 32
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.1.4.8 R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
z
Can be used as working register
z
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
-
Bit 6
RBIT6
R/W
-
Bit 5
RBIT5
R/W
-
Bit 4
RBIT4
R/W
-
Bit 3
RBIT3
R/W
-
Bit 2
RBIT2
R/W
-
Bit 1
RBIT1
R/W
-
Bit 0
RBIT0
R/W
-
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
SONiX TECHNOLOGY CO., LTD
Page 33
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.2 ADDRESSING MODE
2.2.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
¾
Example: Move the immediate data 12H to ACC.
MOV
¾
; To set an immediate data 12H into ACC.
Example: Move the immediate data 12H to R register.
B0MOV
A, #12H
R, #12H
; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.2.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
¾
Example: Move 0x12 RAM location data into ACC.
B0MOV
¾
A, 12H
; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
Example: Move ACC data into 0x12 RAM location.
B0MOV
12H, A
; To get a content of ACC and save in RAM location 12H of
bank 0.
2.2.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z).
¾
Example: Indirectly addressing mode with @YZ register.
B0MOV
B0MOV
B0MOV
Y, #0
Z, #12H
A, @YZ
SONiX TECHNOLOGY CO., LTD
; To clear Y register to access RAM bank 0.
; To set an immediate data 12H into Z register.
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
Page 34
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.3 STACK OPERATION
2.3.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
STKP + 1
CALL /
INTERRUPT
STKP - 1
PCH
PCL
STACK Level
STACK Buffer
High Byte
STACK Buffer
Low Byte
STKP = 7
STK7H
STK7L
STKP = 6
STK6H
STK6L
STKP = 5
STK5H
STKP
STK5L
STKP
STKP = 4
STK4H
STK4L
STKP = 3
STK3H
STK3L
STKP = 2
STK2H
STK2L
STKP = 1
STK1H
STK1L
STKP = 0
STK0H
STK0L
SONiX TECHNOLOGY CO., LTD
Page 35
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.3.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 14-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit[2:0]
STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7
GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
¾
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
MOV
B0MOV
A, #00000111B
STKP, A
0F0H~0FFH
STKnH
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
SnPC13
R/W
0
Bit 4
SnPC12
R/W
0
Bit 3
SnPC11
R/W
0
Bit 2
SnPC10
R/W
0
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
0F0H~0FFH
STKnL
Read/Write
After reset
Bit 7
SnPC7
R/W
0
Bit 6
SnPC6
R/W
0
Bit 5
SnPC5
R/W
0
Bit 4
SnPC4
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
STKn = STKnH , STKnL (n = 7 ~ 0)
SONiX TECHNOLOGY CO., LTD
Page 36
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
2.3.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
0
1
2
3
4
5
6
7
8
>8
STKPB2
STKP Register
STKPB1
STKPB0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
Stack Buffer
High Byte Low Byte
Free
STK0H
STK1H
STK2H
STK3H
STK4H
STK5H
STK6H
STK7H
-
Free
STK0L
STK1L
STK2L
STK3L
STK4L
STK5L
STK6L
STK7L
-
Description
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
8
7
6
5
4
3
2
1
0
STKP Register
STKPB2
STKPB1
STKPB0
1
0
0
0
0
1
1
1
1
SONiX TECHNOLOGY CO., LTD
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Stack Buffer
High Byte Low Byte
STK7H
STK6H
STK5H
STK4H
STK3H
STK2H
STK1H
STK0H
Free
Page 37
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
Free
Description
-
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
z
z
z
z
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
PFLAG
Read/Write
After reset
Bit [7:6]
Bit 7
NT0
R/W
-
Bit 6
NPD
R/W
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
NT0, NPD: Reset status flag.
NT0
0
0
1
1
NPD
0
1
0
1
Condition
Watchdog reset
Reserved
Power on reset and LVD reset.
External reset
Description
Watchdog timer overflow.
Power voltage is lower than LVD detecting level.
External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
Power
LVD Detect Level
VSS
VDD
External Reset
VSS
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog Normal Run
Watchdog Reset
Watchdog Stop
System Normal Run
System Status
System Stop
Power On
Delay Time
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External
Reset Delay
Time
Page 38
Watchdog
Reset Delay
Time
Version 1.1
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USB 2.0 Full-Speed 8-Bit Micro-Controller
3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
z
z
z
z
z
Power-up: System detects the power voltage up and waits for power stable.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
z
z
z
z
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
z
z
z
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
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3.4 BROWN OUT RESET
3.4.1 BROWN OUT DESCRIPTION
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
System Work
Well Area
V1
V2
VSS
V3
System Work
Error Area
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
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3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini.
Operating Voltage.
Vdd (V)
Normal Operating
Area
Dead-Band Area
Reset Area
System Reset
Voltage.
System Rate (Fcpu)
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
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3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
z
z
z
z
LVD reset
Watchdog reset
Reduce the system executing rate
External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1.
The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can
completely improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips)
and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset
IC”). The structure can improve noise effective and get good EFT characteristic.
LVD reset:
VDD
Power
LVD Detect Voltage
VSS
Power is below LVD Detect
Voltage and System Reset.
System Normal Run
System Status
System Stop
Power On
Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
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3.5 EXTERNAL RESET
External reset function is controlled by “Reset_Pin” code option. Set the code option as “Reset” option to enable
external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when
reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset
operation actives in power on and normal running mode. During system power-up, the external reset pin must be high
level input, or the system keeps in reset status. External reset sequence is as following.
z
z
z
z
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
VDD
R1
47K ohm
R2
RST
100 ohm
MCU
C1
0.1uF
VSS
VCC
GND
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
Note: The reset circuit is no any protection against unusual power or brown out reset.
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3.6.2 Diode & RC Reset Circuit
VDD
R1
47K ohm
DIODE
R2
RST
100 ohm
MCU
C1
0.1uF
VSS
VCC
GND
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
VDD
R1
33K ohm
R2
E
B
10K ohm
Vz
Q1
C
RST
MCU
R3
40K ohm
VSS
VCC
GND
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
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3.6.4 Voltage Bias Reset Circuit
VDD
R1
47K ohm
E
B
Q1
C
R2
10K ohm
RST
MCU
R3
2K ohm
VSS
VCC
GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops
below the reset detect voltage, the system reset would be triggered, and then system executes
reset sequence. That makes sure the system work well under unstable power situation.
3.6.5 External Reset IC
VDD
VDD
B yp ass
C ap acito r
0 .1u F
R e set
IC
VSS
RST
RST
MCU
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation
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4
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator & on-chip PLL circuit. The low-speed clock is generated from on-chip low-speed
RC oscillator circuit (ILRC 24 KHz).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
)
Normal Mode (High Clock):
Fcpu = Fhosc / N, N = 1 ~ 4, Select N by Fcpu code option.
)
Slow Mode (Low Clock):
Fcpu = Flosc/4.
SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise
outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.
4.2 CLOCK BLOCK DIAGRAM
STPHX
XIN
XOUT
HOSC
Fhosc.
Fcpu Code Option
Fcpu = Fhosc/1 ~ Fhosc/4, Noise Filter Disable.
Fcpu = Fhosc/4, Noise Filter Enable.
CLKMD
Fosc
Fcpu
Fosc
CPUM[1:0]
Flosc.
z
z
z
z
z
Fcpu = Flosc/4
HOSC: High_Clk code option.
Fhosc: External high-speed clock.
Flosc: Internal low-speed RC clock (Typical 24 KHz).
Fosc: System clock source.
Fcpu: Instruction cycle.
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4.3 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH
OSCM
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
CPUM1
R/W
0
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 0
-
Bit 1
STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2
CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3]
CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
¾
Example: Stop high-speed oscillator and PLL circuit.
B0BSET
FSTPHX
; To stop external high-speed oscillator only.
Example: When entering the power down mode (sleep mode), both high-speed external oscillator, PLL circuit
and internal low-speed oscillator will be stopped.
B0BSET
FCPUM0
SONiX TECHNOLOGY CO., LTD
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
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4.4 SYSTEM HIGH CLOCK
The system high clock is from the in circuit PLL. User must select the external oscillator 6MHz X’tal, 12MHz X’tal or
16MHz X’tal by the code option “Ext_OSC”, and the entire three clock source will input to the on-chip PLL circuit. PLL
will output 12MHz to system clock (Fosc).
4.4.1 EXTERNAL HIGH CLOCK
External high clock includes three modules (Crystal and external clock signal). The start up time of crystal and ceramic
oscillator is different. The oscillator start-up time decides reset time length.
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4.4.1.1 CRYSTAL
Crystal devices are driven by XIN, XOUT pins.
XIN
CRYSTAL
C
20pF
XOUT
MCU
C
VDD
20pF
VSS
VCC
GND
Note: Connect the Crystal and C as near as possible to the XIN/XOUT/VSS pins of micro-controller.
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4.1.1.2 EXTERNAL CLOCK SIGNAL
Selecting external clock signal input to be the input clock source is by the “Ext_OSC” code option. The external clock
signal is input from XIN pin. XOUT pin is general purpose I/O pin.
External Clock Input
XIN
XOUT
MCU
VSS
VDD
VCC
GND
Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.
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4.2 SYSTEM LOW CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 24KHz.
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.
)
Flosc = Internal low RC oscillator (24KHz).
)
Slow mode Fcpu = Flosc / 4
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 24K mode
and watchdog disable. If system is in 24K mode and watchdog disable, only 24K oscillator actives and system is under
low power consumption.
¾
Example: Stop internal low-speed oscillator by power down mode.
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1
(24K, watchdog disable) bits of OSCM register.
4.2.1 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
Example: Fcpu instruction cycle of external oscillator.
B0BSET
P0M.0
; Set P0.0 to be output mode for outputting Fcpu toggle signal.
B0BSET
B0BCLR
JMP
P0.0
P0.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
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5
SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
z
z
z
z
High-speed mode
Low-speed mode
Power-down mode (Sleep mode)
Green mode
Power Down Mode
(Sleep Mode)
P0, P1 Wake-up Function Active.
USB Bus.
External Reset Circuit Active.
CPUM1, CPUM0 = 01.
CLKMD = 1
Normal Mode
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
USB Bus.
External Reset Circuit Active.
CLKMD = 0
Slow Mode
CPUM1, CPUM0 = 10.
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
USB Bus.
Green Mode
External Reset Circuit
Active.
System Mode Switching Diagram
Operating mode description
MODE
EHOSC
ILRC
CPU instruction
T0 timer
T1 timer
TC0 timer
TC1 timer
USB
Watchdog timer
Internal interrupt
External interrupt
Wakeup source
z
z
POWER DOWN
(SLEEP)
Running
By STPHX
By STPHX
Stop
Running
Running
Running
Stop
Executing
Executing
Stop
Stop
*Active
*Active
*Active
Inactive
*Active
*Active
Inactive
Inactive
*Active
*Active
Inactive
Inactive
*Active
*Active
Inactive
Inactive
Running
Inactive
Inactive
Inactive
By Watch_Dog By Watch_Dog By Watch_Dog By Watch_Dog
Code option
Code option
Code option
Code option
All active
All active
T0
All inactive
All active
All active
All active
All inactive
P0, P1, T0,
P0, P1, Reset
Reset
NORMAL
SLOW
GREEN
REMARK
* Active if T0ENB=1
* Active if T1ENB=1
* Active if TC0ENB=1
* Active if TC1ENB=1
* Active if USBE=1
Refer to code option
description
EHOSC: External high clock (External X’tal)
ILRC: Internal low clock (24KHz RC oscillator)
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5.2 SYSTEM MODE SWITCHING EXAMPLE
¾
Example: Switch normal/slow mode to power down (sleep) mode.
B0BSET
FCPUM0
; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
¾
Example: Switch normal mode to slow mode.
B0BSET
B0BSET
¾
FCLKMD
FSTPHX
;To set CLKMD = 1, Change the system into slow mode
;To stop external high-speed oscillator for power saving.
Example: Switch slow mode to normal mode (The external high-speed oscillator is still running).
B0BCLR
FCLKMD
;To set CLKMD = 0
Example: Switch slow mode to normal mode (The external high-speed oscillator stops).
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for
external clock stable.
@@:
B0BCLR
FSTPHX
; Turn on the external high-speed oscillator.
MOV
B0MOV
DECMS
JMP
A, #20
Z, A
Z
@B
; internal RC=24KHz (typical) will delay
B0BCLR
FCLKMD
; 0.33ms X 30 ~ 10ms for external clock stable
;
; Change the system back to the normal mode
Example: Switch normal/slow mode to green mode.
B0BSET
FCPUM1
; Set CPUM1 = 1.
Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can
wakeup the system backs to the previous operation mode.
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Example: Switch normal/slow mode to green mode and enable T0 wake-up function.
; Set T0 timer wakeup function.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
B0BCLR
B0BCLR
B0BSET
; Go into green mode
B0BCLR
B0BSET
FT0IEN
FT0ENB
A,#20H
T0M,A
A,#74H
T0C,A
FT0IEN
FT0IRQ
FT0ENB
; To disable T0 interrupt service
; To disable T0 timer
;
; To set T0 clock = Fcpu / 64
FCPUM0
FCPUM1
;To set CPUMx = 10
; To set T0C initial value = 74H (To set T0 interval = 10 ms)
; To disable T0 interrupt service
; To clear T0 interrupt request
; To enable T0 timer
Note: During the green mode with T0 wake-up function, the wakeup pin and T0 wakeup the system back
to the last mode. T0 wake-up period is controlled by program.
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5.3 WAKEUP
5.3.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change),
internal trigger (T0 timer overflow) and USB bus toggle.
z
z
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change
and USB bus toggle)
Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,
P1 level change), internal trigger (T0 timer overflow) and USB bus toggle.
5.3.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 16384 external 6MHz clocks as the wakeup time to stable the oscillator circuit. After the
wakeup time, the system goes into the normal mode.
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
The value of the wakeup time is as the following.
“16M_X’tal/12M_X’tal/6M_X’tal” mode:
The Wakeup time = 1/Fosc * 16384 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
Example: In 16M_X’tal/12M_X’tal/6M_X’tal mode and power down mode (sleep mode), the system is waked up.
After the wakeup time, the system goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/6MHz * 16384 = 2.72 ms
The total wakeup time = 2.72 ms + oscillator start-up time
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6
INTERRUPT
6.1 OVERVIEW
This MCU provides 9 interrupt sources, including 6 internal interrupt (T0/T1/TC0/TC1/USB/SIO) and two external
interrupt (INT0/INT1). The external interrupt can wakeup the chip while the system is switched from power down mode
to high-speed normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for
stopping other interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the
next interrupts’ request. All of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable
Register
P00IR
Q
P01IR
Q
INT0 Trigger
INT1 Trigger
T0 Time
Out
T1 Time
Out
TC0 Time Out
INTR
Q
2Bit
Latchs
TC1 Time Out
USB Process
End
SIO Transmit ready
I/O pin wakeup
trigger
T0IRQ
T1IRQ
TC0IRQ
TC1IRQ
Interrupt Vector Address (0008H)
Interrupt
Enabl
e
Global Interrupt Request
Signal
Gating
USBIR
Q
SIOIRQ
WAKEIR
Q
Note: The GIE bit must enable during all interrupt operation.
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6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C7H
INTEN1
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 0
TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
Bit 1
TC1IEN: TC1 timer interrupt control bit.
0 = Disable TC1 interrupt function.
1 = Enable TC1 interrupt function.
0C9H
INTEN
Read/Write
After reset
Bit 7
SOFIEN
R/W
0
Bit 6
USBIEN
R/W
0
Bit 5
T1IEN
R/W
0
Bit 4
Bit 3
Bit 2
Bit 1
TC1IEN
R/W
0
Bit 0
TC0IEN
R/W
0
Bit 4
T0IEN
R/W
0
Bit 3
SIOIEN
R/W
0
Bit 2
WAKEIEN
R/W
0
Bit 1
P01IEN
R/W
0
Bit 0
P00IEN
R/W
0
Bit 0
P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 1
P01IEN: External P0.1 interrupt (INT1) control bit.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
Bit 2
WAKEIEN: I/O PORT0 & PORT 1 WAKEUP interrupt control bit.
0 = Disable WAKEUP interrupt function.
1 = Enable WAKEUP interrupt function.
Bit 3
SIOIEN: SIO interrupt control bit.
0 = Disable SIO interrupt function.
1 = Enable SIO interrupt function.
Bit 4
T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
Bit 5
T1IEN: T1 timer interrupt control bit.
0 = Disable T1 interrupt function.
1 = Enable T1 interrupt function.
Bit 6
USBIEN: USB interrupt control bit.
0 = Disable USB interrupt function.
1 = Enable USB interrupt function.
Bit 7
SOFIEN: USB SOF interrupt control bit. Control this SOF interrupt with the USB_INT_EN register.
0 = Disable USB SOF interrupt function.
1 = Enable USB SOF interrupt function.
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs; the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C6H
INTRQ1
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 0
TC0IRQ: TC0 timer interrupt request flag.
0 = None TC0 interrupt request.
1 = T0 interrupt request.
Bit 1
TC1IRQ: TC1 timer interrupt request flag.
0 = None TC1 interrupt request.
1 = T0 interrupt request.
0C8H
INTRQ
Read/Write
After reset
Bit 7
SOFIRQ
RW
0
Bit 6
USBIRQ
R/W
0
Bit 5
T1IRQ
R/W
0
Bit 4
Bit 3
Bit 2
Bit 1
TC1IRQ
R/W
0
Bit 0
TC0IRQ
R/W
0
Bit 4
T0IRQ
R/W
0
Bit 3
SIOIRQ
R/W
0
Bit 2
WAKEIRQ
R/W
0
Bit 1
P01IRQ
R/W
0
Bit 0
P00IRQ
R/W
0
Bit 0
P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 1
P01IRQ: External P0.1 interrupt (INT1) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 2
WAKEIRQ: I/O PORT0 & PORT1 WAKEUP interrupt request flag.
0 = None WAKEUP interrupt request.
1 = WAKEUP interrupt request.
Bit 3
SIOIRQ: SIO interrupt request flag.
0 = None SIO interrupt request.
1 = SIO interrupt request.
Bit 4
T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
Bit 5
T1IRQ: T1 timer interrupt request flag.
0 = None T1 interrupt request.
1 = T1 interrupt request.
Bit 6
USBIRQ: USB interrupt request flag.
0 = None USB interrupt request.
1 = USB interrupt request.
Bit 7
SOFIRQ: USB SOF interrupt request flag. Control this SOF interrupt with the USTATUS register.
0 = None USB SOF interrupt request.
1 = USB SOF interrupt request.
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6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH
STKP
Read/Write
After reset
Bit 7
Bit 7
GIE
R/W
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instructions save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is
an unique buffer and only one level.
¾
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine
executed.
ORG
JMP
0
START
ORG
JMP
8
INT_SERVICE
ORG
10H
START:
…
INT_SERVICE:
PUSH
…
…
POP
; Save ACC and PFLAG to buffers.
RETI
…
ENDP
; Exit interrupt service vector
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; Load ACC and PFLAG from buffers.
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6.6 INT0 (P0.0) & INT1 (P0.1) INTERRUPT OPERATION
When the INT0/INT1 trigger occurs, the P00IRQ/P01IRQ will be set to “1” no matter the P00IEN/P01IEN is enable or
disable. If the P00IEN/P01IEN = 1 and the trigger event P00IRQ/P01IRQ is also set to be “1”. As the result, the
system will execute the interrupt vector (ORG 8). If the P00IEN/P01IEN = 0 and the trigger event P00IRQ/P01IRQ is
still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P00IRQ/P01IRQ is set to be “1”.
Users need to be cautious with the operation under multi-interrupt situation.
If the interrupt trigger direction is identical with wake-up trigger direction, the INT0/INT1 interrupt request flag
(INT0IRQ/INT1IRQ) is latched while system wake-up from power down mode or green mode by P0.0 wake-up trigger.
System inserts to interrupt vector (ORG 8) after wake-up immediately.
Note: INT0 interrupt request can be latched by P0.0 wake-up trigger.
Note: INT1 interrupt request can be latched by P0.1 wake-up trigger.
Note: The interrupt trigger direction of P0.0/P0.1 is control by PEDGE register.
0BFH
PEDGE
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit[1:0]
P00G[1:0]: P0.0 interrupt trigger edge control bits.
00 = reserved.
01 = rising edge.
10 = falling edge.
11 = rising/falling bi-direction (Level change trigger).
Bit[3:2]
P01G[1:0]: P0.1 interrupt trigger edge control bits.
00 = reserved.
01 = rising edge.
10 = falling edge.
11 = rising/falling bi-direction (Level change trigger).
Bit 3
P01G1
R/W
1
Bit 2
P01G0
R/W
0
Bit 1
P00G1
R/W
1
Bit 0
P00G0
R/W
0
Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV
B0MOV
A, #18H
PEDGE, A
; Set INT0 interrupt trigger as bi-direction edge.
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
; Enable INT0 interrupt service
; Clear INT0 interrupt request flag
; Enable GIE
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Example: INT0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
…
…
FP00IRQ
; Reset P00IRQ
; INT0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.7 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
¾
Example: T0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FT0IEN
FT0ENB
A, #20H
T0M, A
A, #74H
T0C, A
; Disable T0 interrupt service
; Disable T0 timer
;
; Set T0 clock = Fcpu / 64
; Set T0C initial value = 74H
; Set T0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
; Enable T0 interrupt service
; Clear T0 interrupt request flag
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
Example: T0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FT0IRQ
EXIT_INT
; Check T0IRQ
; T0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FT0IRQ
A, #74H
T0C, A
; Reset T0IRQ
; Reset T0C.
; T0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.8 T1 INTERRUPT OPERATION
When the T1C counter overflows, the T1IRQ will be set to “1” no matter the T1IEN is enable or disable. If the T1IEN
and the trigger event T1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the T1IEN =
0, the trigger event T1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the
T1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: T1 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
MOV
B0MOV
FT1IEN
FT1ENB
A, #00H
T1M, A
A, #0E5H
T1C_L, A
A, #48H
T1C_H, A
; Disable T1 interrupt service
; Disable T1 timer
;
; Set T1 clock = Fcpu / 256
; Set T1C_L initial value = E5H
B0BSET
B0BCLR
B0BSET
FT1IEN
FT1IRQ
FT1ENB
; Enable T1 interrupt service
; Clear T1 interrupt request flag
; Enable T1 timer
B0BSET
FGIE
; Enable GIE
; Set T1C_H initial value = 48H
; Set T1 interval = 1s
Example: T1 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FT1IRQ
EXIT_INT
; Check T1IRQ
; T1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
MOV
B0MOV
…
…
FT1IRQ
A, #0E5H
T1C_L, A
A, #48H
T1C_H, A
; Reset T1IRQ
; Reset T1C_L.
; Reset T1C_H.
; T1 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.9 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: TC0 interrupt request setup.
¾
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A, #20H
TC0M, A
A, #74H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 74H
; Set TC0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC0IRQ
A, #74H
TC0C, A
; Reset TC0IRQ
; Reset TC0C.
; TC0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.10 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: TC1 interrupt request setup.
¾
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC1IEN
FTC1ENB
A, #20H
TC1M, A
A, #74H
TC1C, A
; Disable TC1 interrupt service
; Disable TC1 timer
;
; Set TC1 clock = Fcpu / 64
; Set TC1C initial value = 74H
; Set TC1 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
; Enable TC1 interrupt service
; Clear TC1 interrupt request flag
; Enable TC1 timer
B0BSET
FGIE
; Enable GIE
Example: TC1 interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC1IRQ
A, #74H
TC1C, A
; Reset TC1IRQ
; Reset TC1C.
; TC1 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.11 USB INTERRUPT OPERATION
When the USB process finished, the USBIRQ will be set to “1” no matter the USBIEN is enable or disable. If the
USBIEN and the trigger event USBIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If
the USBIEN = 0, the trigger event USBIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector.
Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: USB interrupt request setup.
B0BCLR
B0BCLR
B0BSET
FUSBIEN
FUSBIRQ
FUSBIEN
…
…
B0BSET
; Disable USB interrupt service
; Clear USB interrupt request flag
; Enable USB interrupt service
; USB initializes.
; USB operation.
FGIE
; Enable GIE
Example: USB interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
PUSH
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FUSBIRQ
EXIT_INT
; Check USBIRQ
; USBIRQ = 0, exit interrupt vector
B0BCLR
FUSBIRQ
; Reset USBIRQ
…
…
; USB interrupt service routine
POP
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
EXIT_INT:
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6.12 WAKEUP INTERRUPT OPERATION
When the I/O port 1 or I/O port 0 wakeup the MCU from the sleep mode, the WAKEIRQ will be set to “1” no matter the
WAKEIEN is enable or disable. If the WAKEIEN and the trigger event WAKEIRQ is set to be “1”. As the result, the
system will execute the interrupt vector. If the WAKEIEN = 0, the trigger event WAKEIRQ is still set to be “1”.
Moreover, the system won’t execute interrupt vector. Users need to be cautious with the operation under multi-interrupt
situation.
¾
Example: WAKE interrupt request setup.
B0BCLR
B0BCLR
B0BSET
FWAKEIEN
FWAKEIRQ
FWAKEIEN
…
…
B0BSET
; Disable WAKE interrupt service
; Clear WAKE interrupt request flag
; Enable WAKE interrupt service
; Pin WAKEUP initialize.
; Pin WAKEUP operation.
FGIE
; Enable GIE
Example: WAKE interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
PUSH
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FWAKEIRQ
EXIT_INT
; Check WAKEIRQ
; WAKEIRQ = 0, exit interrupt vector
B0BCLR
FWAKEIRQ
; Reset WAKEIRQ
…
…
; WAKE interrupt service routine
POP
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
EXIT_INT:
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6.13 SIO INTERRUPT OPERATION
When the SIO converting successfully, the SIOIRQ will be set to “1” no matter the SIOIEN is enable or disable. If the
SIOIEN and the trigger event SIOIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
SIOIEN = 0, the trigger event SIOIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the SIOIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: SIO interrupt request setup.
B0BSET
B0BCLR
B0BSET
¾
FSIOIEN
FSIOIRQ
FGIE
; Enable SIO interrupt service
; Clear SIO interrupt request flag
; Enable GIE
Example: SIO interrupt service routine.
ORG
JMP
8
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FSIOIRQ
EXIT_INT
; Check SIOIRQ
; SIOIRQ = 0, exit interrupt vector
B0BCLR
…
…
FSIOIRQ
; Reset SIOIRQ
; SIO interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.14 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
Trigger Event Description
P00IRQ
P0.0 trigger controlled by PEDGE
T0IRQ
T0C overflow
T1IRQ
T1C overflow
USBIRQ
USB process finished
WAEKIRQ
I/O port0 & port1 wakeup MCU
SIOIRQ
SIO process finished
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
¾
Example: Check the interrupt request under multi-interrupt operation
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
INTP00CHK:
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTT0CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FT0IEN
INTT1CHK
FT0IRQ
INTT0
B0BTS1
JMP
B0BTS0
JMP
FT1IEN
INTTC1CHK
FT1IRQ
INTT1
B0BTS1
JMP
B0BTS0
JMP
FUSBIEN
INTWAKECHK
FUSBIRQ
INTUSB
B0BTS1
JMP
B0BTS0
JMP
FWAKEIEN
INTSIOCHK
FWAKEIRQ
INTWAKEUP
B0BTS1
JMP
B0BTS0
JMP
FSIOIEN
INT_EXIT
FSIOIRQ
INTSIO
INTT0CHK:
INTT1CHK:
INTUSBCHK:
INTWAKECHK:
INTSIOCHK:
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Check T0 interrupt request
; Check T0IEN
; Jump check to next interrupt
; Check T0IRQ
; Jump to T0 interrupt service routine
; Check T1 interrupt request
; Check T1IEN
; Jump check to next interrupt
; Check T1IRQ
; Jump to T1 interrupt service routine
; Check USB interrupt request
; Check USBIEN
; Jump check to next interrupt
; Check USBIRQ
; Jump to USB interrupt service routine
; Check USB interrupt request
; Check WAKEIEN
; Jump check to next interrupt
; Check WAKEIRQ
; Jump to WAKEUP interrupt service routine
; Check SIO interrupt request
; Check SIOIEN
; Jump check to next interrupt
; Check SIOIRQ
; Jump to SIO interrupt service routine
INT_EXIT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
SONiX TECHNOLOGY CO., LTD
Page 69
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
7
I/O PORT
7.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
0B8H
P0M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P03M
R/W
0
Bit 2
P02M
R/W
0
Bit 1
P01M
R/W
0
Bit 0
P00M
R/W
0
0C1H
P1M
Read/Write
After reset
Bit 7
P17M
R/W
0
Bit 6
P16M
R/W
0
Bit 5
P15M
R/W
0
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P11M
R/W
0
Bit 0
P10M
R/W
0
0C2H
P2M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25M
R/W
0
Bit 4
P24M
R/W
0
Bit 3
P23M
R/W
0
Bit 2
P22M
R/W
0
Bit 1
P21M
R/W
0
Bit 0
P20M
R/W
0
0C5H
P5M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54M
R/W
0
Bit 3
P53M
R/W
0
Bit 2
P52M
R/W
0
Bit 1
P51M
R/W
0
Bit 0
P50M
R/W
0
Bit[7:0]
PnM[7:0]: Pn mode control bits. (n = 0~3).
0 = Pn is input mode.
1 = Pn is output mode.
Note:
1. Users can program them by bit control instructions (B0BSET, B0BCLR).
2. P0.4 is input only pin, so there is no P0.4 mode control bit.
¾
Example: I/O mode selecting
CLR
CLR
CLR
P0M
P1M
P5M
; Set all ports to be input mode.
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0M, A
P1M, A
P5M, A
; Set all ports to be output mode.
B0BCLR
P1M.2
; Set P1.2 to be input mode.
B0BSET
P1M.2
; Set P1.2 to be output mode.
SONiX TECHNOLOGY CO., LTD
Page 70
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
7.2 I/O PULL UP REGISTER
0E0H
P0UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P03R
W
0
Bit 2
P02R
W
0
Bit 1
P01R
W
0
Bit 0
P00R
W
0
0E1H
P1UR
Read/Write
After reset
Bit 7
P17R
W
0
Bit 6
P16R
W
0
Bit 5
P15R
W
0
Bit 4
P16R
W
0
Bit 3
P13R
W
0
Bit 2
P12R
W
0
Bit 1
P11R
W
0
Bit 0
P10R
W
0
0E2H
P2UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25R
W
0
Bit 4
P24R
W
0
Bit 3
P23R
W
0
Bit 2
P22R
W
0
Bit 1
P21R
W
0
Bit 0
P20R
W
0
0E5H
P5UR
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54R
W
0
Bit 3
P53R
W
0
Bit 2
P52R
W
0
Bit 1
P51R
W
0
Bit 0
P50R
W
0
Note: P0.4 is input only pin with pull-up resister.
¾
Example: I/O Pull up Register
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0UR, A
P1UR, A
P5UR, A
SONiX TECHNOLOGY CO., LTD
; Enable Port0, 1, 5 Pull-up register,
;
Page 71
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
7.3 I/O PORT DATA REGISTER
0D0H
P0
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P04
R
0
Bit 3
P03
R/W
0
Bit 2
P02
R/W
0
Bit 1
P01
R/W
0
Bit 0
P00
R/W
0
0D1H
P1
Read/Write
After reset
Bit 7
P17
R/W
0
Bit 6
P16
R/W
0
Bit 5
P15
R/W
0
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
0D2H
P2
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
P25
R/W
0
Bit 4
P24
R/W
0
Bit 3
P23
R/W
0
Bit 2
P22
R/W
0
Bit 1
P21
R/W
0
Bit 0
P20
R/W
0
0D5H
P5
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
P54
R/W
0
Bit 3
P53
R/W
0
Bit 2
P52
R/W
0
Bit 1
P51
R/W
0
Bit 0
P50
R/W
0
Note: The P0.4 keeps “1” when external reset enable by code option.
¾
Example: Read data from input port.
B0MOV
A, P0
B0MOV
A, P1
B0MOV
A, P5
¾
¾
Example: Write data to output port.
MOV
A, #0FFH
B0MOV
P0, A
B0MOV
P1, A
B0MOV
P5, A
Example: Write one bit data to output port.
B0BSET
P1.3
B0BSET
P5.3
B0BCLR
B0BCLR
P1.3
P5.3
SONiX TECHNOLOGY CO., LTD
; Read data from Port 0
; Read data from Port 1
; Read data from Port 5
; Write data FFH to all Port.
; Set P1.3 and P5.3 to be “1”.
; Set P1.3 and P5.3 to be “0”.
Page 72
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
7.4 I/O PORT1 WAKEUP CONTROL REGISTER
0C0H
P1W
Read/Write
After reset
Bit [7:0]
Bit 7
P17W
R/W
0
Bit 6
P16W
R/W
0
Bit 5
P15W
R/W
0
Bit 4
P14W
R/W
0
Bit 3
P13W
R/W
0
Bit 2
P12W
R/W
0
Bit 1
P11W
R/W
0
Bit 0
P10W
R/W
0
P1nW: Port 1 wakeup function control bit.
0 = Disable port 1 wakeup function.
1 = Enable port 1 wakeup function.
SONiX TECHNOLOGY CO., LTD
Page 73
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (24KHz).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD
5V
Internal Low RC Freq.
24KHz
Watchdog Overflow Time
341ms
Note: If watchdog is “Always_On” mode, it keeps running event under power down mode or green
mode.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR
Read/Write
W
W
W
W
W
W
W
After reset
0
0
0
0
0
0
0
Bit 0
WDTR0
W
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the
main routine of the program.
Main:
MOV
B0MOV
…
CALL
CALL
…
…
…
JMP
A,#5AH
WDTR,A
; Clear the watchdog timer.
SUB1
SUB2
MAIN
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
Watchdog timer application note is as following.
z
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
z
z
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
¾
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
Err:
…
…
JMP $
; Check I/O.
; Check RAM
; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
B0BSET
…
CALL
CALL
…
…
…
JMP
FWDRST
; I/O and RAM are correct. Clear watchdog timer and
; execute program.
; Only one clearing watchdog timer of whole program.
SUB1
SUB2
MAIN
SONiX TECHNOLOGY CO., LTD
Page 75
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purpose of the T0 timer is as following.
)
)
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by
T0 time out.
T0 Rate
(Fcpu/2~Fcpu/256)
Internal Data Bus
T0ENB
Load
Fcpu
T0C 8-Bit Binary Up Counting Counter
T0 Time Out
CPUM0,1
8.2.2 T0M MODE REGISTER
0D8H
T0M
Read/Write
After reset
Bit 7
T0ENB
R/W
0
Bit 6
T0rate2
R/W
0
Bit 5
T0rate1
R/W
0
Bit [6:4]
T0RATE[2:0]: T0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
T0ENB: T0 counter control bit.
0 = Disable T0 timer.
1 = Enable T0 timer.
SONiX TECHNOLOGY CO., LTD
Bit 4
T0rate0
R/W
0
Page 76
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H
T0C
Read/Write
After reset
Bit 7
T0C7
R/W
0
Bit 6
T0C6
R/W
0
Bit 5
T0C5
R/W
0
Bit 4
T0C4
R/W
0
Bit 3
T0C3
R/W
0
Bit 2
T0C2
R/W
0
Bit 1
T0C1
R/W
0
Bit 0
T0C0
R/W
0
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example: To set 1ms interval time for T0 interrupt. High clock is 12MHz. Fcpu=Fosc/2. Select T0RATE=010
(Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10-3 * 6 * 106 / 1 / 64)
= 162
= A2H
The basic timer table interval time of T0.
High speed mode (Fcpu = 12MHz / 2)
T0RATE
T0CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
10.923 ms
42.67 us
001
Fcpu/128
5.461 ms
21.33 us
010
Fcpu/64
2.731 ms
10.67 us
011
Fcpu/32
1.365 ms
5.33 us
100
Fcpu/16
0.683 ms
2.67 us
101
Fcpu/8
0.341 ms
1.33 us
110
Fcpu/4
0.171 ms
0.67 us
111
Fcpu/2
0.085 ms
0.33 us
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
)
Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
)
)
FT0ENB
FT0IEN
FT0IRQ
; T0 timer.
; T0 interrupt function is disabled.
; T0 interrupt request flag is cleared.
MOV
A, #0xxx0000b
B0MOV
T0M,A
;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
; T0 timer is disabled.
Set T0 timer rate.
Set T0 interrupt interval time.
MOV
B0MOV
)
; Set T0C value.
FT0IEN
; Enable T0 interrupt function.
FT0ENB
; Enable T0 timer.
Set T0 timer function mode.
B0BSET
)
A,#7FH
T0C,A
Enable T0 timer.
B0BSET
SONiX TECHNOLOGY CO., LTD
Page 78
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.3 TIMER T1 (T1)
8.3.1 OVERVIEW
The T1 is an 16-bit binary up timer and event counter. If T1 timer occurs an overflow (from FFFFH to 0000H), it will
continue counting and issue a time-out signal to trigger T1 interrupt to request interrupt service.
The main purpose of the T1 timer is as following.
)
)
16-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
Green mode wakeup function: T1 can be green mode wake-up time as T1ENB = 1. System will be wake-up by
T1 time out.
T1 Rate
(Fcpu/2~Fcpu/256)
Internal Data Bus
T1ENB
Load
Fcpu
T1C 16-Bit Binary Up Counting Counter
T1 Time Out
CPUM0,1
8.3.2 T1M MODE REGISTER
0DAH
T1M
Read/Write
After reset
Bit 7
T1ENB
R/W
0
Bit 6
T1rate2
R/W
0
Bit 5
T1rate1
R/W
0
Bit [6:4]
T1RATE[2:0]: T1 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
T1ENB: T1 counter control bit.
0 = Disable T1 timer.
1 = Enable T1 timer.
SONiX TECHNOLOGY CO., LTD
Bit 4
T1rate0
R/W
0
Page 79
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.3.3 T1C COUNTING REGISTER
T1C_L with T1C_H is an 16-bit counter register for T1 interval time control.
0DBH
T1C_L
Read/Write
After reset
Bit 7
T1C7
R/W
0
Bit 6
T1C6
R/W
0
Bit 5
T1C5
R/W
0
Bit 4
T1C4
R/W
0
Bit 3
T1C3
R/W
0
Bit 2
T1C2
R/W
0
Bit 1
T1C1
R/W
0
Bit 0
T1C0
R/W
0
0DCH
T1C_H
Read/Write
After reset
Bit 7
T1C15
R/W
0
Bit 6
T1C14
R/W
0
Bit 5
T1C13
R/W
0
Bit 4
T1C12
R/W
0
Bit 3
T1C11
R/W
0
Bit 2
T1C10
R/W
0
Bit 1
T1C9
R/W
0
Bit 0
T1C8
R/W
0
The equation of T1C initial value is as following.
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
Example: To set 1ms interval time for T1 interrupt. High clock is 12MHz. Fcpu=Fosc/2. Select T1RATE=001
(Fcpu/128).
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
= 65536 - (1s * 12MHz / 2 / 128)
= 65536 - (10 * 6 * 106 / 1 / 128)
= 18661
= 48E5H
The basic timer table interval time of T1.
High speed mode (Fcpu = 12MHz / 2)
T1RATE
T1CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
2.796 s
42.67 us
001
Fcpu/128
1.398 s
21.33 us
010
Fcpu/64
699.051 ms
10.67 us
011
Fcpu/32
349.525 ms
5.33 us
100
Fcpu/16
174.763 ms
2.67 us
101
Fcpu/8
87.381 ms
1.33 us
110
Fcpu/4
43.691 ms
0.67 us
111
Fcpu/2
21.845 ms
0.33 us
SONiX TECHNOLOGY CO., LTD
Page 80
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.3.4 T1 TIMER OPERATION SEQUENCE
T1 timer operation sequence of setup T1 timer is as following.
)
Stop T1 timer counting, disable T1 interrupt function and clear T1 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
)
)
FT1ENB
FT1IEN
FT1IRQ
; T1 timer.
; T1 interrupt function is disabled.
; T1 interrupt request flag is cleared.
MOV
A, #0xxx0000b
B0MOV
T1M,A
;The T1 rate control bits exist in bit4~bit6 of T1M. The
; value is from x000xxxxb~x111xxxxb.
; T1 timer is disabled.
Set T1 timer rate.
Set T1 interrupt interval time.
MOV
B0MOV
MOV
B0MOV
)
; Set T1C_L value.
; Set T1C_H value.
Set T1 timer function mode.
B0BSET
)
A,#0E5H
T1C_L,A
A,#48H
T1C_H,A
FT1IEN
; Enable T1 interrupt function.
FT1ENB
; Enable T1 timer.
Enable T1 timer.
B0BSET
SONiX TECHNOLOGY CO., LTD
Page 81
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.4 TIMER/COUNTER 0 (TC0)
8.4.1 OVERVIEW
The TC0 is an 8-bit binary up counting timer with double buffers. TC0 has two clock sources including internal clock
and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT0 from
P0.0 pin (Falling edge trigger). Using TC0M register selects TC0C’s clock source from internal or external. If TC0 timer
occurs an overflow, it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt
service. TC0 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC0 overflow is decided by PWM cycle
controlled by ALOAD0 and TC0OUT bits.
The main purposes of the TC0 timer is as following.
)
)
)
)
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT0 input pin.
Buzzer output
PWM output
TC0OUT
Internal P5.4 I/O Circuit
Up Counting
Reload Value
ALOAD0
Buzzer
Auto. Reload
TC0 Time Out
TC0R Reload
Data Buffer
R
TC0CKS
Compare
TC0ENB
P5.4
ALOAD0, TC0OUT
TC0 Rate
(Fcpu/2~Fcpu/256)
Fcpu
TC0 / 2
PWM0OUT
PWM
S
Load
TC0C
8-Bit Binary Up
Counting Counter
TC0 Time Out
INT0
(Schmitter Trigger)
CPUM0,1
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Page 82
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.4.2 TC0M MODE REGISTER
088H
TC0M
Read/Write
After reset
Bit 7
TC0ENB
R/W
0
Bit 6
TC0rate2
R/W
0
Bit 5
TC0rate1
R/W
0
Bit 4
TC0rate0
R/W
0
Bit 3
TC0CKS
R/W
0
Bit 2
ALOAD0
R/W
0
Bit 1
TC0OUT
R/W
0
Bit 0
PWM0OUT: PWM output control bit.
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC0OUT, ALOAD0 bits.
Bit 1
TC0OUT: TC0 time out toggle signal output control bit. Only valid when PWM0OUT = 0.
0 = Disable, P5.4 is I/O function.
1 = Enable, P5.4 is output TC0OUT signal.
Bit 2
ALOAD0: Auto-reload control bit. Only valid when PWM0OUT = 0.
0 = Disable TC0 auto-reload function.
1 = Enable TC0 auto-reload function.
Bit 3
TC0CKS: TC0 clock source select bit.
0 = Internal clock (Fcpu or Fosc).
1 = External clock from P0.0/INT0 pin.
Bit [6:4]
TC0RATE[2:0]: TC0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
TC0ENB: TC0 counter control bit.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
Bit 0
PWM0OUT
R/W
0
Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0
interrupt request will be raised. (P0.0IRQ will be always 0).
SONiX TECHNOLOGY CO., LTD
Page 83
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.4.3 TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for TC0 interval time control.
089H
TC0C
Read/Write
After reset
Bit 7
TC0C7
R/W
0
Bit 6
TC0C6
R/W
0
Bit 5
TC0C5
R/W
0
Bit 4
TC0C4
R/W
0
Bit 3
TC0C3
R/W
0
Bit 2
TC0C2
R/W
0
Bit 1
TC0C1
R/W
0
Bit 0
TC0C0
R/W
0
The equation of TC0C initial value is as following.
TC0C initial value = N - (TC0 interrupt interval time * input clock)
N is TC0 overflow boundary number. TC0 timer overflow time has six types (TC0 timer, TC0 event counter, TC0 Fcpu
clock source, TC0 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC0 overflow time
and valid value as follow table.
TC0CKS PWM0 ALOAD0 TC0OUT
0
1
¾
0
1
1
1
1
-
x
0
0
1
1
-
x
0
1
0
1
-
N
256
256
64
32
16
256
TC0C valid
value
0x00~0xFF
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
TC0C value
binary type
00000000b~11111111b
00000000b~11111111b
xx000000b~xx111111b
xxx00000b~xxx11111b
xxxx0000b~xxxx1111b
00000000b~11111111b
Remark
Overflow per 256 count
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
Overflow per 256 count
Example: To set 1ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC0RATE=010 (Fcpu/64).
TC0C initial value = N - (TC0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10-3 * 6 * 106 / 1 / 64)
= 162
= A2H
The basic timer table interval time of TC0.
High speed mode (Fcpu = 6MHz / 1)
TC0RATE TC0CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
10.923 ms
42.67 us
001
Fcpu/128
5.461 ms
21.33 us
010
Fcpu/64
2.731 ms
10.67 us
011
Fcpu/32
1.365 ms
5.33 us
100
Fcpu/16
0.683 ms
2.67 us
101
Fcpu/8
0.341 ms
1.33 us
110
Fcpu/4
0.171 ms
0.67 us
111
Fcpu/2
0.085 ms
0.33 us
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8.4.4 TC0R AUTO-LOAD REGISTER
TC0 timer is with auto-load function controlled by ALOAD0 bit of TC0M. When TC0C overflow occurring, TC0R value
will load to TC0C by system. It is easy to generate an accurate time, and users don’t reset TC0C during interrupt
service routine.
TC0 is double buffer design. If new TC0R value is set by program, the new value is stored in 1st buffer. Until TC0
overflow occurs, the new value moves to real TC0R buffer. This way can avoid TC0 interval time error and glitch in
PWM and Buzzer output.
Note: Under PWM mode, auto-load is enabled automatically. The ALOAD0 bit is selecting overflow
boundary.
08AH
TC0R
Read/Write
After reset
Bit 7
TC0R7
W
0
Bit 6
TC0R6
W
0
Bit 5
TC0R5
W
0
Bit 4
TC0R4
W
0
Bit 3
TC0R3
W
0
Bit 2
TC0R2
W
0
Bit 1
TC0R1
W
0
Bit 0
TC0R0
W
0
The equation of TC0R initial value is as following.
TC0R initial value = N - (TC0 interrupt interval time * input clock)
N is TC0 overflow boundary number. TC0 timer overflow time has six types (TC0 timer, TC0 event counter, TC0 Fcpu
clock source, TC0 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC0 overflow time
and valid value as follow table.
TC0CKS PWM0 ALOAD0 TC0OUT
0
1
¾
0
1
1
1
1
-
x
0
0
1
1
-
x
0
1
0
1
-
N
256
256
64
32
16
256
TC0R valid
value
0x00~0xFF
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
TC0R value
binary type
00000000b~11111111b
00000000b~11111111b
xx000000b~xx111111b
xxx00000b~xxx11111b
xxxx0000b~xxxx1111b
00000000b~11111111b
Example: To set 1ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC0RATE=010 (Fcpu/64).
TC0R initial value = N - (TC0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10-3 * 6 * 106 / 1 / 64)
= 162
= A2H
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8.4.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC0OUT) is from TC0 timer/counter frequency output function. By setting the TC0 clock frequency, the
clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0OUT frequency is
divided by 2 from TC0 interval time. TC0OUT frequency is 1/2 TC0 frequency. The TC0 clock has many combinations
and easily to make difference frequency. The TC0OUT frequency waveform is as following.
1
2
3
4
TC0 Overflow Clock
1
2
3
4
TC0OUT (Buzzer) Output Clock
¾
Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The
TC0OUT frequency is 0.5KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 1KHz. The
TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110.
TC0C = TC0R = 131.
MOV
B0MOV
A,#01100000B
TC0M,A
MOV
B0MOV
B0MOV
A,#131
TC0C,A
TC0R,A
; Set the auto-reload reference value
B0BSET
B0BSET
B0BSET
FTC0OUT
FALOAD1
FTC0ENB
; Enable TC0 output to P5.4 and disable P5.4 I/O function
; Enable TC0 auto-reload function
; Enable TC0 timer
; Set the TC0 rate to Fcpu/4
Note: Buzzer output is enable, and “PWM0OUT” must be “0”.
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8.4.6 TC0 TIMER OPERATION SEQUENCE
TC0 timer operation includes timer interrupt, event counter, TC0OUT and PWM. The sequence of setup TC0 timer is
as following.
)
)
Stop TC0 timer counting, disable TC0 interrupt function and clear TC0 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
)
)
FTC0ENB
FTC0IEN
FTC0IRQ
Set TC0 timer rate. (Besides event counter mode.)
MOV
A, #0xxx0000b
B0MOV
TC0M,A
;The TC0 rate control bits exist in bit4~bit6 of TC0M. The
; value is from x000xxxxb~x111xxxxb.
; TC0 interrupt function is disabled.
Set TC0 timer clock source.
; Select TC0 internal / external clock source.
B0BCLR
FTC0CKS
or
B0BSET
FTC0CKS
)
; TC0 timer, TC0OUT and PWM stop.
; TC0 interrupt function is disabled.
; TC0 interrupt request flag is cleared.
; Select TC0 internal clock source.
; Select TC0 external clock source.
Set TC0 timer auto-load mode.
B0BCLR
FALOAD0
; Enable TC0 auto reload function.
B0BSET
FALOAD0
; Disable TC0 auto reload function.
or
)
Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty cycle.
; Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty.
MOV
A,#7FH
; TC0C and TC0R value is decided by TC0 mode.
B0MOV
TC0C,A
; Set TC0C value.
B0MOV
TC0R,A
; Set TC0R value under auto reload mode or PWM mode.
; In PWM mode, set PWM cycle.
B0BCLR
B0BCLR
or
B0BCLR
B0BSET
or
B0BSET
B0BCLR
or
B0BSET
B0BSET
)
FALOAD0
FTC0OUT
; ALOAD0, TC0OUT = 00, PWM cycle boundary is
; 0~255.
FALOAD0
FTC0OUT
; ALOAD0, TC0OUT = 01, PWM cycle boundary is
; 0~63.
FALOAD0
FTC0OUT
; ALOAD0, TC0OUT = 10, PWM cycle boundary is
; 0~31.
FALOAD0
FTC0OUT
; ALOAD0, TC0OUT = 11, PWM cycle boundary is
; 0~15.
Set TC0 timer function mode.
B0BSET
FTC0IEN
; Enable TC0 interrupt function.
B0BSET
FTC0OUT
; Enable TC0OUT (Buzzer) function.
B0BSET
FPWM0OUT
; Enable PWM function.
FTC0ENB
; Enable TC0 timer.
or
or
)
Enable TC0 timer.
B0BSET
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8.5 PWM0 MODE
8.5.1 OVERVIEW
PWM function is generated by TC0 timer counter and output the PWM signal to PWM0OUT pin (P5.4). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD0, TC0OUT bits. The value of the 8-bit counter (TC0C) is
compared to the contents of the reference register (TC0R). When the reference register value (TC0R) is equal to the
counter value (TC0C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM0 output is TC0R/256, 64, 32, 16.
PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to
change the PWM’s duty cycle is to modify the TC0R.
Note: TC0 is double buffer design. Modifying TC0R to change PWM duty by program, there is no glitch
and error duty signal in PWM output waveform. Users can change TC0R any time, and the new reload
value is loaded to TC0R buffer at TC0 overflow.
ALOAD0 TC0OUT PWM duty range
0
0
1
1
0
1
0
1
TC0C valid value TC0R valid bits value
0/256~255/256
0/64~63/64
0/32~31/32
0/16~15/16
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
MAX. PWM
Frequency
(Fcpu = 6MHz)
11.719K
46.875K
93.75K
187.5K
Remark
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256.
0
1
128
……
……
254
255
0
1
……
128
……
254
255
TC0 Clock
TC0R=00H
Low
High
TC0R=01H
TC0R=80H
TC0R=FFH
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Low
High
Low
High
Low
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
8.5.2 TCxIRQ and PWM Duty
In PWM mode, the frequency of TC0IRQ is depended on PWM duty range. From following diagram, the TC0IRQ
frequency is related with PWM duty.
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~255)
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~63)
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~31)
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~15)
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8.5.3 PWM Duty with TCxR Changing
In PWM mode, the system will compare TC0C and TC0R all the time. When TC0C<TC0R, the PWM will output logic
“High”, when TC0C≧TC0R, the PWM will output logic “Low”. If TC0C is changed in certain period, the PWM duty will
change in next PWM period. If TC0R is fixed all the time, the PWM waveform is also the same.
TC0C = TC0R
TC0C overflow
and TC0IRQ set
0xFF
TC0C Value
0x00
PWM0 Output
Period
1
2
3
4
5
6
7
Above diagram is shown the waveform with fixed TC0R. In every TC0C overflow PWM output “High, when
TC0C≧TC0R PWM output ”Low”. If TC0R is changing in the program processing, the PWM waveform will became as
following diagram.
TC0C < TC0R
PWM Low > High
TC0C > = TC0R
PWM High > Low
TC0C overflow
and TC0IRQ set
Update New TC0R!
Old TC0R < TC0C < New TC0R
0xFF
Old TC0R
Update New TC0R!
New TC0R < TC0C < Old TC0R
New TC0R
New TC0R
Old TC0R
TC0C Value
0x00
PWM0 Output
Period
1
1st PWM
2
Update PWM Duty
3
2nd PWM
4
Update PWM Duty
5
3th PWM
In period 2 and period 4, new Duty (TC0R) is set. TC0 is double buffer design. The PWM still keeps the same duty in
period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not
changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.
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8.5.4 PWM PROGRAM EXAMPLE
¾
Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The clock source is internal 6MHz. Fcpu =
Fosc/1. The duty of PWM is 30/256. The PWM frequency is about 6KHz. The PWM clock source is from
external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 30.
MOV
B0MOV
A,#01100000B
TC0M,A
MOV
B0MOV
B0MOV
A,#30
TC0C,A
TC0R,A
; Set the PWM duty to 30/256
B0BCLR
B0BCLR
B0BSET
B0BSET
FTC0OUT
FALOAD0
FPWM0OUT
FTC0ENB
; Set duty range as 0/256~255/256.
; Set the TC0 rate to Fcpu/4
; Enable PWM0 output to P5.4 and disable P5.4 I/O function
; Enable TC0 timer
Note: The TC0R is write-only register. Don’t process them using INCMS, DECMS instructions.
¾
Example: Modify TC0R registers’ value.
MOV
B0MOV
A, #30H
TC0R, A
; Input a number using B0MOV instruction.
INCMS
NOP
B0MOV
B0MOV
BUF0
; Get the new TC0R value from the BUF0 buffer defined by
; programming.
A, BUF0
TC0R, A
Note: The PWM can work with interrupt request.
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8.6 TIMER/COUNTER 1 (TC1)
8.6.1 OVERVIEW
The TC1 is an 8-bit binary up counting timer with double buffers. TC1 has two clock sources including internal clock
and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT0 from
P0.0 pin (Falling edge trigger). Using TC1M register selects TC1C’s clock source from internal or external. If TC1 timer
occurs an overflow, it will continue counting and issue a time-out signal to trigger TC1 interrupt to request interrupt
service. TC1 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC1 overflow is decided by PWM cycle
controlled by ALOAD0 and TC1OUT bits.
The main purposes of the TC1 timer is as following.
)
)
)
)
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT0 input pin.
Buzzer output
PWM output
TC0OUT
Internal P5.4 I/O Circuit
Up Counting
Reload Value
ALOAD0
Buzzer
Auto. Reload
TC0 Time Out
TC0R Reload
Data Buffer
R
TC0CKS
Compare
TC0ENB
P5.4
ALOAD0, TC0OUT
TC0 Rate
(Fcpu/2~Fcpu/256)
Fcpu
TC0 / 2
PWM0OUT
PWM
S
Load
TC0C
8-Bit Binary Up
Counting Counter
TC0 Time Out
INT0
(Schmitter Trigger)
CPUM0,1
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8.6.2 TC1M MODE REGISTER
08BH
TC1M
Read/Write
After reset
Bit 7
TC1ENB
R/W
0
Bit 6
TC1rate2
R/W
0
Bit 5
TC1rate1
R/W
0
Bit 4
TC1rate0
R/W
0
Bit 3
TC1CKS
R/W
0
Bit 2
ALOAD0
R/W
0
Bit 1
TC1OUT
R/W
0
Bit 0
PWM0OUT: PWM output control bit.
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC1OUT, ALOAD0 bits.
Bit 1
TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM0OUT = 0.
0 = Disable, P5.3 is I/O function.
1 = Enable, P5.3 is output TC1OUT signal.
Bit 2
ALOAD0: Auto-reload control bit. Only valid when PWM0OUT = 0.
0 = Disable TC1 auto-reload function.
1 = Enable TC1 auto-reload function.
Bit 3
TC1CKS: TC1 clock source select bit.
0 = Internal clock (Fcpu or Fosc).
1 = External clock from P0.0/INT0 pin.
Bit [6:4]
TC1RATE[2:0]: TC1 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7
TC1ENB: TC1 counter control bit.
0 = Disable TC1 timer.
1 = Enable TC1 timer.
Bit 0
PWM0OUT
R/W
0
Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.0
interrupt request will be raised. (P0.0IRQ will be always 0).
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8.6.3 TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for TC1 interval time control.
08CH
TC1C
Read/Write
After reset
Bit 7
TC1C7
R/W
0
Bit 6
TC1C6
R/W
0
Bit 5
TC1C5
R/W
0
Bit 4
TC1C4
R/W
0
Bit 3
TC1C3
R/W
0
Bit 2
TC1C2
R/W
0
Bit 1
TC1C1
R/W
0
Bit 0
TC1C0
R/W
0
The equation of TC1C initial value is as following.
TC1C initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time
and valid value as follow table.
TC1CKS PWM0 ALOAD0 TC1OUT
0
1
¾
0
1
1
1
1
-
x
0
0
1
1
-
x
0
1
0
1
-
N
256
256
64
32
16
256
TC1C valid
value
0x00~0xFF
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
TC1C value
binary type
00000000b~11111111b
00000000b~11111111b
xx000000b~xx111111b
xxx00000b~xxx11111b
xxxx0000b~xxxx1111b
00000000b~11111111b
Remark
Overflow per 256 count
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
Overflow per 256 count
Example: To set 1ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC1RATE=010 (Fcpu/64).
TC1C initial value = N - (TC1 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10-3 * 6 * 106 / 1 / 64)
= 162
= A2H
The basic timer table interval time of TC1.
High speed mode (Fcpu = 6MHz / 1)
TC1RATE TC1CLOCK
Max overflow interval One step = max/256
000
Fcpu/256
10.923 ms
42.67 us
001
Fcpu/128
5.461 ms
21.33 us
010
Fcpu/64
2.731 ms
10.67 us
011
Fcpu/32
1.365 ms
5.33 us
100
Fcpu/16
0.683 ms
2.67 us
101
Fcpu/8
0.341 ms
1.33 us
110
Fcpu/4
0.171 ms
0.67 us
111
Fcpu/2
0.085 ms
0.33 us
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8.6.4 TC1R AUTO-LOAD REGISTER
TC1 timer is with auto-load function controlled by ALOAD0 bit of TC1M. When TC1C overflow occurring, TC1R value
will load to TC1C by system. It is easy to generate an accurate time, and users don’t reset TC1C during interrupt
service routine.
TC1 is double buffer design. If new TC1R value is set by program, the new value is stored in 1st buffer. Until TC1
overflow occurs, the new value moves to real TC1R buffer. This way can avoid TC1 interval time error and glitch in
PWM and Buzzer output.
Note: Under PWM mode, auto-load is enabled automatically. The ALOAD0 bit is selecting overflow
boundary.
08DH
TC1R
Read/Write
After reset
Bit 7
TC1R7
W
0
Bit 6
TC1R6
W
0
Bit 5
TC1R5
W
0
Bit 4
TC1R4
W
0
Bit 3
TC1R3
W
0
Bit 2
TC1R2
W
0
Bit 1
TC1R1
W
0
Bit 0
TC1R0
W
0
The equation of TC1R initial value is as following.
TC1R initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time
and valid value as follow table.
TC1CKS PWM0 ALOAD0 TC1OUT
0
1
¾
0
1
1
1
1
-
x
0
0
1
1
-
x
0
1
0
1
-
N
256
256
64
32
16
256
TC1R valid
value
0x00~0xFF
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
TC1R value
binary type
00000000b~11111111b
00000000b~11111111b
xx000000b~xx111111b
xxx00000b~xxx11111b
xxxx0000b~xxxx1111b
00000000b~11111111b
Example: To set 1ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC1RATE=010 (Fcpu/64).
TC1R initial value = N - (TC1 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10-3 * 6 * 106 / 1 / 64)
= 162
= A2H
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8.6.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC1OUT) is from TC1 timer/counter frequency output function. By setting the TC1 clock frequency, the
clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC1OUT frequency is
divided by 2 from TC1 interval time. TC1OUT frequency is 1/2 TC1 frequency. The TC1 clock has many combinations
and easily to make difference frequency. The TC1OUT frequency waveform is as following.
1
2
3
4
TC1 Overflow Clock
1
2
3
4
TC1OUT (Buzzer) Output Clock
¾
Example: Setup TC1OUT output from TC1 to TC1OUT (P5.4). The external high-speed clock is 4MHz. The
TC1OUT frequency is 0.5KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 1KHz. The
TC1 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110.
TC1C = TC1R = 131.
MOV
B0MOV
A,#01100000B
TC1M,A
MOV
B0MOV
B0MOV
A,#131
TC1C,A
TC1R,A
; Set the auto-reload reference value
B0BSET
B0BSET
B0BSET
FTC1OUT
FALOAD1
FTC1ENB
; Enable TC1 output to P5.4 and disable P5.4 I/O function
; Enable TC1 auto-reload function
; Enable TC1 timer
; Set the TC1 rate to Fcpu/4
Note: Buzzer output is enable, and “PWM0OUT” must be “0”.
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8.6.6 TC1 TIMER OPERATION SEQUENCE
TC1 timer operation includes timer interrupt, event counter, TC1OUT and PWM. The sequence of setup TC1 timer is
as following.
)
)
Stop TC1 timer counting, disable TC1 interrupt function and clear TC1 interrupt request flag.
B0BCLR
B0BCLR
B0BCLR
)
)
FTC1ENB
FTC1IEN
FTC1IRQ
Set TC1 timer rate. (Besides event counter mode.)
MOV
A, #0xxx0000b
B0MOV
TC1M,A
;The TC1 rate control bits exist in bit4~bit6 of TC1M. The
; value is from x000xxxxb~x111xxxxb.
; TC1 interrupt function is disabled.
Set TC1 timer clock source.
; Select TC1 internal / external clock source.
B0BCLR
FTC1CKS
or
B0BSET
FTC1CKS
)
; TC1 timer, TC1OUT and PWM stop.
; TC1 interrupt function is disabled.
; TC1 interrupt request flag is cleared.
; Select TC1 internal clock source.
; Select TC1 external clock source.
Set TC1 timer auto-load mode.
B0BCLR
FALOAD0
; Enable TC1 auto reload function.
B0BSET
FALOAD0
; Disable TC1 auto reload function.
or
)
Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty cycle.
; Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty.
MOV
A,#7FH
; TC1C and TC1R value is decided by TC1 mode.
B0MOV
TC1C,A
; Set TC1C value.
B0MOV
TC1R,A
; Set TC1R value under auto reload mode or PWM mode.
; In PWM mode, set PWM cycle.
B0BCLR
B0BCLR
or
B0BCLR
B0BSET
or
B0BSET
B0BCLR
or
B0BSET
B0BSET
)
FALOAD0
FTC1OUT
; ALOAD0, TC1OUT = 00, PWM cycle boundary is
; 0~255.
FALOAD0
FTC1OUT
; ALOAD0, TC1OUT = 01, PWM cycle boundary is
; 0~63.
FALOAD0
FTC1OUT
; ALOAD0, TC1OUT = 10, PWM cycle boundary is
; 0~31.
FALOAD0
FTC1OUT
; ALOAD0, TC1OUT = 11, PWM cycle boundary is
; 0~15.
Set TC1 timer function mode.
B0BSET
FTC1IEN
; Enable TC1 interrupt function.
B0BSET
FTC1OUT
; Enable TC1OUT (Buzzer) function.
B0BSET
FPWM0OUT
; Enable PWM function.
FTC1ENB
; Enable TC1 timer.
or
or
)
Enable TC1 timer.
B0BSET
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8.7 PWM1 MODE
8.7.1 OVERVIEW
PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD0, TC1OUT bits. The value of the 8-bit counter (TC1C) is
compared to the contents of the reference register (TC1R). When the reference register value (TC1R) is equal to the
counter value (TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM1 output is TC1R/256, 64, 32, 16.
PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to
change the PWM’s duty cycle is to modify the TC1R.
Note: TC1 is double buffer design. Modifying TC1R to change PWM duty by program, there is no glitch
and error duty signal in PWM output waveform. Users can change TC1R any time, and the new reload
value is loaded to TC1R buffer at TC1 overflow.
ALOAD0 TC1OUT PWM duty range
0
0
1
1
0
1
0
1
MAX. PWM
Frequency
(Fcpu = 6MHz)
11.719K
46.875K
93.75K
187.5K
TC1C valid value TC1R valid bits value
0/256~255/256
0/64~63/64
0/32~31/32
0/16~15/16
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
0x00~0xFF
0x00~0x3F
0x00~0x1F
0x00~0x0F
Remark
Overflow per 256 count
Overflow per 64 count
Overflow per 32 count
Overflow per 16 count
The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256.
0
1
128
……
……
254
255
0
1
……
128
……
254
255
TC1 Clock
TC1R=00H
Low
High
TC1R=01H
TC1R=80H
TC1R=FFH
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Low
High
Low
High
Low
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8.7.2 TCxIRQ and PWM Duty
In PWM mode, the frequency of TC1IRQ is depended on PWM duty range. From following diagram, the TC1IRQ
frequency is related with PWM duty.
TC1 Overflow,
TC1IRQ = 1
0xFF
TC1C Value
0x00
PWM1 Output
(Duty Range 0~255)
TC1 Overflow,
TC1IRQ = 1
0xFF
TC1C Value
0x00
PWM1 Output
(Duty Range 0~63)
TC1 Overflow,
TC1IRQ = 1
0xFF
TC1C Value
0x00
PWM1 Output
(Duty Range 0~31)
TC1 Overflow,
TC1IRQ = 1
0xFF
TC1C Value
0x00
PWM1 Output
(Duty Range 0~15)
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8.7.3 PWM Duty with TCxR Changing
In PWM mode, the system will compare TC1C and TC1R all the time. When TC1C<TC1R, the PWM will output logic
“High”, when TC1C≧TC1R, the PWM will output logic “Low”. If TC1C is changed in certain period, the PWM duty will
change in next PWM period. If TC1R is fixed all the time, the PWM waveform is also the same.
TC1C = TC1R
TC1C overflow
and TC1IRQ set
0xFF
TC1C Value
0x00
PWM1 Output
Period
1
2
3
4
5
6
7
Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when
TC1C≧TC1R PWM output ”Low”. If TC1R is changing in the program processing, the PWM waveform will became as
following diagram.
In period 2 and period 4, new Duty (TC1R) is set. TC1 is double buffer design. The PWM still keeps the same duty in
period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not
changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.
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8.7.4 PWM PROGRAM EXAMPLE
¾
Example: Setup PWM1 output from TC1 to PWM1OUT (P5.4). The clock source is internal 6MHz. Fcpu =
Fosc/1. The duty of PWM is 30/256. The PWM frequency is about 6KHz. The PWM clock source is from
external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 30.
MOV
B0MOV
A,#01100000B
TC1M,A
MOV
B0MOV
B0MOV
A,#30
TC1C,A
TC1R,A
; Set the PWM duty to 30/256
B0BCLR
B0BCLR
B0BSET
B0BSET
FTC1OUT
FALOAD0
FPWM1OUT
FTC1ENB
; Set duty range as 0/256~255/256.
; Set the TC1 rate to Fcpu/4
; Enable PWM1 output to P5.4 and disable P5.4 I/O function
; Enable TC1 timer
Note: The TC1R is write-only register. Don’t process them using INCMS, DECMS instructions.
¾
Example: Modify TC1R registers’ value.
MOV
B0MOV
A, #30H
TC1R, A
; Input a number using B0MOV instruction.
INCMS
NOP
B0MOV
B0MOV
BUF0
; Get the new TC1R value from the BUF0 buffer defined by
; programming.
A, BUF0
TC1R, A
Note: The PWM can work with interrupt request.
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9
UNIVERSAL SERIAL BUS (USB)
9.1 OVERVIEW
The USB is the answer to connectivity for the PC architecture. A fast, bi-directional interrupt pipe, low-cost, dynamically
attachable serial interface is consistent with the requirements of the PC platform of today and tomorrow. The SONIX
USB microcontrollers are optimized for human-interface computer peripherals such as a mouse, joystick, game pad.
USB Specification Compliance
— Conforms to USB specifications, Version 2.0.
— Supports 1 Full-speed USB device address.
— Supports 1 control endpoint, 3 interrupt endpoints.
— Integrated USB transceiver.
— 5V to 3.3V regulator output for D+ 1.5K ohm internal resistor pull up.
9.2 USB MACHINE
The USB machine allows the microcontroller to communicate with the USB host. The hardware handles the following
USB bus activity independently of the microcontroller.
The USB machine will do:
• Translate the encoded received data and format the data to be transmitted on the bus.
• CRC checking and generation by hardware. If CRC is not correct, hardware will not send any response to USB host.
• Send and update the data toggle bit (Data1/0) automatically by hardware.
• Send appropriate ACK/NAK/STALL handshakes.
• SETUP, IN, or OUT Token type identification. Set the appropriate bit once a valid token is received.
• Place valid received data in the appropriate endpoint FIFOs.
• Bit stuffing/unstuffing.
• Address checking. Ignore the transactions not addressed to the device.
• Endpoint checking. Check the endpoint’s request from USB host, and set the appropriate bit of registers.
Firmware is required to handle the rest of the following tasks:
• Coordinate enumeration by decoding USB device requests.
• Fill and empty the FIFOs.
• Suspend/Resume coordination.
• Remote wake up function.
• Determine the right interrupt request of USB communication.
9.3 USB INTERRUPT
The USB function will accept the USB host command and generate the relative interrupts, and the program counter will
go to 0x08 vector. Firmware is required to check the USB status bit to realize what request comes from the USB host.
The USB function interrupt is generated when:
• The endpoint 0 is set to accept a SETUP token.
• The device receives an ACK handshake after a successful read transaction (IN) from the host.
• If the endpoint is in ACK OUT modes, an interrupt is generated when data is received.
• The USB host send USB suspend request to the device.
• USB bus reset event occurs.
• The USB endpoints interrupt after a USB transaction complete is on the bus.
• The SOF packet received if the SOF interrupt enable.
• The NAK handshaking when the NAK interrupt enable.
The following examples show how to avoid the error of reading or writing the endpoint FIFOs and to do the right USB
request routine according to the flag.
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9.4 USB ENUMERATION
A typical USB enumeration sequence is shown below.
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device
descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor
over the USB bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a
new USB address to the device.
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence
completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB
bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
10. Once the device receives a Set Configuration request, its functions may now be used.
11. Firmware should take appropriate action for Endpoint 0~3 transactions, which may occur from this point.
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9.5 USB REGISTERS
9.5.1 USB DEVICE ADDRESS REGISTER
The USB Device Address Register (UDA) contains a 7-bit USB device address and one bit to enable the USB function.
This register is cleared during a reset, setting the USB device address to zero and disable the USB function.
090H
UDA
Read/Write
After reset
Bit [6:0]
Bit 7
Bit 7
UDE
R/W
0
Bit 6
UDA6
R/W
0
Bit 5
UDA5
R/W
0
Bit 4
UDA4
R/W
0
Bit 3
UDA3
R/W
0
Bit 2
UDA2
R/W
0
Bit 1
UDA1
R/W
0
Bit 0
UDA0
R/W
0
UDA [6:0]: These bits must be set by firmware during the USB enumeration process (i.e., SetAddress) to
the non-zero address assigned by the USB host.
UDE: Device Function Enable. This bit must be enabled by firmware to enable the USB device function.
0 = Disable USB device function.
1 = Enable USB device function.
9.5.2 USB STATUS REGISTER
The USB status register indicates the status of USB.
091H
USTATUS
Read/Write
After reset
Bit 7
Bit 6
Bit 5
SOF
R/W
0
Bit 4
BUS_RST
R
0
Bit 3
Bit 2
SUSPEND EP0_SETUP
R
R/W
0
0
Bit 1
EP0_IN
R/W
0
Bit 0
EP0_OUT
R/W
0
Bit 0
EP0_OUT : Endpoint 0 OUT Token Received.
0 = Endpoint 0 has no OUT token received.
1 = A valid OUT packet has been received. The bit is set to 1 after the last received packet in an OUT
transaction.
Bit 1
EP0_IN : Endpoint 0 IN Token Received.
0 = Endpoint 0 has no IN token received.
1 = A valid IN packet has been received. The bit is set to 1 after the last received packet in an IN
transaction.
Bit 2
EP0_SETUP : Endpoint 0 SETUP Token Received.
0 = Endpoint 0 has no SETUP token received.
1 = A valid SETUP packet has been received. The bit is set to 1 after the last received packet in an SETUP
transaction. While the bit is set to 1, the HOST can not write any data in to EP0 FIFO. This prevents SIE
from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data.
Bit 3
SUSPEND: indicate USB suspend status.
0 = Non-suspend status. When MCU wakeup from sleep mode by USB resume wakeup request, the bit will
changes from 1 to 0 automatically.
1 = Set to 1 by hardware when USB suspend request.
Bit 4
BUS_RST: USB bus reset.
0 = Non-USB bus reset.
1 = Set to 1 by hardware when USB bus reset request.
Bit 5
SOF: Indicate the USB SIE’s SOF packet is received
0 = Non USB SIE’s SOF packet received.
1 = If SOF_INT_EN = 1 then this bit will set to 1 by hardware when the SOF packet is received. Otherwise
the bit will always be 0. Clear this bit and also the bit 7 of INTRQ register (0x C8) by firmware.
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9.5.3 USB DATA COUNT REGISTER
The USB EP0 OUT token data byte counter.
092H
EP0OUT_CNT
Read/Write
After reset
Bit [4:0]
Bit 7
Bit 6
Bit 5
Bit 4
UEP0OC4
R/W
0
Bit 3
UEP0OC3
R/W
0
Bit 2
UEP0OC2
R/W
0
Bit 1
UEP0OC1
R/W
0
Bit 0
UEP0OC0
R/W
0
UEP0C [4:0]: USB endpoint 0 OUT token data counter.
9.5.4 USB ENABLE CONTROL REGISTER
The register control the regulator output 3.3 volts enable, SOF packet receive interrupt, NAK handshaking interrupt and
D+ internal 1.5k ohm pull up.
093H
Bit 7
USB_INT_EN
REG_EN
Read/Write
After reset
R/W
1
Bit 6
Bit 5
Bit 4
Bit 3
DP_UP_EN SOF_INT_EN
R/W
0
R/W
0
Bit 2
EP3NAK
_INT_EN
R/W
0
Bit 1
EP2NAK
_INT_EN
R/W
0
Bit [2:0]
EPnNAK_INT_EN [2:0]: EP1~EP3 NAK transaction interrupts enable control bits. n = 1, 2, 3.
0 = Disable NAK transaction interrupt request.
1 = Enable NAK transaction interrupt request.
Bit 5
SOF_INT_EN: USB SIE’s SOF packet receive interrupt enable.
Clear the bit and the bit 7 of INTEN register (0x C9)
= Disable USB SIE’s SOF interrupt request.
Set the bit and the bit 7 of INTEN register (0x C9) to 1
= Enable USB SIE’s SOF interrupt request. The
Bit 6
DP_UP_EN: D+ internal 1.5k ohm pull up resistor control bit.
0 = Disable D+ pull up 1.5k ohm to 3.3volts.
1 = Enable D+ pull up 1.5k ohm to 3.3volts.
Bit 7
REG_EN: 3.3volts Regulator control bit.
0 = Disable regulator output 3.3volts.
1 = Enable regulator output 3.3volts.
Bit 0
EP1NAK
_INT_EN
R/W
0
9.5.5 USB endpoint’s ACK handshaking flag REGISTER
The status of endpoint’s ACK transaction.
094H
Bit 7
Bit 6
Bit 5
Bit 4
EP_ACK
Read/Write
After reset
Bit [2:0]
Bit 3
Bit 2
EP3_ACK
R/W
0
Bit 1
EP2_ACK
R/W
0
Bit 0
EP1_ACK
R/W
0
EPn_ACK [2:0]: EP1~EP3 ACK transaction. n= 1, 2, 3. The bit is set whenever the endpoint that completes
with an ACK received.
0 = the endpoint (interrupt pipe) doesn’t complete with an ACK.
1 = the endpoint (interrupt pipe) complete with an ACK.
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9.5.6 USB endpoint’s NAK handshaking flag REGISTER
The status of endpoint’s NAK transaction.
095H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EP_NAK
Read/Write
After reset
Bit [2:0]
Bit 2
EP3_NAK
R/W
0
Bit 1
EP2_NAK
R/W
0
Bit 0
EP1_NAK
R/W
0
EPn_NAK [2:0]: EP1~EP3 NAK transaction. n = 1, 2, 3. The bit is set whenever the endpoint that
completes with an NAK received.
0 = the EPnNAK_INT_EN = 0 or the endpoint (interrupt pipe) doesn’t complete with an NAK.
1 = the EPnNAK_INT_EN = 1 and the endpoint (interrupt pipe) complete with an NAK.
9.5.7 USB ENDPOINT 0 ENABLE REGISTER
An endpoint 0 (EP0) is used to initialize and control the USB device. EP0 is bi-directional (Control pipe), as the device,
can both receive and transmit data, which provides to access the device configuration information and allows generic
USB status and control accesses.
096H
UE0R
Read/Write
After reset
Bit 7
-
Bit 6
UE0M1
R/W
0
Bit 5
UE0M0
R/W
0
Bit 4
-
Bit 3
UE0C3
R/W
0
Bit 2
UE0C
R/W
0
Bit 1
UE0C1
R/W
0
Bit 0
UE0C0
R/W
0
Bit [3:0]
UE0C [3:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 0 FIFO.
Bit [6:5]
UE0M [1:0]: The endpoint 0 modes determine how the SIE responds to USB traffic that the host sends to
the endpoint 0. For example, if the endpoint 0’s mode bit is set to 00 that is NAK IN/OUT mode as shown in
Table, The USB SIE will send NAK handshakes in response to any IN/OUT token set to the endpoint 0.The
bit 5 UE0M0 will auto reset to zero when the ACK transaction complete.
USB endpoint 0’s mode table
UE0M1
UE0M0
IN/OUT Token Handshake
0
0
NAK
0
1
ACK
1
0
STALL
1
1
STALL
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9.5.8 USB ENDPOINT 1 ENABLE REGISTER
The communication with the USB host using endpoint 1, endpoint 1’s FIFO is implemented as 16 bytes of dedicated
RAM. The endponit1 is an interrupt endpoint.
097H
UE1R
Read/Write
After reset
Bit 7
UE1E
R/W
0
Bit 6
UE1M1
R/W
0
Bit 5
UE1M0
R/W
0
Bit 4
UE1C4
R/W
0
Bit 3
UE1C3
R/W
0
Bit 2
UE1C2
R/W
0
Bit 1
UE1C1
R/W
0
Bit 0
UE1C0
R/W
0
Bit [4:0]
UE1C [4:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 1 FIFO.
Bit [6:5]
UE1M [1:0]: The endpoint 1 modes determine how the SIE responds to USB traffic that the host sends to
the endpoint 1. For example, if the endpoint 1’s mode bit is set to 00 that is NAK IN/OUT mode as shown in
Table, The USB SIE will send NAK handshakes in response to any IN/OUT token set to the endpoint 1.The
bit 5 UE1M0 will auto reset to zero when the ACK transaction complete.
USB endpoint 1’s mode table
UE1M1
UE1M0
IN/OUT Token Handshake
0
0
NAK
0
1
ACK
1
0
STALL
1
1
STALL
Bit 7
UE1E: USB endpoint 1 function enable bit.
0 = disable USB endpoint 1 function.
1 = enable USB endpoint 1 function.
9.5.9 USB ENDPOINT 2 ENABLE REGISTER
The communication with the USB host using endpoint 2, endpoint 2’s FIFO is implemented as 16 bytes of dedicated
RAM. The endpoint 2 is an interrupt endpoint.
098H
UE2R
Read/Write
After reset
Bit 7
UE2E
R/W
0
Bit 6
UE2M1
R/W
0
Bit 5
UE2M0
R/W
0
Bit 4
UE2C4
R/W
0
Bit 3
UE2C3
R/W
0
Bit 2
UE2C2
R/W
0
Bit 1
UE2C1
R/W
0
Bit 0
UE2C0
R/W
0
Bit [4:0]
UE2C [4:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 2 FIFO.
Bit [6:5]
UE2M [1:0]: The endpoint 2 modes determine how the SIE responds to USB traffic that the host sends to
the endpoint 2. For example, if the endpoint 2’s mode bit is set to 00 that is NAK IN/OUT mode as shown in
Table, The USB SIE will send NAK handshakes in response to any IN/OUT token set to the endpoint 2. The
bit 5 UE2M0 will auto reset to zero when the ACK transaction complete.
USB endpoint 2’s mode table
UE2M1
UE2M0
IN/OUT Token Handshake
0
0
NAK
0
1
ACK
1
0
STALL
1
1
STALL
Bit 7
UE2E: USB endpoint 2 function enable bit.
0 = disable USB endpoint 2 function.
1 = enable USB endpoint 2 function.
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9.5.10 USB ENDPOINT 3 ENABLE REGISTER
The communication with the USB host using endpoint 3, endpoint 3’s FIFO is implemented as 8 bytes of dedicated
RAM. The endpoint 3 is an interrupt endpoint.
099H
UE3R
Read/Write
After reset
Bit 7
UE3E
R/W
0
Bit 6
UE3M1
R/W
0
Bit 5
UE3M0
R/W
0
Bit 4
UE3C4
R/W
0
Bit 3
UE3C3
R/W
0
Bit 2
UE3C2
R/W
0
Bit 1
UE3C1
R/W
0
Bit 0
UE3C0
R/W
0
Bit [4:0]
UE3C [4:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 3 FIFO.
Bit [6:5]
UE3M [1:0]: The endpoint 3 modes determine how the SIE responds to USB traffic that the host sends to
the endpoint 3. For example, if the endpoint 3’s mode bit is set to 00 that is NAK IN/OUT mode as shown in
Table, The USB SIE will send NAK handshakes in response to any IN/OUT token set to the endpoint 3. The
bit 5 UE3M0 will auto reset to zero when the ACK transaction complete.
USB endpoint 3’s mode table
UE3M1
UE3M0
IN/OUT Token Handshake
0
0
NAK
0
1
ACK
1
0
STALL
1
1
STALL
Bit 7
UE3E: USB endpoint 3 function enable bit.
0 = disable USB endpoint 3 function.
1 = enable USB endpoint 3 function.
9.5.11 USB DATA POINTER REGISTER
USB FIFO address pointer. Use the point to set the FIFO address for reading data from USB FIFO and writing data to
USB FIFO.
0A3H
Bit 7
Bit 6
Bit 5
UDP0
UDP07
UDP06
UDP05
Read/Write
R/W
R/W
R/W
After reset
0
0
0
Address [07]~address [00]: data buffer for endpoint 0.
Address [17]~address [08]: data buffer for endpoint 1.
Address [27]~address [18]: data buffer for endpoint 2.
Address [37]~address [28]: data buffer for endpoint 3.
Bit 4
UDP04
R/W
0
Bit 3
UDP03
R/W
0
Bit 2
UDP02
R/W
0
Bit 1
UDP01
R/W
0
Bit 0
UDP00
R/W
0
Bit 3
UDR0_R3
R/W
0
Bit 2
UDR0_R2
R/W
0
Bit 1
UDR0_R1
R/W
0
Bit 0
UDR0_R0
R/W
0
Bit 2
UDR0_W2
R/W
0
Bit 1
UDR0_W1
R/W
0
Bit 0
UDR0_W0
R/W
0
9.5.12 USB DATA READ/WRITE REGISTER
0A5H
UDR0_R
Read/Write
After reset
Bit 7
UDR0_R7
R/W
0
Bit 6
UDR0_R6
R/W
0
Bit 5
UDR0_R5
R/W
0
Bit 4
UDR0_R4
R/W
0
UDR0_R: Read the data from USB FIFO which UDP0 register point to.
0A6H
Bit 7
UDR0_W UDR0_W7
Read/Write
R/W
After reset
0
Bit 6
UDR0_W6
R/W
0
Bit 5
UDR0_W5
R/W
0
Bit 4
UDR0_W4
R/W
0
Bit 3
UDR0_W3
R/W
0
UDR0_W: Write the data to USB FIFO which UDP0 register point to.
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
9.5.13 USB ENDPOINT OUT TOKEN DATA BYTES COUNTER
Endpoint 1’s OUT TOKEN DATA BYTES COUNTER.
0A7H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EP1OUT_CNT
UEP1OC4 UEP1OC3
Read/Write
R/W
R/W
After reset
0
0
Bit [4:0] UEP1Cn: Bytes counter of EP1 token data. Reset by firmware.
Bit 2
UEP1OC2
R/W
0
Bit 1
UEP1OC1
R/W
0
Bit 0
UEP1OC0
R/W
0
Bit 1
UEP2OC1
R/W
0
Bit 0
UEP2OC0
R/W
0
Bit 2
UEP3OC2
R/W
0
Bit 1
UEP3OC1
R/W
0
Bit 0
UEP3OC0
R/W
0
Bit 2
UBDE
R/W
0
Bit 1
DDP
R/W
0
Bit 0
DDN
R/W
0
Bit 1
EP2
_DATA0/1
R/W
1
Bit 0
EP1
_DATA0/1
R/W
1
9.5.14 Endpoint 2’s OUT TOKEN DATA BYTES COUNTER.
0A8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EP2OUT_CNT
UEP2OC4 UEP2OC3
Read/Write
R/W
R/W
After reset
0
0
Bit [4:0] UEP2Cn: Bytes counter of EP2 token data. Reset by firmware.
Bit 2
UEP2OC2
R/W
0
9.5.15 Endpoint 3’s OUT TOKEN DATA BYTES COUNTER.
0A9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EP3OUT_CNT
UEP3OC4 UEP3OC3
Read/Write
R/W
R/W
After reset
0
0
Bit [4:0] UEP3Cn: Bytes counter of EP3 token data. Reset by firmware.
9.5.16 UPID REGISTER
Forcing bits allow firmware to directly drive the D+ and D– pins.
0ABH
Bit 7
UPID
EP0OUT_EN
Read/Write
R/W
After reset
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 0
DDN: Drive D- on the USB bus.
0 = drive D- low.
1 = drive D- high.
Bit 1
DDP: drive D+ on the USB bus.
0 = drive D+ low.
1 = drive D+ high.
Bit 2
UBDE: Enable to direct drive USB bus.
0 = disable.
1 = enable.
Bit 7
EP0OUT_EN: Enable EP0 control data out.
0 = disable.
1 = enable to receive the EP0 continuous OUT TOKEN data over 8 bytes.
9.5.17 ENDPOINT TOGGLE BIT CONTROL REGISTER
0ACH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
UTOGGLE
-
-
-
-
-
Read/Write
After reset
-
-
-
-
-
Bit [2:0]
Bit 2
EP3
_DATA0/1
R/W
1
Endpoint 1~3’s DATA0/1 toggle bit control.
0 = Clear the endpoint 1~3’s toggle bit to DATA0
1 = hardware set toggle bit automatically.
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
10
SERIAL INPUT/OUTPUT TRANSCEIVER
10.1 OVERVIEW
The SIO (serial input/output) transceiver allows high-speed synchronous data transfer between the SN8F2250B series
MCU and peripheral devices or between several SN8F2250B devices. These peripheral devices may be Serial
EEPROMs, shift registers, display drivers, etc. The SN8F2250B SIO features include the following:
z
z
z
z
z
z
z
Full-duplex, 3-wire synchronous data transfer
TX/RX or TX Only mode
Master (SCK is clock output) or Slave (SCK is clock input) operation
MSB/LSB first data transfer
SDO (P5.2) is programmable open-drain output pin for multiple salve devices application
Two programmable bit rates (Only in master mode)
End-of-Transfer interrupt
The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, transfer edge and starting
this circuit. This SIO circuit will transmit or receive 8-bit data automatically by setting SENB and START bits in SIOM
register. The SIOB is an 8-bit buffer, which is designed to store transfer data. SIOC and SIOR are designed to
generate SIO’s clock source with auto-reload function. The 3-bit I/O counter can monitor the operation of SIO and
announce an interrupt request after transmitting/receiving 8-bit data. After transferring 8-bit data, this circuit will be
disabled automatically and re-transfer data by programming SIOM register.
SENB
MLSB
SI
8-bit Receive Buffer
CPUM1,0
SENB
MLSB
SO
SIOB 8-bit Buffer
CPUM1,0
SENB
SCLKMD
CPOL
CPHA
SCK
SIO 3-bit I/O Counter
CPUM1,0
÷1
Fcpu
START
SENB
÷8
SIO 8-bit Counter
÷16
÷32
SIO Time Out
CPUM1,0
Srate1,0
Auto-Reload
SIOR Register
SIO Interface Circuit Diagram
SONiX TECHNOLOGY CO., LTD
Page 110
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SIOB Data Register before the entire shift cycle is completed. When
receiving data, however, a received byte must be read from the SIOB Data Register before the next byte has been
completely shifted in. Otherwise, the first byte is lost. Following figure shows a typical SIO transfer between two
SN8F2250B micro-controllers. Master MCU sends SCK for initial the data transfer. Both master and slave MCU must
work in the same clock edge direction, and then both controllers would send and receive data at the same time.
SIO Master
SIO Slave
(SCKMD = 0)
(SCKMD = 1)
Read SIOB
SCK
SCK
SI
SO
2nd Receive Buffer
(Address = SIOB)
Shift Register
(SIOB)
Shift Register
(SIOB)
Write SIOB
Read SIOB
Write SIOB
SO
SI
Internal Bus
Internal Bus
2nd Receive Buffer
(Address = SIOB)
SIO Data Transfer Diagram
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
The SIO data transfer timing as following figure:
M
L
S
B
C
P
O
L
C
P
H
A
SCK
Idle
Status
0
0
1
Low
0
1
1
High
0
0
0
Low
0
1
1
1
0
1
0
1
1
Diagrams
bit7
bit6
bit7
bit6
bit5
bit4
bit5
bit7
bit6
bit5
bit7
bit6
bit5
bit4
bit4
bit3
bit3
bit3
bit2
bit2
bit1
bit2
bit1
bit0
bit1
bit0
bit0
Next data
High
bit4
bit3
bit2
bit1
bit0
Next data
Low
bit0
bit1
bit2
bit3
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Bit7
High
1
0
0
Low
1
1
0
High
bit4
bit5
bit6
Bit7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Bit7
Next data
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Bit7
Next data
SIO Data Transfer Timing
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
10.2 SIOM MODE REGISTER
0B4H
SIOM
Read/Write
After reset
Bit 7
SENB
R/W
0
Bit 6
START
R/W
0
Bit 5
SRATE1
R/W
0
Bit 4
SRATE0
R/W
0
Bit 3
MLSB
R/W
0
Bit 2
SCKMD
R/W
0
Bit 1
CPOL
R/W
0
Bit 7
SENB: SIO function control bit.
0 = Disable (P5.0~P5.2 is general purpose I/O port).
1 = Enable (P5.0~P5.2 is SIO pins).
Bit 6
START: SIO progress control bit.
0 = End of transfer.
1 = Progressing.
Bit [5:4]
SRATE1:0: SIO’s transfer rate select bit. These 2-bits are workless when SCKMD=1.
00 = Fcpu.
01 = Fcpu/32
10 = Fcpu/16
11 = Fcpu/8.
Bit 3
MLSB: MSB/LSB transfer first.
0 = MSB transmit first.
1 = LSB transmit first.
Bit 2
SCKMD: SIO’s clock mode select bit.
0 = Internal. (Master mode)
1 = External. (Slave mode)
Bit 1
CPOL: SIO’s transfer clock edge select bit.
0 = SCK idle status is low status
1 = SCK idle status is high status
Bit 0
CPHA: The Clock Phase bit controls the phase of the clock on which data is sampled.
0 = Data receive at the fisrt clock phase.
1 = Data receive at the second clock phase.
Bit 0
CPHA
R/W
0
Note: 1. If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock,
the SIO is in MASTER mode.
2. Don’t set SENB and START bits in the same time. That makes the SIO function error.
Because SIO function is shared with Port5 for P5.0 as SCK, P5.1 as SDI and P5.2 as SDO.
The following table shown the Port5[2:0] I/O mode behavior and setting when SIO function enable and disable.
SENB=1 (SIO Function Enable)
(SCKMD=1)
P5.0 will change to Input mode automatically, no matter what P5M
SIO source = External clock
setting
P5.0/SCK
(SCKMD=0)
P5.0 will change to Output mode automatically, no matter what
SIO source = Internal clock
P5M setting
P5.1/SDI
P5.1 must be set as Input mode in P5M ,or the SIO function will be abnormal
SIO = Transmitter/Receiver
P5.2 will change to Output mode automatically, no matter what
P5.2/SDO
P5M setting
SENB=0 (SIO Function Disable)
P5.0/P5.1/P5.2 Port5[2:0] I/O mode are fully controlled by P5M when SIO function is disable
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
10.3 SIOB DATA BUFFER
0B6H
SIOB
Read/Write
After reset
Bit 7
SIOB7
R/W
0
Bit 6
SIOB6
R/W
0
Bit 5
SIOB5
R/W
0
Bit 4
SIOB4
R/W
0
Bit 3
SIOB3
R/W
0
Bit 2
SIOB2
R/W
0
Bit 1
SIOB1
R/W
0
Bit 0
SIOB0
R/W
0
Bit 2
SIOR2
W
0
Bit 1
SIOR1
W
0
Bit 0
SIOR0
W
0
SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data.
10.4 SIOR REGISTER DESCRIPTION
0B5H
SIOR
Read/Write
After reset
Bit 7
SIOR7
W
0
Bit 6
SIOR6
W
0
Bit 5
SIOR5
W
0
Bit 4
SIOR4
W
0
Bit 3
SIOR3
W
0
The SIOR is designed for the SIO counter to reload the counted value when end of counting. It is like a post-scaler of
SIO clock source and let SIO has more flexible to setting SCK range. Users can set the SIOR value to setup SIO
transfer time. The valid SIOR value = 0x0 to 0xFD. To setup SIOR value equation to desire transfer time is as
following.
SCK frequency = SIO rate / (256 - SIOR);
SIOR = 256 - ( 1 / ( SCK frequency ) * SIO rate )
Example: Setup the SIO clock to be 2MHz. Fosc = 12MHz. SIO’s rate = Fcpu/2. Fcpu = Fosc/1 = 12MHz.
SIOR = 256 – (1/(2MHz) * 12MHz/2)
= 256 – 3
= 253
= 0xFD
Example: Master, duplex transfer and transmit data on rising edge
MOV
A,TXDATA
; Load transmitted data into SIOB register.
B0MOV
SIOB,A
MOV
A,#0FEH
; Set SIO clock
B0MOV
SIOR,A
MOV
A,#10000000B
; Setup SIOM and enable SIO function.
B0MOV
SIOM,A
B0BSET
FSTART
; Start transfer and receiving SIO data.
CHK_END:
B0BTS0
FSTART
; Wait the end of SIO operation.
JMP
CHK_END
B0MOV
A,SIOB
; Save SIOB data into RXDATA buffer.
MOV
RXDATA,A
Example: Slave, duplex transfer and transmit data on rising edge
MOV
A,TXDATA
; Load transfer data into SIOB register.
B0MOV
SIOB,A
MOV
A,# 10000100B
; Setup SIOM and enable SIO function.
B0MOV
SIOM,A
B0BSET
FSTART
; Start transfer and receiving SIO data.
CHK_END:
B0BTS0
FSTART
; Wait the end of SIO operation.
JMP
CHK_END
B0MOV
A,SIOB
; Save SIOB data into RXDATA buffer.
MOV
RXDATA,A
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
11
Flash
11.1 OVERVIEW
The SN8F2250B series USB MCU integrated device feature in-system programmable (ISP) FLASH memory for
convenient, upgradeable code storage. The FLASH memory may be programmed via the SONiX 8 bit MCU
programming interface or by application code and USB interface for maximum flexibility. The SN8F2250B provides
security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH
memory.
¾
The MCU is stalled during Flash write (program) and erase operations, although peripherals (USB, Timers, WDT,
I/O, PWM, etc.) remain active.
¾
Interrupts will disable by firmware during a Flash write or erase operation.
¾
The Flash page containing the boot loader and code option (ROM address 0x2000 ~ 0x27FF) cannot be erased
from application code when the code option’s security1 enable.
¾
Watch dog timer should be clear before the Flash write or erase operation.
¾
The erase operation sets all the bits in the Flash page to logic 1.
¾
Hardware will hold system clock and automatically move out data from RAM and do programming, after
programming finished, hardware will release system clock and let MCU execute the next instruction.(Recommend
add two NOP instructions after this active).
11.2 FLASH PROGRAMMING/ERASE CONTROL REGISTER
0BAH
PECMD
Read/Write
After reset
Bit [7:0]
Bit 7
PECMD7
W
0
Bit 6
PECMD6
W
0
Bit 5
PECMD5
W
0
Bit 4
PECMD4
W
0
Bit 3
PECMD3
W
0
Bit 2
PECMD2
W
0
Bit 1
PECMD1
W
0
Bit 0
PECMD0
W
0
PECMD[7:0]: 0x5A: Page Program (32 words/page), 0xC3: Page Erase (128 words/page)
SONiX TECHNOLOGY CO., LTD
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Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
11.3 PROGRAMMING/ERASE ADDRESS REGISTER
0BBH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEROML7 PEROML6 PEROML5 PEROML4 PEROML3 PEROML2 PEROML1 PEROML0
PEROML
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Bit [7:0] PEROML[7:0]: Define the target starting low byte address [7:0] of Flash memory (10K x 16) which is going
to be programmed or erased.
0BCH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEROMH7 PEROMH6 PEROMH5 PEROMH4 PEROMH3 PEROMH2 PEROMH1 PEROMH0
PEROMH
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Bit [7:0] PEROMH [7:0]: Define the target starting high address [15:8] of Flash memory (10K x 16) which is going to
be programmed or erased.
The valid PAGE ERASE starting addresses are 0x0, 0x80, 0x100, 0x180, 0x 200, 0x280, 0x300, 0x380 … 0x2780.
The page erase function is used to erase a page of 128 contiguous words in Flash ROM.
Note: If the code option SECURITY1 = 0 (SECURITY1 disable), the code option address 0x27FC ~ 0x27FF will
NOT be protected by hardware. And the code option can be “erase and program” by the
in-system-programming function. To avoid the error occur, when SECUIRTY1 = 0 (SECURITY1 disable),
please DO NOT set the PAGE ERASE starting address at 0x2780.
The valid PAGE PROGRAM starting addresses are 0x0, 0x20, 0x40, 0x60, 0x80, 0xA0, 0xC0, 0xE0 … 0x27E0. The
page program function is used to program a page of 32 contiguous words in Flash ROM.
10Kx16 FLASH
User reset vector
0000H
Reset vector
Jump to user start address
0001H
.
General purpose area
.
0007H
0008H
User interrupt vector
Interrupt vector
0009H
User program
.
.
000FH
General purpose area
0010H
0011H
.
.
.
2000H
.
27FBH
End of user program
SECURITY1 protect &
27FCH
Reserved (Code option)
27FDH
27FEH
27FFH
Flash ROM mapping
Note: 1. If the code option SECURITY1 = 1 (SECURITY1 enable), the FLASH ROM ADDRESS = 0x2000 ~
0x27FF will not allow to do the “page erase and page program”.
2. If the code option SECURITY1 = 0 (SECURITY1 disable), the code option address 0x27FC ~ 0x27FF
will not be protected by hardware. And the code option can be “erase and program” by the
in-system-programming function.
SONiX TECHNOLOGY CO., LTD
Page 116
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
11.4 PROGRAMMING/ERASE DATA REGISTER
0BDH
PERAML
Read/Write
After reset
0BEH
PERAMCNT
Read/Write
After reset
Bit 7
PERAML7
R/W
0
Bit 6
PERAML6
R/W
0
Bit 5
PERAML5
R/W
0
Bit 4
PERAML4
R/W
0
Bit 3
PERAML3
R/W
0
Bit 2
PERAML2
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PERAMCNT4 PERAMCNT3 PERAMCNT2 PERAMCNT1 PERAMCNT0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 1
PERAML1
R/W
0
Bit 2
-
Bit 1
-
Bit 0
PERAML0
R/W
0
Bit 0
PERAML8
R/W
0
{PERAMCNT [1:0], PERAML [7:0]}: Define the starting RAM address [9:0], which stores the data wanted to be
programmed. The valid RAM addresses are 00H ~ 07FH and 0100H ~ 01FFH.
PERAMCNT [7:3]: Defines the number of words wanted to be programmed. The maximum PERAMCNT [7:3] is 01FH,
which program 32 words (64 bytes RAM) to the Flash. The minimum PERAMCNT [7:3] is 00H, which program only 1
word to the Flash.
11.4.1 Flash In-system-programming mapping address
X
X+1
RAM (byte)
bit7 ~ bit0
DATA0
DATA1
X+2
DATA2
X+3
…
X+N
DATA3
DATAN
SONiX TECHNOLOGY CO., LTD
Y
Y+1
=>
Flash ROM (word)
bit15 ~ bit8
bit7 ~ bit0
DATA1
DATA0
DATA3
DATA2
Y+2
Y+3
…
Y+M
Page 117
DATAN
DATAN-1
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
12
Field
M
O
V
E
A
R
I
T
H
M
E
T
I
C
L
O
G
I
C
P
R
O
C
E
S
S
B
R
A
N
C
H
INSTRUCTION TABLE
Mnemonic
MOV
A,M
MOV
M,A
B0MOV
A,M
B0MOV
M,A
MOV
A,I
B0MOV
M,I
XCH
A,M
B0XCH
A,M
MOVC
A←M
M←A
A ← M (bank 0)
M (bank 0) ← A
A←I
M ← I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
A ←→M
A ←→M (bank 0)
R, A ← ROM [Y,Z]
Description
C
-
DC
-
Z
√
√
-
Cycle
1
1
1
1
1
1
1+N
1+N
2
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
A,M
M,A
A,M
M,A
M,A
A,I
A,M
M,A
A,M
M,A
A,I
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
A ( A + M, if occur carry, then C=1, else C=0
M ( A + M, if occur carry, then C=1, else C=0
M (bank 0) ( M (bank 0) + A, if occur carry, then C=1, else C=0
A ( A + I, if occur carry, then C=1, else C=0
A ( A - M - /C, if occur borrow, then C=0, else C=1
M ( A - M - /C, if occur borrow, then C=0, else C=1
A ( A - M, if occur borrow, then C=0, else C=1
M ( A - M, if occur borrow, then C=0, else C=1
A ← A - I, if occur borrow, then C=0, else C=1
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
√
√
√
1
1+N
1
1+N
1+N
1
1
1+N
1
1+N
1
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
A ← A xor M
M ← A xor M
A ← A xor I
√
√
√
√
√
√
√
√
√
√
√
-
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
1
1+N
1
1
1+N
1
1
1+N
1
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
M ← RRC M
A ← RLC M
M ← RLC M
M←0
M.b ← 0
M.b ← 1
M(bank 0).b ← 0
M(bank 0).b ← 1
√
√
√
√
-
-
√
√
√
√
√
√
√
√
√
-
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
CMPRS
CMPRS
INCS
INCMS
DECS
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
CALL
A,I
A,M
M
M
M
M
M.b
M.b
M.b
M.b
d
d
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
If M.b = 0, then skip next instruction
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
√
√
-
-
√
√
-
1+S
1+S
1+ S
1+N+S
1+ S
1+N+S
1+S
1+S
1+S
1+S
2
2
√
-
√
-
√
-
2
2
1
1
1
RET
PC ← Stack
RETI
PC ← Stack, and to enable global interrupt
PUSH
To push ACC and PFLAG (except NT0, NPD bit) into buffers.
POP
To pop ACC and PFLAG (except NT0, NPD bit) from buffers.
NOP
No operation
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.
2. If branch condition is true then “S = 1”, otherwise “S = 0”.
M
I
S
C
SONiX TECHNOLOGY CO., LTD
Page 118
1
1+N
1
1+N
1
1+N
1
1+N
1+N
1+N
1+N
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
13
DEVELOPMENT TOOL
SONIX provides ICE (in circuit emulation), IDE (Integrated Development Environment), EV-kit and firmware library for
USB application development. ICE and EV-kit is external hardware device and IDE is a friendly user interface for
firmware development and emulation.
13.1 ICE (In Circuit Emulation)
The ICE called “SN8ICE2K Plus”
SONiX TECHNOLOGY CO., LTD
Page 119
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
13.2 SN8F2250B EV-kit
The SN8F2250B and SN8F2250 use the same EV-kit. The EV-kit includes ICE interface, GPIO interface, USB
interface, and VREG 3.3V power supply.
z
z
z
z
ICE Interface: Interface connected to SN8ICE2K Plus
GPIO Interface: SN8F2251/11/21/53/531/55 package form connector.
USB Interface: USB Mini-B connector.
VREG 3.3V Power Supply: Use SN8P2212’s VREG to supply 3.3V power for VREG pin.
The outline of SN8F2250/SN8F2250B EV-kit is as following.
z
z
z
z
J1: Jumper to connect between the 5V VDD from SN8ICE2K Plus and VDD_IC on SN8F2251/11/21/53/531/55
package form socket.
J4: USB Mini-B connector.
U8: SN8P2212 to supply 3.3V power for VREG pin and USB PHY.
U9-U14: SN8F2251/11/21/53/531/55 connector for user’s target board.
13.3 SN8F2250/SN8F2250B Transition Board
The SN8F2250 and SN8F2250B use the same transition boards. The Transition Boards includes total 6 models, and
each of them is designated to each IC Package. The following shows the transition board outline for SN8F22531.
Among the board, both C1 and C2 MUST be welded by 1uF capacitor.
SONiX TECHNOLOGY CO., LTD
Page 120
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
14
ELECTRICAL CHARACTERISTIC
14.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd)…………………………………………………………………………………………………………………….……………… - 0.3V ~ 6.0V
Input in voltage (Vin)…………………………………………………………………………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)
SN8F2251BJ, SN8F22521B/2253BS, SN8F22521BX, SN8F2253BJ, SN8F2255BF ………………………...…. ………………… 0°C ~ + 70°C
Storage ambient temperature (Tstor) ………………………………………………………………….………………………………………… –30°C ~ + 125°C
14.2 ELECTRICAL CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, fosc = 12MHz, ambient temperature is 25°C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
Normal mode except USB transmitter
Vdd1
4.0
5
Operating voltage
specifications, Vpp = Vdd
Vdd2 USB mode
4.25
5
RAM Data Retention voltage
Vdr
1.5*
Vdd rise rate
Vpor Vdd rise rate to ensure power-on reset
0.05
ViL1 P0, P1, P5.3, P5.4 input ports
Vss
Input Low Voltage
ViL2 P2, P5.0, P5.1, P5.2 input ports
Vss
ViH1
Input High Voltage
P0, P1, P5.3, P5.4 input ports
ViH2
P2, P5.0, P5.1, P5.2 input ports
Reset pin leakage current
I/O port pull-up resistor Rup1
I/O port pull-up resistor Rup2
D+ pull-up resistor
I/O port input leakage current
I/O output source current
sink current
Ilekg
Rup1
Rup2
Rd+
Ilekg
IoH
IoL
Vin = Vdd
P0, P1, P5.3, P5.4 ‘s Vin = Vss, Vdd = 5V
P2, P5.0, P5.1, P5.2’s Vin = Vss, Vdd = 5V
Vdd = 5V, VREG = 3.3V
Pull-up resistor disable, Vin = Vdd
Vop = Vdd – 1V
Vop = Vss + 0.4V
INTn trigger pulse width
Tint0
INT0 interrupt request pulse width
Page erase (128 words)
Page program (32 words)
Terase Flash ROM page erase time
Tpg
Flash ROM page program time (program 32 words)
VREG33 Max Regulator Output Current,
IVREG33
VREG33 Regulator current
Vcc > 4.35 volt with 10uF to GND
Ivreg33 No loading. VREG33 pin output 3.3V ((Regulator
VREG33 Regulator GND current
_gnl enable)
Ivreg25 No loading.VREG25 pin output 2.5V ((Regulator
VREG25 Regulator GND current
_gnl enable)
VREG33 Regulator Output
voltage
Supply Current
LVD Voltage
0.7Vdd
0.8
VREG33
25
50
1.35
15
MAX.
UNIT
5.5
V
V
V
V/ms
V
-
5.25
0.3Vdd
0.2
VREG33
Vdd
V
V
-
Vdd
V
40*
100*
1.5
20*
15*
2
70
150
1.65
2
uA
KΩ
KΩ
KΩ
uA
2/fcpu
-
-
cycle
-
25*
TBD
ms
-
1*
TBD
ms
-
-
60
mA
-
70
100
uA
-
120
150
uA
mA
20
Vreg1
VCC > 4.35V, 0 < temp < 40°C,
IVREG ≦ 60 mA with 10uF to GND
3.0
-
3.6
V
Vreg2
VCC > 4.35V, 0 < temp < 40°C,
IVREG ≦ 25 mA with 10uF to GND
3.1
-
3.6
V
Idd1
normal Mode
(No loading,
Fcpu = Fosc/1)
Vdd= 5V, 12Mhz
-
10
15
mA
Idd2
Slow Mode
(Internal low RC)
Vdd= 5V, 24Khz
-
190
250
uA
Idd3
Sleep Mode
Vdd= 5V
-
190
250
uA
Idd4
Green Mode
(No loading,
Fcpu = Fosc/4
Watchdog Disable)
Vdd= 5V, 12Mhz
-
5
10
mA
Vdet
Low voltage reset level.
2.0
190
2.4
250
2.9
uA
V
Vdd=5V, ILRC 24Khz
* These parameters are for design reference, not tested.
SONiX TECHNOLOGY CO., LTD
Page 121
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
15
FLASH ROM PROGRAMMING PIN
Programming Information of SN8F2250 Series
SN8F2251BJ SN8F22521BS/X SN8F2253BS SN8F22531BJ
Chip Name
EZ Writer / MP Writer
Flash IC / JP3 Pin Assigment
Connector
Numbe
Name
Number Pin Number Pin Number Pin Number
r
1
VDD
11
VDD
18
VDD
20
VDD
23
2
GND
5
VSS
14
VSS
16
VSS
19
3
CLK
10
P2.0
19
P2.0
21
P2.0
24
4
CE
5
PGM
15
P1.0
6
P1.0
6
P1.0
9
6
OE
9
P2.1
20
P2.1
22
P2.1
1
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
17
HLS
18
RST
19
20
ALSB/PDB
16
P1.1
7
P1.1
7
P1.1
10
SONiX TECHNOLOGY CO., LTD
Page 122
SN8F2255BF
Pin
Number
Pin
VDD
VSS
P2.0
14
10
15
VDD
VSS
P2.0
P1.0
P2.1
26
16
P1.0
P2.1
P1.1
27
P1.1
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
Programming Information of SN8F2250 Series
Chip Name
SN8F22511BX
EZ Writer / MP Writer
Flash IC / JP3 Pin Assigment
Connector
Numbe
Name
Number Pin
r
1
VDD
14
VDD
2
GND
10
VSS
3
CLK
15
P2.0
4
CE
5
PGM
4
P1.0
6
OE
16
P2.1
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
17
HLS
18
RST
19
20
ALSB/PDB
5
P1.1
SONiX TECHNOLOGY CO., LTD
Page 123
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16
PACKAGE INFORMATION
16.1 LQFP32 PIN
SYMBOLS
MIN.
MAX.
(mm)
A
--
1.6
A1
0.05
0.15
A2
1.35
1.45
c1
0.09
0.16
D
9.00 BSC
D1
7.00 BSC
E
9.00 BSC
E1
7.00 BSC
e
0.8 BSC
b
0.30
0.45
L
0.45
0.75
L1
SONiX TECHNOLOGY CO., LTD
1 REF
Page 124
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16.2 SOP 24 PIN
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.004
0.599
0.291
0.394
0.016
0°
0.600
0.295
0.407
0.035
4°
NOR
MAX
(mm)
0.104
0.624
0.299
0.419
0.050
8°
0.102
15.214
7.391
10.008
0.406
0°
15.24
7.493
10.337
0.889
4°
2.642
15.84
7.595
10.643
1.270
8°
16.3 SOP 20 PIN
SONiX TECHNOLOGY CO., LTD
Page 125
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.496
0.291
0.394
0.016
0°
SONiX TECHNOLOGY CO., LTD
0.099
0.008
0.502
0.295
0.407
0.033
4°
NOR
MAX
(mm)
0.104
0.012
0.508
0.299
0.419
0.050
8°
Page 126
2.362
0.102
12.598
7.391
10.008
0.406
0°
2.502
0.203
12.751
7.493
10.325
0.838
4°
2.642
0.305
12.903
7.595
10.643
1.270
8°
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16.4 SSOP 20 PIN
SYMBOLS
A
A1
A2
b
c
D
E
E1
[e]
h
L
L1
ZD
Y
θ°
MIN
NOR
MAX
MIN
(inch)
0.053
0.004
0.008
0.007
0.337
0.228
0.150
0.010
0.016
0.039
0°
SONiX TECHNOLOGY CO., LTD
0.063
0.006
0.010
0.008
0.341
0.236
0.154
0.025
0.017
0.025
0.041
0.059
-
NOR
MAX
(mm)
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
1.350
0.100
0.200
0.180
8.560
5.800
3.800
0.020
0.050
0.043
0.250
0.400
1.000
0.004
8°
0°
Page 127
1.600
0.150
0.254
0.203
8.660
6.000
3.900
0.635
0.420
0.635
1.050
1.500
-
1.750
0.250
1.500
0.300
0.250
8.740
6.200
4.000
0.500
1.270
1.100
0.100
8°
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16.5 QFN 24 PIN
SONiX TECHNOLOGY CO., LTD
Page 128
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16.6 QFN 16 PIN
SONiX TECHNOLOGY CO., LTD
Page 129
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
16.7 SSOP 16 PIN
SYMBOLS
A
A1
A2
b
b1
c
c1
D
E1
E
L
e
θ°
MIN
NOR
MAX
MIN
(inch)
0.053
0.004
0.008
0.008
0.007
0.007
0.189
0.150
0.228
0.016
0°
SONiX TECHNOLOGY CO., LTD
0.025 BASIC
-
NOR
MAX
(mm)
0.069
0.010
0.059
0.012
0.011
0.010
0.009
0.197
0.157
0.244
0.050
1.3462
0.1016
0.2032
0.2032
0.1778
0.1778
4.8006
3.81
5.7912
0.4064
8°
0°
Page 130
0.635 BASIC
-
1.7526
0.254
1.4986
0.3048
0.2794
0.254
0.2286
5.0038
3.9878
6.1976
1.27
8°
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
17Marking Definition
17.1 INTRODUCTION
There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit
MCU for order or obtain information.
17.2 MARKING INDETIFICATION SYSTEM
SN8 X
Part No.
X X X
Material
B = PB-Free Package
G = Green Package
Temperature
Range
- = 0℃ ~ 70℃
Shipping
Package
SONiX TECHNOLOGY CO., LTD
D = -40℃ ~ 85℃
W = Wafer
H = Dice
K = SK-DIP
P = P-DIP
S = SOP
X = SSOP
F = LQFP
J = QFN
Device
Device Part No.
ROM Type
P=OTP
F=FLASH
Title
SONiX 8-bit MCU Production
Page 131
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
17.3 MARKING EXAMPLE
Name
SN8F2253BSB
SN8F2253BXB
SN8F2251BJG
SN8F2253BSG
SN8F2253BXG
SN8F2255BFG
SN8F2253BW
SN8F2253BH
ROM Type
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Device
2253B
2253B
2251B
2253B
2253B
2255B
2253B
2253B
Package
SOP
SSOP
QFN
SOP
SSOP
LQFP
Wafer
Dice
Temperature
0℃~70℃
0℃~70℃
0℃~70℃
0℃~70℃
0℃~70℃
0℃~70℃
0℃~70℃
0℃~70℃
Material
PB-Free Package
PB-Free Package
Green Package
Green Package
Green Package
Green Package
-
17.4 DATECODE SYSTEM
X X X X XXXXX
SONiX Internal Use
Day
1=01
2=02
....
9=09
A=10
B=11
....
Month
1=January
2=February
....
9=September
A=October
B=November
C=December
Year
SONiX TECHNOLOGY CO., LTD
03= 2003
04= 2004
05= 2005
06= 2006
....
Page 132
Version 1.1
SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 10F-1, NO. 36, Taiyuan Stree., Chupei City, Hsinchu, Taiwan R.O.C.
Tel: 886-3-5600 888
Fax: 886-3-5600 889
Taipei Office:
Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C.
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
Hong Kong Office:
Unit No.705,Level 7 Tower 1,Grand Central Plaza 138 Shatin Rural Committee
Road,Shatin,New Territories,Hong Kong.
Tel: 852-2723-8086
Fax: 852-2723-9179
Technical Support by Email:
[email protected]
SONiX TECHNOLOGY CO., LTD
Page 133
Version 1.1