SP5748 2.4GHz Very Low Phase Noise PLL Advance Information DS4875 - 1.3 November 1998 The SP5748 is a single chip frequency synthesiser designed for tuning systems up to 2.4 GHz and is optimized for low phase noise with comparison frequencies up to 4 MHz. It is designed to be downwards software compatible with the SP5658. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. a buffered reference frequency output is also available to drive a second SP5748. ENABLE DATA CLOCK PORT P1/OC SPOT REF. CRYSTAL CAP CRYSTAL The RF programmable divider contains a front end dual modulus 16/17 functioning over the full operating range and allows for coarse tuning in the upconverter application and fine tuning in the downconverter. 14 CHARGE PUMP DRIVE VEE RF INPUT RF INPUT VCC REF PORT P0/OP MP14 Figure1 Pin connections - top view The device also contains 2 switching ports. APPLICATIONS FEATURES ● TV, VCR and Cable tuning systems ● Complete 2.4 GHz single chip system (for faster device refer to to SP5768) ● Optimised for low phase noise, with comparison frequencies up to 4 MHz ● Communications systems ● No RF prescaler SP5748/KG/MP1S (Tubes) SP5748/KG/MP1T (Tape and Reel) ● Selectable reference division ratio ● Reference frequency output ● Selectable charge pump current ● Integrated loop amplifier ● Two switching ports ● Low power replacement for SP5658 and 5668 ● Downwards software compatible with SP5658 ● ESD protection, (Normal ESD handling procedures should be observed) ORDERING INFORMATION SP5748 Advance Information REF 13 BIT COUNT RF INPUT REFERENCE DIVIDER CRYSTAL 16/17 4 BIT COUNT PUMP DRIVE 17 BIT LATCH DATA CLOCK 6 BIT LATCH 3 BIT LATCH & PORT/ TEST MODE INTERFACE DATA INTERFACE ENABLE PORT P0/OP PORT P1/OC Figure 2 SP5748 block diagram ELECTRICAL CHARACTERISTICS These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V Characteristic Pin Min Supply current 10 Value Typ Units Max 13 mA RF input frequency range 11,12 80 2400 MHz RF input voltage 11,12 30 300 mV rms RF input impedance 11,12 Data, clock & enable input high voltage input low voltage input current hysterysis 5,6,4 See Figure 3 3 0 -10 Vcc 0.7 10 0.8 V V µA V PP 2 Conditions All input conditions SP5748 Advance Information ELECTRICAL CHARACTERISTICS (continued) These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC =+ 4·5V to +5·5V Characteristic Pin Min Clock rate Value Typ 6 Bus timing data set up data hold enable set up enable hold clock to enable Units 500 kHz 5,6,4 300 600 300 600 ns ns ns ns 300 ns Charge pump output current 1 Charge pump output leakage 1 Charge pump drive output current 14 0.5 Crystal frequency Recommended crystal 2,3 2 10 Conditions Max See Figure4 See Figure 5, Vpin1 = 2V +-3 +-10 nA Vpin1=2V mA Vpin 14=0.7V 20 200 MHz Ω See Figure 6 for application 4 MHz parallel resonant crystal. series resistance Oscillator temperature stability TBC o ppm/ C Oscillator supply voltage stability TBC ppm/V External reference input frequency 2 2 20 MHz Sinewave coupled through TBA nF blocking capacitor External reference drive 2 0.2 0.5 Vpp Sinewave coupled through level Buffered reference frequency output * output amplitude output impedance TBA nF blocking capacitor 9 AC coupled 0.35 TBC Vpp Ω 2-20MHz 3 SP5748 Advance Information ELECTRICAL CHARACTERISTICS These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V Characteristic Pin Value Min Typ Comparison frequency Units Max 4 Equivalent phase noise at phase detector -148 RF division ratio 240 MHz dBc/Hz @10 kHz, SSB, with 2 MHz comparison from 4 MHz crystal reference 131071 Reference division ratio Output ports P0-P1# sink current leakage current Conditions see figure (7) 7, 8 2 10 µA mA Vport = 0.7V Vport = Vcc * Reference output disabled by connecting to Vcc if not required ’ Output ports high impedance on power up, with data, clock and enable at logic 0 4 SP5748 Advance Information ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE at 0V Characteristic Supply voltage, Vcc Pin Min 10 -0.3 RF input voltage 11,12 RF input DC offset 11,12 -0.3 7,8 -0.3 Charge pump DC offset 1 -0.3 Varactor drive DC offset 14 -0.3 Crystal DC offset 2,3 -0.3 9 5,6,4 Port voltage Buffered ref output Data, clock & enable DC offset Storage temperature Max Units 7 V 2.5 Vp-p V Vcc+0.3 Vcc+0.3 V V -0.3 Vcc+0.3 Vcc+0.3 -0.3 Vcc+0.3 V -55 +125 °C +150 °C 81 27 °C/W °C/W TBC mW MP14 thermal resistance, chip to ambient chip to case 2 Conditions Differential across pins 11 and 12 V Vcc+0.3 Vcc+0.3 Junction temperature Power consumption at Vcc=5.5V ESD protection Typ V V kV All ports off Mil-std 883B latest revision method 3015 cat.1. Functional description The SP5748 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The package and pin allocation is shown in Figure 1 and the block diagram in Figure 2. The SP5748 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 26 bits, two of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits RD & R0-R2, see Figure 7, two bits to set charge pump current, bit C0 and C1, see Figure 5, and the remaining bit to access test modes, bit T0, see Figure 8. The programming format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17 bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bit and the A counter 4 The output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in Figure 7. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Figure 5, A buffered crystal reference frequency suitable for driving further synthesisers is available from pin 9. If not required this output can be disabled by connecting to Vcc The programmable divider output divided by 2, Fpd/2 and comparison frequency, Fcomp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Figure 8. 5 SP5748 Advance Information +j1 +j2 +j0.5 +j0.2 +j5 0 1 2 -j0.2 S11 : Zo = 50Ω 4 -j0.5 Normalised to 50Ω -j5 3 Frequency Markers at 500MHz, -j2 1GHz, 1.5GHz and 2.4GHz -j1 Figure 3 RF input impedance CLOCK ENABLE DATA 225 P1 224 223 222 221 P0 T0 C1 C0 220 R2 219 218 R1 R0 217 RD 216 MSB LSB Frequency data TIMING DIAGRAM TBC 2^16 to 2^0 : Programmable divider ratio control bits R2,R1,R0 : Reference divider control bits RD : Reference divider mode select P1,P0 : Port control bits C1,C0 : Charge pump current select T0 : Test mode enable Figure 4 Data format C1 C0 Current (in mA) 0 0 0.2 0 1 0.9 1 0 .1 1 1 .45 Figure 5 Charge pump current 6 20 SP5748 Advance Information 2 SP5748 3 Figure 6 Crystal oscillator application RD 0 0 0 0 0 0 0 0 R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 RATIO 2 4 8 16 32 64 128 256 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 5 10 20 40 80 160 320 Figure 7 Reference division ratio P1 X 0 0 1 1 P0 X 0 1 0 1 T0 0 1 1 1 1 FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port P1 = Fcomp, P0 = Fpd/1 X = don't care Figure 8 Test modes 7 SP5748 Advance Information 300 VIN (mV RMS INTO 50Ω) OPERATING WINDOW 30 10 1000 80 2400 FREQUENCY (MHz) Figure 9 Typical input sensitivity 1.6GHz 50 - 900MHz 38.9MHz 1650-2700MHz 1650 -2400MHz 2 VCO SP5748 SP5748 3 3 VCO 10 10nF Figure 10 Example of double conversion from VHF/UHF frequencies to TV IF 18pF +30V 2 39pF 68pF 3 15nF +5V 22k 4MHz 16k 13k3 BCW31 Optional application utilising on–board crystal controlled oscillator ENABLE DATA 2 13 3 12 4 5 CLOCK P1 SP5748 CONTROL MICRO 2n2 TUNER 1n 1n OSCILLATOR OUTPUT 11 10 6 9 7 8 10n P0 Figure 11 Typical application SP5748 8 47k 14 1 REFERENCE +12V SP5748 Advance Information APPLICATION NOTES REFERENCE SOURCE A generic set of application notes AN168 for designing withsynthesisers such as the SP5748 has been written. This covers aspects such as loop filter design and decoupling. Thisapplication note is also featured in the Media Data Book, or refer to the Mitel Semiconductor Internet Site http://www.Mitelsemi.com. A generic test/ demo board has been produced which can be used for the SP5748. A circuit diagram is shown in Figure 12. The SP5748 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: The board can be used for the following purposes: (A) Measuring RF sensitivity performance. (B) Indicating port function. (C) Synthesising the voltage controlled oscillator. (D) Testing of external reference. (E) Measurement of phase noise performance. phase comparator LO frequency noise floor + 20 log 10 phase comparator frequency ( Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:– A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. LOOP BANDWIDTH The majority of applications for which the SP5748 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. 9 ) Clock GND Enable Data 3 WIRE BUS J5 6 5 4 3 C12 C13 C15 100pF 100pF 100pF 8V C11 1nF HLMPK-150 LED2 HLMPK-150 LED1 10nF C6 RF2 EXT REF 4K7 R4 4K7 R1 1 R6 POT2 2 LK2 LK 18pF C1 1 2 1 SW DIP-2 S1 2 4 3 X1 4MHz 39pF C18 7 6 5 4 3 2 1 1 2 J4 C2 2n2F P0 REF OUT VCC RF Input RF Input VEE PORT OUTPUTS P1 CLK DATA ENA XTAL XTAL CAP Drive Output IC1 SP5748 CP NF C3 8 9 10 11 12 13 14 C17 10nF Figure 12 Evaluation Board LK2 TO BE FITTED FOR NORMAL OPERATION W R7 13K3 C9 100nF C8 4u7F 1nF R13 16R 16R 16R RF3 COMP O/P C4 R12 R11 1nF C21 0R 1K C14 4n7F R10 C5 1nF VCC LK1 LK +8V +22V +5V POWER CONNECTOR 1 2 3 4 5 J1 R9 8V VCC T1 BCW31 R8 22K 2 1 1nF C20 1 2 C19 100pF 1 8V VARACTOR RF INPUT RF1 J2 +8V R14 68R GND POS_2000 7 POS_2000 POS-2000 TUNING RANGE = 1370MHz - 2000MHz 8 VT RF OUT 10 2 C7 C10 C16 100nF 100pF 4u7F SP5748 Advance Information SP5748 Advance Information Top view Bottom view Figure 13 11 SP5748 Advance Information VREF VCC 500 500 CHARGE PUMP RF INPUTS 200 RF inputs Loop amplifier VCC PORT 25K BIAS Disable, Enable, Data and Clock inputs Output Ports VCC VCC CRYSTAL REF 1.2mA CRYSTAL CAP Reference oscillator Reference output Figure 14 Input/Output interface cicruits 12 DRIVE http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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