® SP703/SP704 Low Power Microprocessor Supervisory with Battery Switch-Over ■ Precision Voltage Monitor: SP703 at 4.65V SP704 at 4.40V ■ Reset Time Delay - 200ms ■ Debounced TTL/CMOS Compatible Manual - Reset Input ■ Minimum component count ■ 60µA Maximum Operating Supply Current ■ 0.6µA Maximum Battery Backup Current ■ 0.1µA Maximum Battery Standby Current ■ Power Switching 250mA Output in VCC Mode (0.6Ω) 25mA Output in Battery Mode (5Ω) ■ Voltage Monitor for Power Fail or Low Battery Warning ■ Available in 8 pin SO and DIP packages ■ RESET asserted down to VCC = 1V ■ Pin Compatible Upgrades to MAX703/MAX704 DESCRIPTION The SP703/704 devices are microprocessor (µP) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The series will significantly improve system reliability and operational efficiency when compared to discrete solutions. The features of the SP703/704 devices include a manual reset input, a µP reset and backup-battery switchover, and powerfailure warning. The series is ideal for applications in computers, controllers, intelligent instruments and automotive systems. All designs where it is critical to monitor the power supply to the µP and its related digital components will find the series to be an ideal solution. VBATT VOUT 1 8 VBATT VCC 2 7 RESET GND 3 6 MR PFI 4 5 BATTERY SWITCHOVER CIRCUITRY VCC RESET GENERATOR VOUT RESET 1.25V MR PFI PFO PFO 1.25V PINOUT SP703/704DS/07 INTERNAL BLOCK DIAGRAM SP703/704 Low Power Microprocessor Supervisory 1 © Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC........................................................-0.3V to 6.0V VBATT.....................................................-0.3V to 6.0V All Other Inputs......................................-0.3V to (VCC +0.3V) Input Current: VCC.........................................................250mA VBATT........................................................50mA GND........................................................20mA Output Current: VOUT.....Short-Circuit Protected for up to 10sec All Other Inputs.................................20mA Rate of Rise, VCC,VBATT..................100V/µs Continuous Power Dissipation.......500mW Storage Temperature.......-65°C to +160°C Lead Temperature(soldering,10sec).................+300°C ESD Rating.............................4kV Human Body Model SPECIFICATIONS Vcc=4.75v to 5.50V for SP703, VCC = 4.50V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted. PARAMETERS Operating Voltage Range, MIN. TYP. MAX. UNITS 5.5 Volts 35 60 µA 0.001 0.6 µA 0.02 µA 0 CONDITIONS VCC or VBATT, NOTE 1 Supply Current, ISUPPLY, ISUPPLY in Battery Backup Mode, VCC = 0V, VBATT = 2.8V VBATT Standby Current, NOTE 2 VOUT Output -0.1 excluding IOUT VCC > VBATT + 0.2V VCC - 0.1 VCC - 0.03 VCC - 0.15 Volts IOUT = 50mA IOUT = 250mA VBATT -0.15 VBATT - 0.04 VBATT - 0.20 Volts IOUT = 5mA IOUT = 25mA Battery Switch Threshold, VCC to VBATT 20 -20 mV Power-up Power-down Battery Switchover Hysteresis 40 mV Peak to Peak VOUT in Battery-Backup Mode VCC < VBATT - 0.2V Reset Threshold SP703/704DS/07 4.50 4.25 4.65 4.40 4.75 4.50 Volts SP703 SP704 SP703/704 Low Power Microprocessor Supervisory 2 © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) Vcc=4.75V to 5.50V for SP703, VCC = 4.5 0V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted. PARAMETERS MIN. Reset Threshold Hysteresis TYP. MAX. 40 Reset Pulse Width, tRS 140 RESET Output Voltage VCC - 1.5 200 2.0 MR Minimum Pulse Width 150 CONDITIONS mV Peak to Peak ms ISOURCE = 800µA 0.1 0.004 MR Input Threshold LOW HIGH 280 UNITS 0.4 0.3 Volts 0.8 V ns MR to RESET Delay 250 ns MR Pull Up Current 100 250 600 µA PFI Input Threshold 1.200 1.250 1.300 Volts -25 0.01 25 nA PFI Input Current PFO Output Voltage ISINK = 3.2mA ISINK = 50µA, VCC = 1.0V VCC - 1.5 0.1 0.4 Volts MR=0V ISOURCE = 800µA ISINK = 3.2mA NOTE 1: Either VCC or VBATT can go to 0V if the other is greater than 2.0V. NOTE 2: "-" equals the battery-charging current, "+" equals the battery-discharging current. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 3 © Copyright 2000 Sipex Corporation PINOUT INTERNAL BLOCK DIAGRAM VBATT VOUT 1 8 VBATT VCC 2 7 RESET GND 3 6 MR PFI 4 5 PFO BATTERY SWITCHOVER CIRCUITRY VCC RESET GENERATOR VOUT RESET 1.25V MR PFI PIN ASSIGNMENTS Pin 1 —VOUT — Output Supply Voltage. VOUT connects to VCC when VCC is greater than VBATT and VCC is above the reset threshold. When VCC falls below VBATT and VCC is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. PFO 1.25V Pin 8 — VBATT — Backup-Battery Input. When VCC falls below the reset threshold, VBATT will be switched to VOUT if VBATT is 20mV greater than VCC. When VCC rises 20mV above VBATT, VOUT will be reconnected to VCC. The 40mV hysteresis prevents repeated switching if VCC falls slowly. Pin 2 — VCC — +5V Supply Input Pin3 — GND — Ground reference for all signals Pin 4 — PFI — Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or VOUT when not used. Pin 5 — PFO — Power-Fail Output. Pin 6 — MR — Manual Reset Input. This input generates a reset pulse when pulled below 0.8V. This active LOW input is TTL/ CMOS compatible and can be shorted to ground with a switch. It has an internal 250µA (typical) pull-up current. Leave this pin floating when not used. Pin 7 — RESET (Active Low)– Reset Output. RESET Output goes low whenever VCC falls below the reset threshold or whenever MR is pulled below 0.8V for longer than 150nS. RESET remains low for 200ms after VCC crosses the reset threshold voltage on power-up or after being triggered by MR. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 4 © Copyright 2000 Sipex Corporation TYPICAL CHARACTERISTICS (25oC, unless otherwise noted) VCC Supply Current vs. Temperature (Normal Mode) 1.9 1.4 0.9 0 30 60 90 1.250 1.248 1.246 -60 5 VBATT=4.5V 0 -60 0.7 0.6 0.5 0.4 0.3 -30 0 30 60 90 120 150 -60 -30 Temperature Deg. C 212 Reset Delay (mS) VCC=5V,VBATT=2.8V 500 Soucing Current 400 300 200 VCC=0V,VBATT=2.8V Sink Current -30 0 30 60 90 Temperature Deg. C SP703/704DS/07 30 60 90 120 150 120 150 VCC=0V to 5V Step, VBATT=2.8V 210 208 206 204 202 200 -60 -30 0 30 60 90 90 120 150 -30 0 30 60 90 120 150 Temperature Deg. C Battery Current vs. VCC Voltage 120 150 Temperature Deg. C SP703/704 Low Power Microprocessor Supervisory 5 60 VBATT=0V Power Down SP703 -60 Reset Delay vs. Temperature 600 100 0 4.70 4.69 4.68 4.67 4.66 4.65 4.64 4.63 4.62 4.61 4.60 Temperature Deg. C Reset Output Resistance vs. Temperature 0 -60 Reset Threshold (V) Resistance (ohms) VBATT=2.8V VCC=5V VBATT=0V 0.8 30 Reset Threshold vs. Temperature 0.9 VBATT=2V 10 0 Temperature Deg. C VCC to VOUT On Resistance vs. Temperature 15 VCC=0V -30 Temperature Deg. C VBATT to VOUT ON Resistance vs. Temperature Resistance (ohms) 1.252 -0.1 -60 -40 -20 0 20 40 60 80 100 120 140 120 150 VCC=5V VBATT=0 NO LOAD ON PFO 1.254 0.4 Temperature Deg. C Resistance (ohms) 1.256 PFI Threshold (V) 2.4 VCC=0V VBATT=2.8V VBATT Current(µA) Log Scale VCC Current (µA) 2.9 VBATT Current (µA) VCC=5V VBATT=2.8V 51 47 43 39 35 31 27 23 19 -60 -30 PFI Threshold vs. Temperature Battery Supply Current vs. Temperature (Backup Mode) IE+2 IE+1 IE+0 IE-1 IE-2 IE-3 IE-4 IE-5 IE-6 IE-7 IE-8 VBATT=2.8V .0000 VCC (0.5V/div) 5.000 © Copyright 2000 Sipex Corporation 1000 1000 VBATT=4.5V VCC=0V Slope=5Ω Voltage Drop(mV) Voltage Drop(mV) VCC=4.5V VBATT=0V Slope=0.6Ω 100 10 1 1 10 100 100 10 1 1000 1 10 IOUT (mA) 100 IOUT (mA) Figure 2. VBATT to VOUT Vs. Output Current Figure 1. VCC to VOUT Vs. Output Current VCC VBATT = 0V TA = +25 C VCC VBATT = 0V TA = 25oC 2V div VCC 0V 2KΩ RESET RESET RESET 0V 330pF GND 1sec/div Figure 3A. SP703 RESET Output Voltage vs. Supply Voltage SP703/704DS/07 Figure 3B. Circuit for the RESET Output Voltage vs. Supply Voltage SP703/704 Low Power Microprocessor Supervisory 6 © Copyright 2000 Sipex Corporation VCC VCC +5V TA = +25 C +4V VCC RESET +5V 10KΩ RESET 0V 30pF GND 2µs/div Figure 4B. Circuit for the RESET Response Time Figure 4A. SP703 RESET Response Time +5V VCC = 5V VBATT = 0V +1.3V PFI VCC = +5V TA = +25 C +1.2V 5V 1KΩ PFO PFI 0V +1.25V PFO 30pF 500ns/div Figure 5B. Circuit for the Power-Fail Comparator Response Time (FALL) Figure 5A. Power-Fail Comparator Response Time (FALL) SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 7 © Copyright 2000 Sipex Corporation VCC = 5V VBATT = 0V PFI +1.3V +5V VCC = +5V TA = +25 C +1.2V PFI PFO 3V PFO 30pF +1.25V 0V 1KΩ 2µs/div Figure 6A. Power-Fail Comparator Response Time (RISE) Figure 6B. Circuit for the Power-Fail Comparator Response Time (RISE) +5V VCC 0V +5V RESET tRS 0V +5V VOUT 3.0V 0V +5V PFO 0V VBATT = PFI = 3.0V Figure 7. Timing Diagram SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 8 © Copyright 2000 Sipex Corporation FEATURES THEORY OF OPERATION The SP703/704 devices provide four key functions: 1. A battery backup switching for CMOS RAM, CMOS microprocessors, or other logic. 2. A reset output during power-up, power-down and brownout conditions. 3. A reset pulse if the manual reset has been pulled below 0.8V for at least 150ns. 4. A 1.25V threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than +5V. Reset Output The microprocessor's (µP's) reset input starts the µP in a known state. When the µP is in an unknown state, it should be held in reset. The SP703/704 assert reset during power-up and prevent code execution errors during powerdown or brownout conditions. On power-up, once VCC reaches 1V, RESET is guaranteed to be a logic low. As VCC rises, RESET remains low. When VCC exceeds the reset threshold, RESET will remain low for 200ms, Figure 9. If a brownout condition occurs and VCC dips below the reset threshold, RESET is triggered. Each time RESET is triggered, it stays low for the reset pulse width interval. If a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. On power-down, once VCC goes below the threshold, RESET is guaranteed to be logic low until VCC drops below 1V. RESET is also triggered by a manual reset The SP703/704 devices differ only in their supply voltage monitor level. The SP703 generates a reset when VCC drops below 4.65V while the SP704 generates a reset below 4.4V. The SP703/704 devices are ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. All designs into an environment where it is critical to monitor the power supply to the µP and its related digital components will find the SP703/704 ideal. Regulated +5V Unregulated DC 0.1µF VCC VCC µP RESET NMI R1 RESET PFI PFO MR GND BUS Pushbutton Switch CMOS RAM R2 VOUT VCC VBATT GND 3.6V Lithium Battery GND Figure 8. Typical Operating Circuit SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 9 © Copyright 2000 Sipex Corporation Power-Fail Comparator Backup-Battery Switchover The Power-Fail Comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). The PFI input is compared to an internal 1.25V reference. If PFI is less than 1.25V, PFO goes low. The external voltage divider drives PFI to sense the unregulated DC input to the +5V regulator. The voltage-divider ratio can be chosen such that the voltage at PFI falls below 1.25V just before the +5V regulator drops out. PFO then triggers an interrupt which signals the µP to prepare for power-down. In the event of a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at VBATT, the RAM is assured to have power if VCC fails. As long as VCC exceeds the reset threshold, VOUT connects to VCC through a 0.6Ω PMOS power switch. Once VCC falls below the reset threshold, VCC or VBATT, whichever is higher, switches to VOUT. VBATT connects to VOUT through a 5Ω switch only when VCC is below the reset threshold and VBATT is greater than VCC. When VCC exceeds the reset threshold, it is connected to VOUT, regardless of the voltage applied to VBATT Figure 9. During this time, the diode (D1) between VBATT and VOUT will conduct current from VBATT to VOUT if VBATT is more than .6V above VOUT. When VBATT connects to VOUT, the power-fail comparator is turned off and PFO is forced low to conserve backup-battery power. VBATT SW1 When VBATT connects to VOUT, backup mode is activated and the internal circuitry will be powered from the battery Figure 10. When VCC is just below VBATT, in the backup mode the current drawn from VBATT will be typically 30µA. When VCC drops to more than 1V below VBATT, the internal switchover comparator shuts off and the supply current falls to less than 0.6µA. VCC D2 D1 SW2 D3 VOUT GND CONDITION SW1 SW2 VCC > Reset Threshold Open Closed VCC < Reset Threshold and VCC > VBATT Open Closed VCC < Reset Threshold and VCC < VBATT Closed Open Reset Threshold = 4.65V in SP703 Reset Threshold = 4.40V in SP704 Figure 9. BACKUP-BATTERY Switchover Block Diagram SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 10 © Copyright 2000 Sipex Corporation SIGNAL STATUS VCC Disconnected from VOUT VOUT Connected to VBATT through an internal 8Ω PMOS switch VBATT PFI VCC VBATT Connected to VOUT. Current drawn from the battery is less than 0.6µA, as long as VCC < VBATT - 1V. VOUT SP703 CONNECT TO STATIC RAM RESET 0.1F CONNECT TO µP GND Power-fail comparator is disabled. PFO Logic low RESET Logic low MR +5V Figure 12. Backup Power Source Using High Capacity Capacitor with SP703 and a +5V ±5% Supply If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. Manual Reset is disabled Figure 10. Input and Output Status in Battery-Backup Mode. To enter the Battery-Backup mode, VCC must be less than the Reset threshold and less than VBATT. Leakage current through the capacitor charging diode and the SP703/704 internal power diode eventually discharges the capacitor to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at VCC, the capacitor on VBATT discharges through VCC until VBATT reaches the reset threshold; the SP703/704 then switches to battery-backup mode. Using a High Capacity Capacitor as a Backup Power Source VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically +20mV centered at VBATT, allowing use of a capacitor and a simple charging circuit as a backup source (see Figure 12). PART NUMBER MAXIMUM BACKUP-BATTERY VOLTAGE [V] SP703 4.80 SP704 4.55 +5V VCC VOUT VBATT SP704 0.1F RESET 100KΩ Figure 11. Allowable BACKUP-BATTERY Voltages CONNECT TO STATIC RAM CONNECT TO µP GND Figure 13. Backup Power Source Using High Capacity Capacitor with SP704 and a +5V ±10% Supply SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 11 © Copyright 2000 Sipex Corporation Operation Without a Backup Power Source +5V VIN VCC If a backup power source is not used, ground VBATT and connect VOUT to VCC. Since there is no need to switch over to any backup power source, VOUT does not need to be switched. A direct connection to VCC eliminates any voltage drops across the switch which may push VOUT below VCC. R1 PFI R2 *C1 R3 PFO *optional connect to µP GND VTRIP = 1.25 R2 = VL - 1.25 + 5.0 - 1.25 R3 R1 The backup battery can be removed while VCC remains valid, without danger of triggering RESET/RESET. As long as VCC stays above the reset threshold, battery-backup mode cannot be entered. 1.25 R2 || R3 R1 + R2 || R3 Adding Hysteresis to the Power-Fail Comparator VH = PFO +5V 0V 0V Replacing the Backup Battery 1.25 R2 R1 + R2 Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is close to its trip point. Figure 14 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to its trip point (VTRIP). R3 adds the hysteresis. It will typically be an order of magnitude greater (about 10 times) than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10KΩ so it does not load down the PFO pin. Capacitor C1 adds additional noise rejection. VIN VL VTRIP VH Figure 14. Adding Hysteresis to the POWER-FAIL Comparator Allowable Backup Power-Source Batteries Lithium batteries work very well as backup batteries due to very low self-discharge rate and high energy density. Single lithium batteries with open-circuit voltages of 3.0V to 3.6V are ideal. Any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3V can be connected directly to the VBATT input of this series with no additional circuitry; see Figure 8. However, batteries with open-circuit voltages that are greater than this value cannot be used for backup, as current is sourced into VOUT through the diode (D1 in Figure 9) when VCC is close to the reset threshold. SP703/704DS/07 Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply rail using the circuit of Figure 15. When the negative rail is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and the resistors, R1 and R2. SP703/704 Low Power Microprocessor Supervisory 12 © Copyright 2000 Sipex Corporation +5V Buffered RESET connects to System Components VCC R1 +5V PFI +5V VCC R2 VCC PFO µP V- RESET RESET 4.7KΩ GND 5.0 - 1.25 = 1.25 - VTRIP R2 R1 GND PFO Figure 16. Interfacing to Microprocessors with Bidirectional RESET I/O +5V *VTRIP GND 0V 0V V- *VTRIP is a negative voltage Figure 15. Monitoring a Negative Voltage Interfacing to Microprocessors with Bidirectional Reset Pins Microprocessors with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with this series' RESET output. If, for example, the RESET output is driven high and the µP wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7KΩ resistor between the RESET output and the µP reset I/O, as in Figure 16. Buffer the RESET output to other system components. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 13 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 e = 0.100 BSC (2.540 BSC) Ø L B1 B eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) SP703/704DS/07 8–PIN A2 0.115/0.195 (2.921/4.953) B 0.014/0.022 (0.356/0.559) B1 0.045/0.070 (1.143/1.778) C 0.008/0.014 (0.203/0.356) D 0.355/0.400 (9.017/10.160) E 0.300/0.325 (7.620/8.255) E1 0.240/0.280 (6.096/7.112) L 0.115/0.150 (2.921/3.810) Ø 0°/ 15° (0°/15°) SP703/704 Low Power Microprocessor Supervisory 14 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) E H h x 45° D A Ø e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) SP703/704DS/07 8–PIN A 0.053/0.069 (1.346/1.748) A1 0.004/0.010 (0.102/0.249 B 0.014/0.019 (0.35/0.49) D 0.189/0.197 (4.80/5.00) E 0.150/0.157 (3.802/3.988) e 0.050 BSC (1.270 BSC) H 0.228/0.244 (5.801/6.198) h 0.010/0.020 (0.254/0.498) L 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) SP703/704 Low Power Microprocessor Supervisory 15 © Copyright 2000 Sipex Corporation ORDERING INFORMATION Model Temperature Range Package Types SP703CN..........................................................0°C to +70°C....................................................8-Pin NSOIC SP703CP........................................................0°C to +70°C.........................................................8-Pin PDIP SP703EN......................................................-40°C to +85°C.....................................................8-Pin NSOIC SP703EP.......................................................-40°C to +85°C....................................................... 8-Pin PDIP SP704CN........................................................0°C to +70°C......................................................8-Pin NSOIC SP704CP........................................................0°C to +70°C......................................................... 8-Pin PDIP SP704EN......................................................-40°C to +85°C................................................... ..8-Pin NSOIC SP704EP.......................................................-40°C to +85°C....................................................... 8-Pin PDIP Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory 16 © Copyright 2000 Sipex Corporation