SSM6618M
N-CHANNEL ENHANCEMENT-MODE POWER MOSFET
Low on-resistance
D
Fast switching speed
D
D
D
Surface-mount package
S
S
25V
R DS(ON)
30mΩ
7A
ID
G
SO-8
BV DSS
S
Description
D
Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
G
S
Absolute Maximum Ratings
Symbol
Parameter
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID @ TA=25°C
ID @ TA=70°C
Rating
Units
25
V
± 20
V
Continuous Drain Current
3
7
A
Continuous Drain Current
3
5.8
A
30
A
1,2
IDM
Pulsed Drain Current
PD @ TA=25°C
Total Power Dissipation
2.5
W
Linear Derating Factor
0.02
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-amb
Rev.2.02 3/21/2004
Parameter
Thermal Resistance Junction-ambient
Max.
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Value
Unit
50
°CW
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SSM6618M
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Typ.
Max. Units
25
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.02
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance
VGS=10V, ID=7A
-
-
30
mΩ
VGS=4.5V, ID=5A
-
-
50
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VGS=0V, ID=250uA
Min.
VDS=10V, ID=7A
-
13
-
S
o
VDS=25V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=20V ,VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS= ± 20V
-
-
±100
nA
ID=7A
-
8.4
-
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=20V
-
2.1
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
4.7
-
nC
VDS=15V
-
6
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
5.2
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω ,VGS=10V
-
18.8
-
ns
tf
Fall Time
RD=15Ω
-
4.4
-
ns
Ciss
Input Capacitance
VGS=0V
-
645
-
pF
Coss
Output Capacitance
VDS=25V
-
150
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
95
-
pF
Min.
Typ.
-
-
7
A
-
-
30
A
-
-
1.2
V
Source-Drain Diode
Symbol
IS
ISM
VSD
Parameter
Test Conditions
VD=VG=0V , VS=1.2V
Continuous Source Current ( Body Diode )
1
Pulsed Source Current ( Body Diode )
Forward On Voltage
2
Tj=25°C, IS=7A, VGS=0V
Max. Units
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on FR4 board, t<10 sec.
Rev.2.02 3/21/2004
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SSM6618M
36
T C =25 C
V GS =4.5V
24
10V
8.0V
6.0V
5.0V
T C =150 o C
ID , Drain Current (A)
ID , Drain Current (A)
36
10V
8.0V
6.0V
5.0V
o
12
24
V GS =4.5V
12
0
0
0
2
3
5
0
6
2
3
5
6
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2
80
I D =7.0A
T C =25 ℃
I D =7.0A
V GS =10V
Normalized RDS(ON)
RDS(ON) (mΩ )
60
40
1.4
0.8
20
0
0.2
2
6
10
14
-50
0
100
150
T j , Junction Temperature ( C)
Fig 3. On-Resistance vs. Gate Voltage
Rev.2.02 3/21/2004
50
o
V GS (V)
Fig 4. Normalized On-Resistance
vs. Junction Temperature
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3 of 6
SSM6618M
8
3
ID , Drain Current (A)
6
PD (W)
2
4
1
2
0
0
25
50
75
100
125
150
0
50
T c , Case Temperature ( o C)
100
150
T c , Case Temperature ( o C)
Fig 5. Maximum Drain Current vs.
Case Temperature
Fig 6. Typical Power Dissipation
1
100
Normalized Thermal Response (R thja)
Duty Factor = 0.5
1ms
10
ID (A)
10ms
100ms
1
1s
T C =25 o C
Single Pulse
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t
0.01
T
Single Pulse
Duty Factor = t/T
Peak Tj = P DM x Rthja + Ta
10s
0.001
0.1
0.1
1
10
100
0.0001
0.001
V DS (V)
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 7. Maximum Safe Operating Area
Rev.2.02 3/21/2004
0.01
Fig 8. Effective Transient Thermal Impedance
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4 of 6
SSM6618M
f=1.0MHz
12
10000
VGS , Gate to Source Voltage (V)
I D =7A
9
V DS =12V
V DS =16V
VDS =20V
1000
C (pF)
Ciss
6
Coss
Crss
100
3
0
10
0
4
8
12
16
1
7
13
19
25
31
V DS (V)
Q G , Total Gate Charge (nC)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
3
100
2.5
10
2
o
o
Tj=25 C
VGS(th) (V)
IS(A)
Tj=150 C
1
1.5
1
0.1
0.5
0
0.01
0
0.4
0.8
1.2
-50
0
Fig 11. Forward Characteristic of
Reverse Diode
Rev.2.02 3/21/2004
50
100
150
T j , Junction Temperature ( o C )
V SD (V)
Fig 12. Gate Threshold Voltage vs.
Junction Temperature
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SSM6618M
VDS
90%
RD
VDS
D
RG
TO THE
OSCILLOSCOPE
0.6 x RATED V DS
G
+
10%
VGS
S
10 v
VGS
-
td(on)
Fig 13. Switching Time Circuit
td(off) tf
tr
Fig 14. Switching Time Waveform
VG
VDS
4.5V
0.8 x RATED V DS
G
S
QG
TO THE
OSCILLOSCOPE
D
QGS
QGD
VGS
+
1~ 3 mA
IG
I
D
Charge
Fig 15. Gate Charge Circuit
Q
Fig 16. Gate Charge Waveform
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.2.02 3/21/2004
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