STA013
STA013B STA013T
®
MPEG 2.5 LAYER III AUDIO DECODER
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL
CHANNEL,
SINGLE
CHANNEL
(MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C INTERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION
LOW POWER CONSUMPTION:
85mW AT 2.4V
CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS
I2C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
10 MHz, 14.31818 MHz, OR 14.7456 MHz
EXTERNAL INPUT CLOCK OR BUILT-IN INDUSTRY STANDARD XTAL OSCILLATOR
DIFFERENT FREQUENCIES MAY BE SUPPORTED UPON REQUEST TO STM
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
February 2004
SO28
TQFP44
LFBGA64
ORDERING NUMBERS: STA013$ (SO28)
STA013T$ (TQFP44)
STA013B$ (LFBGA 8x8)
DESCRIPTION
The STA013 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of decoding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementary streams
compressed by using low sampling rates, as specified by MPEG 2.5.
STA013 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA013 digital output to the
most common DACs architectures used on the
market.
The functional STA013 chip partitioning is described in Fig.1.
1/38
STA013 - STA013B - STA013T
Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning.
RESET
SDA
26
SCL
3
4
I2C CONTROL
SDI
SCKR
BIT_EN
5
6
7
9
SERIAL
INPUT
INTERFACE
BUFFER
PARSER
CHANNEL
CONFIG.
&
VOLUME
CONTROL
MPEG 2.5
LAYER III
DECODER
CORE
SYSTEM & AUDIO CLOCKS
8
SRC_INT
28
21
OUT_CLK/DATA_REQ
20
XTI
XTO
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
10
11
SDO
SCKT
LRCKT
TEST INTERFACE
12
OCLK
24
25
TESTEN
SCANEN
D98AU965
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal resistance Junction to Ambient
Value
85
Unit
°C/W
Value
-0.3 to 4
-0.3 to VDD +0.3
-0.3 to VDD +0.3
Unit
V
V
V
-40 to +150
-40 to +85 (*)
-40 to 125
°C
°C
°C
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Vi
VO
Tstg
Toper
Tj
Parameter
Power Supply
Voltage on Input pins
Voltage on output pins
Storage Temperature
Operative ambient temp
Operating Junction Temperature
(*) guaranteed by design.
2/38
STA013 - STA013B - STA013T
Figure 2. Pin Connection
VDD_1
1
28
OUT_CLK/DATA_REQ
VSS_1
2
27
VSS_5
SDA
3
26
RESET
SCL
4
25
SCANEN
SDI
5
24
TESTEN
SCKR
6
23
VDD_4
BIT_EN
7
22
VSS_4
SRC_INT
8
21
XTI
SDO
9
20
XTO
SCKT
10
19
FILT
LRCKT
11
18
PVSS
OCLK
12
17
PVDD
VSS_2
13
16
VDD_3
VDD_2
14
15
VSS_3
SO28
8
7
6
SCKT
N.C.
SDO
N.C.
SRC_INT
N.C.
BIT_EN
N.C.
SCKR
N.C.
SDI
D98AU911A
44
43
42
41
40
39
38
37
36
35
34
N.C.
1
33
N.C.
LRCKT
2
32
SCL
OCLK
3
31
SDA
N.C.
4
30
VSS_1
VSS_2
5
29
VDD_1
VDD_2
6
28
N.C.
VSS_3
7
27
OUT_CLK/DATA_REC
VDD_3
8
26
VSS_5
N.C.
9
25
RESET
PVDD
10
24
SCANEN
PVSS
11
23
N.C.
5
4
12
13
14
15
16
17
18
19
20
21
22
FILT
XTO
N.C.
XTI
N.C.
N.C.
N.C.
VSS_4
N.C.
VDD_4
TESTEN
TQFP44
3
2
D99AU1019
1
A1 = SDI
B2 = SCKR
D4 = BIT_EN
D1 = SRC_INT
E2 = SDO
F2 = SCKT
H1 = LRCKT
H3 = OCLK
F3 = VSS_2
E4 = VDD_2
G4 = VSS_3
G5 = VDD_3
F5 = PVDD
G6 = PVSS
A
B
C
D
E
F
G
H
G7 = FILT
G8 = XTO
F7 = XTI
E7 = VSS4
C8 = VDD4
D7 = TESTEN
A7 = SCANEN
B6 = RESET
A5 = VSS5
C5 = OUT_CLK/DATA_REQ
B5 = VDD1
B4 = VSS1
A4 = SDA
B3 = SCL
D99AU1085
LFBGA64
3/38
STA013 - STA013B - STA013T
PIN DESCRIPTION
SO28
TQFP44 LFBGA64
Pin Name
Type
Function
1
29
B5
VDD_1
Supply Voltage
2
30
B4
VSS_1
Ground
3
31
A4
SDA
I/O
4
32
B3
SCL
5
34
A1
6
36
7
PAD Description
i2C Serial Data + Acknowledge
CMOS Input Pad Buffer
CMOS 4mA Output Drive
I
I2C Serial Clock
CMOS Input Pad Buffer
SDI
I
Receiver Serial Data
CMOS Input Pad Buffer
B2
SCKR
I
Receiver Serial Clock
CMOS Input Pad Buffer
38
D4
BIT_EN
I
Bit Enable
CMOS Input Pad Buffer
with pull up
8
40
D1
SRC_INT
I
Interrupt Line For S.R. Control
CMOS Input Pad Buffer
9
42
E2
SDO
O
Transmitter Serial Data (PCM
Data)
CMOS 4mA Output Drive
10
44
F2
SCKT
O
Transmitter Serial Clock
CMOS 4mA Output Drive
11
2
H1
LRCKT
O
Transmitter Left/Right Clock
CMOS 4mA Output Drive
12
3
H3
OCLK
I/O
Oversampling Clock for DAC
CMOS Input Pad Buffer
CMOS 4mA Output Drive
13
5
F3
VSS_2
Ground
14
6
E4
VDD_2
Supply Voltage
15
7
G4
VSS_3
Ground
16
8
G5
VDD_3
Supply Voltage
17
10
F5
PVDD
PLL Power
18
11
G6
PVSS
PLL Ground
19
12
G7
FILT
O
PLL Filter Ext. Capacitor Conn.
20
13
G8
XTO
O
Crystal Output
CMOS 4mA Output Drive
21
15
F7
XTI
I
Crystal Input (Clock Input)
Specific Level Input Pad
(see paragraph 2.1)
22
19
E7
VSS_4
Ground
23
21
C8
VDD_4
Supply Voltage
24
22
D7
TESTEN
I
Test Enable
CMOS Input Pad Buffer
with pull up
25
24
A7
SCANEN
I
Scan Enable
CMOS Input Pad Buffer
26
25
B6
RESET
I
System Reset
CMOS Input Pad Buffer
with pull up
27
26
A5
VSS_5
28
27
C5
OUT_CLK/
DATA_REQ
O
Buffered Output Clock/
Data Request Signal
Ground
CMOS 4mA Output Drive
Note: SRC_INT signal is used by STA013 internal software in Broadcast Mode only; in Multimedia mode SRC_INT must be connected to
VDD In functional mode TESTEN must be connected to VDD, SCANEN to ground.
4/38
STA013 - STA013B - STA013T
1. ELECTRICAL CHARACTERISTICS: VDD = 2.7V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
VDD
Parameter
Value
Power Supply Voltage
2.4 to 3.6V
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
IIL
Parameter
Low Level Input Current
Without pull-up device
Test Condition
Vi = 0V
Min.
-10
IIH
High Level Input Current
Without pull-up device
Vi = VDD = 3.6V
-10
Electrostatic Protection
Leakage < 1µA
2000
Vesd
Typ.
Max.
10
Unit
µA
Note
1
10
µA
1
V
2
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
VIL
Parameter
Low Level Input Voltage
VIH
Vol
High Level Input Voltage
Voh
Low Level Output Voltage
High Level Output Voltage
Test Condition
Min.
Typ.
Max.
0.2*VDD
0.8*VDD
Unit
V
Note
V
Iol = Xma
0.4V
0.85*VDD
V
V
1, 2
1, 2
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Ipu
Rpu
Parameter
Pull-up current
Equivalent Pull-up
Resistance
Test Condition
Min.
Typ.
Max.
Unit
Note
Vi = 0V; pin numbers 7, 24
and 26; VDD = 3V
-25
-66
50
-125
µA
kΩ
1
Min.
Typ.
Max.
Unit
Note
Note 1: Min. condition: VDD = 2.4V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
Symbol
PD
Parameter
Power Dissipation
@ VDD = 3V
Test Condition
Sampling_freq ≤24 kHz
Sampling_freq ≤32 kHz
76
79
mW
mW
Sampling_freq ≤48 kHz
85
mW
5/38
STA013 - STA013B - STA013T
Figure 3. Test Circuit
28
OUT_CLK/DATA_REQ
VDD
3
1
4
100nF
9
2
VSS
VDD
10
11
14
12
100nF
5
13
VSS
VDD
6
16
7
100nF
VSS
VDD
15
8
23
21
20
100nF
VDD
17
PVDD
4.7µF
18
27
100nF
26
25
RESET
SDO
SCKT
LRCKT
OCLK
SDI
SCKR
BIT_EN
SCR_INT
XTI
XTO
10K
24
SCANEN
4.7µF
PVDD
VSS
SCL
19
22
VSS
SDA
1K
TESTEN
470pF
4.7nF
PVSS
D98AU966
PVSS
PVSS
Figure 4. Test Load Circuit
Test Load
VDD
Output
SDA
IOL
Other Outputs
OUTPUT
IOL
1mA
IOH
CL
100pF
VREF
3.6V
100µA
100µA
100pF
1.5V
VREF
CL
IOH
D98AU967
2. FUNCTIONAL DESCRIPTION
2.1 - Clock Signal
The STA013 input clock is derivated from an external source or from a industry standard crystal
oscillator, generating input frequencies of 10,
14.31818 or 14.7456 MHz.
Symbol
VIL
VIH
Parameter
Low Level Input Voltage
High Level Input Voltage
Other frequencies may be supported upon request to STMicroelectronics. Each frequency is
supported by downloading a specific configuration file, provided by STM
XTI is an input Pad with specific levels.
Test Condition
Min.
VDD-0.8
Typ.
Max.
VDD-1.8
Unit
V
V
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOS pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
6/38
STA013 - STA013B - STA013T
Figure 5. MPEG Decoder Interfaces.
µP
XTI
XTO
FILT
IIC
SCL
DATA_REQ
PLL
SDA
IIC
SDI
DATA
SOURCE
SDO
MPEG
DECODER
SCKR
SCKT
BIT_EN
DAC
LRCKT
SERIAL AUDIO INTERFACE
RX
TX
OCLK
D98AU912
Figure 6. Serial Input Interface Clocks
DATA
SDI
IGNORED
SCKR
SCLK_POL=0
SCKR
SCLK_POL=4
BIT_EN
DATA VALID
D98AU968A
2.2 - Serial Input Interface
STA013 receives the input data (MSB first)
thought the Serial Input Interface (Fig.5). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock.
The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming
data. For proper operation Bit-EN line shold be
toggled only when SCR is stable low (for both
SCLK_POL configuration) The possible configurations are described in Fig. 6.
DATA IGNORED
2.3 - PLL & Clock Generator System
When STA013 receives the input clock, as described in Section 2.1, and a valid layer III input
bit stream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the
Audio Output Interface the nominal frequencies of
the incoming compressed bit stream. The STA013
PLL block diagram is described in Figure 7.
The audio sample rates are obtained dividing the
oversampling clock (OCLK) by software programmable factors. The operation is done by STA013
embedded software and it is transparent to the
user.
The STA013 PLL can drive directly most of the
commercial DACs families, providing an over
sampling clock, OCLK, obtained dividing the VCO
frequency with a software programmable dividers.
7/38
STA013 - STA013B - STA013T
Figure 7. PLL and Clocks Generation System
XTI
N
PFD
CP
R
C
M
C
VCO
Disable PLL
OCLK
Switching
Circuit
FRAC
X
XTI2OCLK
Update FRAC
DCLK
S
XTI2DSPCLK
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 8 gives a description of the several
STA013 PCM Output Formats.
The sample rates set decoded by STA013 is described in Table 1.
2.4 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following signals:
SDO
PCM Serial Data Output
SCKT
PCM Serial Clock Output
LRCLK
Left/Right Channel Selection Clock
The output samples precision is selectable from
Figure 8. PCM Output Formats
16 SCLK Cycles
LRCKT
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
SDO
M
S
L
S
M
S
L
S
M
S
L
S
M
S
L
S
PCM_ORD = 0
PCM_PREC is 16 bit mode
SDO
L
S
M
S
L
S
M
S
L
S
M
S
L
S
M
S
PCM_ORD = 1
PCM_PREC is 16 bit mode
32 SCLK Cycles
LRCKT
32 SCLK Cycles
32 SCLK Cycles
32 SCLK Cycles
M
S
SDO
SDO
0
SDO
L
S
0
M
S
M
S
L
S
MSB
SDO
M
S
0
M
S
L
S
L
S
0
0 M
S
0
L
S
MSB
L
S
M
S
L
S
M
S
0
M
S
32 SCLK Cycles
L
S
0
0
0
L
S
M
S
MSB
M
S
0
L
S
M
S
L
S
M
S
0
0
0
L
S
L
S
M
S
L
S
M
S
MSB
M
S
PCM_FORMAT = 1
PCM_DIFF = 1
0
L
S
PCM_FORMAT = 0
PCM_DIFF = 0
PCM_FORMAT = 0
PCM_DIFF = 1
0
L
S
PCM_FORMAT = 1
PCM_DIFF = 1
Table 1: MPEG Sampling Rates (KHz)
8/38
MPEG 1
48
44.1
MPEG 2
24
22.05
MPEG 2.5
12
11.025
32
16
8
STA013 - STA013B - STA013T
2.5 - STA013 Operation Mode
The STA013 can work in two different modes,
called Multimedia Mode and Broadcast Mode.
In Multimedia Mode, STA013 decodes the incoming bitstream, acting as a master of the data
communication from the source to itself.
This control is done by a specific buffer management, controlled by STA013 embedded software.
The data source, by monitoring the DATA_REQ
line, send to STA013 the input data, when the
signal is high (default configuration).
The communication is stopped when the
DATA_REQ line is low.
In this mode the fractional part of the PLL is disabled and the audio clocks are generated at
nominal rates. Fig. 9 describes the default
DATA_REQ signal behaviour.
Programming STA013 it is possible to invert the
polarity of the DATA_REQ line (register
REQ_POL).
Figure 9.
SOURCE STOPS TRANSMITTING DATA
the configuration register of the device. The DAC
connected to STA013 can be initialised during
this mode (set MUTE to 1).
PLAY
MUTE
Clock State
X
0
Not Running
PCM Output
0
X
1
Running
0
Init Mode
"PLAY" and "MUTE" changes are ignored in this
mode. The internal state of the decoder will be
updated only when the decoder changes from the
state "init" to the state "decode". The "init" phase
ends when the first decoded samples are at the
output stage of the device.
Decode Mode
This mode is completely described by the following table:
PLAY
MUTE
Clock State
0
0
Not Running
PCM
Output
0
0
1
Running
0
No
1
0
Running
Yes
1
1
Running
Decoded
Samples
0
Decoding
No
SOURCE STOPS TRANSMITTING DATA
DATA_REQ
SOURCE SEND DATA TO STA013
D98AU913
In Broadcast Mode, STA013 works receiving a
bitstream with the input speed regulated by the
source. In this configuration the source has to
guarantee that the bitrate is equivalent to the
nominal bitrate of the decoded stream.
To compensate the difference between the nominal and the real sampling rates, the STA013 embedded software controls the fractional PLL operation. Portable or Mobile applications need
normally to operate in Broadcast Mode. In both
modes the MPEG Synchronisation is automatic
and transparent to the user. To operate in Multimedia mode, the STA013, pin nr. 8, SCR-INT
must be connected to VDD on the application
board.
2.6 - STA013 Decoding States
There are three different decoder states: Idle,
Init, and Decode. Commands to change the decoding states are described in the STA013 I2C
registers description.
Idle Mode
In this mode the decoder is waiting for the RUN
command. This mode should be used to initialise
Yes
3 - I2C BUS SPECIFICATION
The STA013 supports the I2C protocol. This protocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchronisation. The STA013 is always a slave device in
all its communications.
3. 1 - COMMUNICATION PROTOCOL
3.1.0 - Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.
3.1.1 - Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state.
A START condition must precede any command
for data transfer.
9/38
STA013 - STA013B - STA013T
The 7 most significant bits are the device address
identifier, corresponding to the I2C bus definition.
For the STA013 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation
RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the STA013
identifies on the bus the device address and, if a
match is found, it acknowledges the identification
on SDA bus during the 9th bit time. The following
byte after the device identification byte is the internal space address.
3.1.2 - Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition terminates communications between STA013 and the
bus master.
3.1.3 - Acknowledge bit
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending
8 bit of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
3.3 - WRITE OPERATION (see fig. 10)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA013 acknowledges this and waits for the
byte of internal address.
After receiving the internal bytes address the
STA013 again responds with an acknowledge.
3.1.4 - Data input
During the data input the STA013 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
3.3.1 - Byte write
In the byte write mode the master sends one data
byte, this is acknowledged by STA013. The master then terminates the transfer by generating a
STOP condition.
3.2 - DEVICE ADDRESSING
To start communication between the master and
the STA013, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
3.3.2 - Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the
master generating a STOP condition.
Figure 10. Write Mode Sequence
ACK
ACK
DEV-ADDR
BYTE
WRITE
START
ACK
SUB-ADDR
DATA IN
RW
STOP
ACK
MULTIBYTE
WRITE
ACK
DEV-ADDR
START
ACK
ACK
SUB-ADDR
DATA IN
DATA IN
RW
STOP
D98AU825B
Figure 11. Read Mode Sequence
ACK
CURRENT
ADDRESS
READ
DEV-ADDR
START
NO ACK
DATA
RW
STOP
ACK
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
START
RW
START
RW= ACK
HIGH
SEQUENTIAL
CURRENT
READ
DEV-ADDR
ACK
STOP
RW
ACK
DATA
NO ACK
DATA
DEV-ADDR
SUB-ADDR
ACK
NO ACK
DATA
DATA
STOP
START
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
10/38
START
RW
ACK
ACK
DATA
DEV-ADDR
SUB-ADDR
RW
ACK
NO ACK
DATA
DATA
D98AU826A
STOP
STA013 - STA013B - STA013T
3.4 - READ OPERATION (see Fig. 11)
3.4.1 - Current byte address read
The STA013 has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1.
The STA013 acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. However in this case the master does acknowledge
the data byte output and the STA013 continues to
output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
4 - I2C REGISTERS
The following table gives a description of the
MPEG Source Decoder (STA013) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the description of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only.
I2C REGISTERS
HEX_COD
$00
$01
$05
$06
DEC_COD
0
1
5
6
DESCRIPTION
VERSION
IDENT
PLLCTL [7:0]
PLLCTL [20:16] (MF[4:0]=M)
RESET
0xAC
0xA1
0x0C
R/W
R (8)
R (8)
R/W (8)
R/W (8)
$07
$0B
$0C
$0D
$0F
$10
$13
7
11
12
13
15
16
19
PLLCTL [15:12] (IDF[3:0]=N)
reserved
REQ_POL
SCLK_POL
ERROR_CODE
SOFT_RESET
PLAY
0x00
R/W (8)
0x01
0x04
0x00
0x00
0x01
R/W (8)
R/W (8)
R (8)
W (8)
R/W(8)
$14
$16
$18
$40
$41
$42
20
22
24
64
65
66
MUTE
CMD_INTERRUPT
DATA_REQ_ENABLE
SYNCSTATUS
ANCCOUNT_L
ANCCOUNT_H
0x00
0x00
0x00
0x00
0x00
0x00
R/W(8)
R/W(8)
R/W(8)
R (8)
R (8)
R (8)
11/38
STA013 - STA013B - STA013T
I2C REGISTERS (continued)
RESET
R/W
$43
HEX_COD
DEC_COD
67
HEAD_H[23:16]
DESCRIPTION
0x00
R(8)
$44
68
HEAD_M[15:8]
0x00
R(8)
$45
$46
69
70
HEAD_L[7:0]
DLA
0x00
0x00
R(8)
R/W (8)
$47
71
DLB
0xFF
R/W (8)
$48
72
DRA
0x00
R/W (8)
$49
73
DRB
0xFF
R/W (8)
$50
80
MFSDF_441
0x00
R/W (8)
$51
81
PLLFRAC_441_L
0x00
R/W (8)
$52
$54
82
84
PLLFRAC_441_H
PCM DIVIDER
0x00
0x03
R/W (8)
R/W (8)
$55
85
PCMCONF
0x21
R/W (8)
$56
$59
86
89
PCMCROSS
ANC_DATA_1 [7:0]
0x00
0x00
R/W (8)
R (8)
$5A
90
ANC_DATA_2 [15:8]
0x00
R (8)
$5B
$5C
91
92
ANC_DATA_3 [23:16]
ANC_DATA_4 [31:24]
0x00
0x00
R (8)
R (8)
$5D
93
ANC_DATA_5 [39:32]
0x00
R (8)
$61
$63
$64
$65
97
99
100
101
MFSDF (X)
DAC_CLK_MODE
PLLFRAC_L
PLLFRAC_H
0x07
0x00
0x46
0x5B
R/W (8)
R/W (8)
R/W (8)
R/W (8)
$67
$68
103
104
FRAME_CNT_L
FRAME_CNT_M
0x00
0x00
R (8)
R (8)
$69
$6A
$71
105
106
113
FRAME_CNT_H
AVERAGE_BITRATE
SOFTVERSION
0x00
0x00
R (8)
R (8)
R (8)
$72
$77
$78
114
RUN
119
120
TREBLE_FREQUENCY_LOW
TREBLE_FREQUENCY_HIGH
0x00
0x00
0x00
R/W (8)
R/W (8)
R/W (8)
$79
$7A
$7B
$7C
$7D
121
122
123
124
125
BASS_FREQUENCY_LOW
BASS_FREQUENCY_HIGH
TREBLE_ENHANCE
BASS_ENHANCE
TONE_ATTEN
0x00
0x00
0x00
0x00
0x00
R/W (8)
R/W (8)
R/W (8)
R/W (8)
R/W (8)
Note:
1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information.
2) RESERVED: register used for production test only, or for future use.
12/38
STA013 - STA013B - STA013T
4.1 - STA013 REGISTERS DESCRIPTION
The STA013 device includes 128 I2C registers. In
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be accessed (in Read or in Write mode). The ReadOnly registers must never be written.
The following table describes the meaning of the
abbreviations used in the I2C registers description:
Symbol
NA
Comment
Not Applicable
UND
Undefined
NC
RO
No Charge
Read Only
WO
Write Only
R/W
R/WS
Read and Write
Read, Write in specific mode
VERSION
Address: 0x00
Type: RO
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
V8
V7
V6
V5
V4
V3
V2
V1
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
MSB
b7
1
b6
0
b5
1
b4
0
b3
1
b2
1
b1
0
LSB
b0
0
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F
BUF
IS
EN
CLK
IS
PCLK CLK RAC
UPD_FRAC: when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
PLLCTL (M)
Address: 0x06
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA013 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA013, by DSP software.
REQ_POL
Address: 0x0C
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
13/38
STA013 - STA013B - STA013T
Hardware Reset: 0x01
The REQ_POL registers is used to program the
polarity of the DATA_REQ line.
MSB
LSB
ERROR_CODE register contains the last error
occourred if any. The codes can be as follows:
Code
Description
(1)
0x00 No error since the last SW or HW Reset
b7
b6
b5
b4
b3
b2
b1
b0
(2)
0x01
CRC Failure
0
0
0
0
0
0
0
1
(3)
0x02
DATA not available
Default polarity (the source sends data when the
DATA_REQ line is high)
MSB
b7
0
LSB
b6
0
b5
0
b4
0
b3
0
b2
1
b1
0
b0
1
Inverted polarity (the source sends data when the
DATA_REQ line is low)
SOFT_RESET
Address: 0x10
Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
SCKL_POL
Address: 0x0D
Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
LSB
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
b0
0
1
X = don’t care; 0 = normal operation; 1 = reset
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
X
X
X
X
X
0
1
0
0
0
0
When this register is written, a soft reset occours.
The STA013 core command register and the interrupt register are cleared. The decoder goes in
to idle mode.
(1)
(2)
X = don’t care
SCKL_POL is used to select the working polarity
of the Input Serial Clock (SCKR).
(1) If SCKL_POL is set to 0x00, the data (SDI)
are sent with the falling edge of SCKR
and sampled on the rising edge.
(2) If SCKL_POL is set to 0x04, the data (SDI)
are sent with the rising edge of SCKR and
sampled on the falling edge.
PLAY
Address: 0x13
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x01
MSB
b7
X
LSB
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
b0
0
1
X = don’t care; 0 = normal operation; 1 = play
ERROR_CODE
Address: 0x0F
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
The PLAY command is handled according to the
state of the decoder, as described in section 2.5.
PLAY only becomes active when the decoder is
in DECODE mode.
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
X
X
X
X
0
0
0
0
0
0
0
0
1
0
1
0
X = don’t care
14/38
(1)
(2)
(3)
STA013 - STA013B - STA013T
CMD_INTERRUPT
Address: 0x16
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MUTE
Address: 0x14
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
b1
X
X
X
X
X
X
X
LSB
MSB
b0
b7
b6
b5
b4
b3
b2
b1
LSB
0
X
X
X
X
X
X
X
1
b0
0
1
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
X = don’t care;
0 = normal operation;
1 = write into I2C/Ancillary Data
The INTERRUPT is used to give STA013 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x59 ... 0x5D). Every time the
Master has to extract the new buffer content (5
bytes) it writes into this register, setting it to a
non-zero value.
DATA_REQ_ENABLE
Address: 0x18
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
X
X
X
X
X
0
X
X
X
X
X
1
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
b1
LSB
b0
Description
X
X
buffered output clock
X
X
request signal
mode.
The buffered Output Clock has the same frequency than the input clock (XTI)
SYNCSTATUS
Address: 0x40
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
b6
X
b5
X
b4
X
b3
X
b2
X
b1
SS1
0
LSB
b0
SS0
0
Research of sync word
0
1
1
1
0
1
Wait for Confirmation
Synchronised
not used
Description
15/38
STA013 - STA013B - STA013T
ANCCOUNT_L
Address: 0x41
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
HEAD_M[15:8]
MSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
ANCCOUNT_H
Address: 0x42
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
MSB
b7
b6
b5
b4
b3
b2
b1
AC15 AC14 AC13 AC12 AC11 AC10 AC9
LSB
b0
AC8
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
X
X
X
H20
H19
H18
H17
H16
x = don’t care
16/38
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H15
H14
H13
H12
H1‘1
H10
H9
H8
HEAD_L[7:0]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H7
H6
H5
H4
H3
H2
H1
H0
Address: 0x43, 0x44, 0x45
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved
STA013 - STA013B - STA013T
The meaning of the flags are shown in the following tables:
MPEG IDs
IDex
0
ID
0
MPEG 2.5
0
1
reserved
1
1
0
1
MPEG 2
MPEG 1
Layer
in Layer III these two flags must be set always to
"01".
Protection_bit
It equals "1" if no redundancy has been added
and "0" if redundancy has been added.
Bitrate_index
indicates the bitrate (Kbit/sec) depending on the
MPEG ID.
bitrate index
’0000’
’0001’
’0010’
’0011’
’0100’
’0101’
’0110’
’0111’
’1000’
’1001’
’1010’
’1011’
’1100’
’1101’
’1110’
’1111’
ID = 1
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
ID = 0
free
8
16
24
32
40
48
56
64
80
96
112
128
144
160
forbidden
Sampling Frequency
indicates the sampling frequency of the encoded
audio signal (KHz) depending on the MPEG ID
Sampling
Frequency
’00’
’01’
’10’
’11’
MPEG1
MPEG2
MPEG2.5
44.1
48
32
reserved
22.05
24
16
reserved
11.03
12
8
reserved
Padding bit
if this bit equals ’1’, the frame contains an additional slot to adjust the mean bitrate to the sampling frequency, otherwise this bit is set to ’0’.
Private bit
Bit for private use. This bit will not be used in the
future by ISO/IEC.
Mode
Indicates the mode according to the following table. The joint stereo mode is intensity_stereo
and/or ms_stereo.
mode
’00’
mode specified
stereo
’01’
joint stereo (intensity_stereo and/or ms_stereo)
’10’
dual_channel
’11’
single_channel (mono)
Mode extension
These bits are used in joint stereo mode. They indicates which type of joint stereo coding method
is applied. The frequency ranges, over which the
intensity_stereo and ms_stereo modes are applied, are implicit in the algorithm.
Copyright
If this bit is equal to ’0’, there is no copyright on
the bitstream, ’1’ means copyright protected.
Original/Copy
This bit equals ’0’ if the bitstream is a copy, ’1’ if it
is original.
Emphasis
Indicates the type of de-emphasis that shall be
used.
emphasis
’00’
’01’
’10’
’11’
emphasis specified
none
50/15 microseconds
reserved
CCITT J,17
17/38
STA013 - STA013B - STA013T
DLA
Address: 0x46
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
DLA7
b6
DLA6
b5
DLA5
b4
DLA4
b3
DLA3
b2
DLA2
b1
DLA1
b0
DLA0
Description
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
-1dB
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
DLA register is used to attenuate the level of
audio output at the Left Channel using the butterfly shown in Fig. 12. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
Figure 12. Volume Control and Output Setup
DSP Left Channel
DLA
X
Output Left Channel
+
DLB
X
DRB
X
DRA
DSP Right Channel
X
Output Right Channel
+
D97AU667
DLB
Address: 0x47
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
Description
DLB7
0
0
DLB6
0
0
DLB5
0
0
DLB4
0
0
DLB3
0
0
DLB2
0
0
DLB1
0
0
DLB0
0
1
OUTPUT ATTENUATION
NO ATTENUATION
-1dB
0
:
0
0
:
1
0
:
1
0
:
0
0
:
0
0
:
0
1
:
0
0
:
0
-2dB
:
-96dB
DLB register is used to re-direct the Left Channel
on the Right, or to mix both the Channels.
18/38
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
STA013 - STA013B - STA013T
DRA
Address: 0x48
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
0
0
1
0
-2dB
:
:
:
:
:
:
:
:
:
0
1
1
0
0
0
0
0
-96dB
DRA register is used to attenuate the level of
audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
DRB
Address: 0x49
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
b7
b1
LSB
b0
b6
b5
b4
b3
b2
DRB7
0
DRB6
0
DRB5
0
DRB4
0
DRB3
0
DRB2
0
Description
DRB1
0
DRB0
0
OUTPUT ATTENUATION
NO ATTENUATION
0
0
0
0
0
0
0
1
-1dB
0
0
0
0
:
0
:
1
:
1
:
0
0
0
1
0
-2dB
:
0
:
0
:
0
:
0
:
-96dB
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels.
Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel.
MFSDF_441
Address: 0x50
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The VCO output frequency, when decoding
44.1KHz bitstream, is divided by (MFSDF_441 +1)
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
X
X
X
M4
M3
M2
M1
M0
PLLFRAC_441_L
Address: 0x51
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
This register contains the value for the PLL X
driver for the 44.1KHz reference frequency.
b7
PF7
LSB
b6
PF6
b5
PF5
b4
PF4
b3
PF3
b2
PF2
b1
PF1
b0
PF0
19/38
STA013 - STA013B - STA013T
PCMDIVIDER
Address: 0x54
Type: RW
Software Reset: 0x03
Hardware Reset: 0x03
PLLFRAC_441_H
Address: 0x52
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
PF15 PF14 PF13 PF12 PF11 PF10
b1
PF9
LSB
7
6
5
4
3
2
1
0
b0
PF8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
The registers are considered logically concatenated and contain the fractional values for the
PLL, for 44.1KHz reference frequency.
(see also PLLFRAC_L and PLLFRAC_H registers)
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
SCKT_freq =
OCLK_freq
2 (1 + PCM_DIV)
The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression:
1) OCLK_freq = O_FAC * LRCKT_ Freq
(DAC relation)
2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32*
LRCKT_Freq (when 16 bit PCM mode is used)
3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64*
LRCKT_Freq (when 32 bit PCM mode is used)
4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode
5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode
Example for setting:
MSB
b7
PD7
0
0
0
0
0
0
LSB
b6
PD6
0
0
0
0
0
0
b5
PD5
0
0
0
0
0
0
for 16 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 7
O_FAC = 256 ; PCM_DIV = 3
O_FAC = 384 ; PCM_DIV = 5
20/38
b4
PD4
0
0
0
0
0
0
b3
PD3
0
0
0
0
0
0
b2
PD2
1
1
0
0
0
0
b1
PD1
1
0
1
1
1
0
b0
PD0
1
1
1
1
0
1
Description
16 bit mode
16 bit mode
16 bit mode
32 bit mode
32 bit mode
32 bit mode
for 32 bit PCM Mode
O_FAC = 512 ; PCM_DIV = 3
O_FAC = 256 ; PCM_DIV = 1
O_FAC = 384 ; PCM_DIV = 2
512 x Fs
384 x Fs
256 x Fs
512 x Fs
384 x Fs
256 x Fs
STA013 - STA013B - STA013T
PCMCONF
Address: 0x55
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB
b7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
b6
ORD
1
0
b5
DIF
b4
INV
b3
FOR
b2
SCL
LSB
b1
b0
PREC (1) PREC (1)
1
0
0
1
1
0
PCMCONF is used to set the PCM Output Interface configuration:
ORD: PCM order. If this bit is set to’1’, the LS Bit
is transmitted first, otherwise MS Bit is transmiited
first.
DIF: PCM_DIFF. It is used to select the position
of the valid data into the transmitted word. This
setting is significant only in 18/20/24 bit/word
mode.If it is set to ’0’ the word is right-padded,
otherwise it is left-padded.
INV (fig.13): It is used to select the LRCKT clock
polarity. If it is set to ’1’ the polarity is compliant to
I2S format (low -> left , high -> right), otherwise
the LRCKT is inverted. The default value is ’0’. (if
I2S have to be selected, must be set to ’1’ in the
STA013 configuration phase).
Figure 13. LRCKT Polarity Selection
left
LRCKT
left
INV_LRCLK=0
right
right
LRCKT
PCM order the LS bit is transmitted First
PCM order the MS bit is transmitted First
The word is right padded
The word is left padded
LRCKT Polarity compliant to I2S format
LRCKT Polarity inverted
I2S format
Different formats
Data are sent on the rising edge of SCKT
Data are sent on the falling edge of SCKT
16 bit mode (16 slots transmitted)
18 bit mode (18 slots transmitted)
20 bit mode (20 slots transmitted)
24 bit mode (24 slots transmitted)
0
1
0
0
1
1
left
left
INV_LRCLK=1
FOR: FORMAT is used to select the PCM Output
Interface format.
After hw and sw reset the value is set to 0 corresponding to I2S format.
SCL (fig.14): used to select the Transmitter Serial
Clock polarity. If set to ’1’ the data are sent on the
Description
0
1
0
1
rising edge of SCKT and sampled on the falling. If
set to ’0’ , the data are sent on the falling edge
and sampled on the rising. This last option is the
most commonly used by the commercial DACs.
The default configuration for this flag is ’0’.
Figure 14. SCKT Polarity Selection
SCKT
SDO
INV_SCLK=0
SCKT
SDO
INV_SCLK=1
PREC [1:0]: PCM PRECISION
It is used to select the PCM samples precision, as
follows:
’00’: 16 bit mode (16 slots transmitted)
’01’: 18 bit mode (32 slots transmitted)
’10’: 20 bit mode (32 slots transmitted)
’11’: 24 bit mode (32 slots transmitted)
The PCM samples precision in STA013 can be
16 or 18-20-24 bits.
When STA013 operates in 16 (18-20-24) bits
mode, the number of bits transmitted during a
LRCLT period is 32 (64).
21/38
STA013 - STA013B - STA013T
PCMCROSS
Address: 0x56
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
X
X
X
0
0
Left channel is mapped on the left output.
Right channel is mapped on the Right output
Description
X
X
X
X
X
X
0
1
Left channel is duplicated on both Output channels.
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
1
Right channel is duplicated on both Output channels
Right and Left channels are toggled
The default configuration for this register is ’0x00’.
The value is changed by the internal STA013
Core, to set the clocks frequencies, according to
the incoming bitstream. This value can be even
set by the user to select the PCM interface configuration.
The VCO output frequency is divided by (X+1).
This register is a reference for 32KHz and 48 KHz
input bitstream.
ANCILLARY DATA BUFFER
Address: 0x59 - 0x5D
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
STA013 can extract max 56 bytes/MPEG frame.
To know the number of A.D. bits available every
MPEG frame, the ANCCOUNT_L and ANCCOUNT_H registers (0x41 and 0x42) have to be
read.
The buffer dimension is 5 bytes, written by
STA013 core in sequential order. The timing information to read the buffer can be obtained by
reading the FRAME_CNT registers (0x67 - 0x69).
To fill up the buffer with a new 5-bytes slot, the
STA013 waits until a CMD_INTERRUPT register
is written by the master.
MFSDF (X)
Address: 0x61
Type: R/W
Software Reset: 0x07
Hardware Reset: 0x07
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
X
X
X
M4
M3
M2
M1
M0
The register contains the values for PLL X divider
(see Fig. 7).
22/38
DAC_CLK_MODE
Address: 0x63
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
LSB
b0
MODE
This register is used to select the operating mode
for OCLK clock signal.
If it is set to ’1’, the OCLK frequency is fixed, and
it is mantained to the value fixed by the user even
if the sampling frequency of the incoming bitstream changes.
It the MODE flag is set to ’0’, the OCLK frequency
changes, and can be set to (512, 384, 256) * Fs.
The default configuration for this mode is 256 *
Fs.
When this mode is selected, the default OCLK
frequency is 12.288 MHz.
STA013 - STA013B - STA013T
PLLFRAC_L ([7:0])
FRAME_CNT_H
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016
PLLFRAC_H ([15:8])
MSB
b7
LSB
b6
b5
b4
b3
b2
PF15 PF14 PF13 PF12 PF11 PF10
b1
b0
PF9
PF8
The three registers are considered logically concatenated and compose the Global Frame
Counter as described in the table.
It is updated at every decoded MPEG Frame.
The registers are reset on both hardware and
software reset.
Address: 0x64 - 0x65
Type: R/W
Software Reset: 0x46 | 0x5B
Hardware Reset: 0xNA | 0x5B
The registers are considered logically concatenated and contain the fractional values for the
PLL, used to select the internal configuration.
After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved.
The following formula describes the relationships
among all the STA013 fractional PLL parameters:
FRAC
1 MCLK_freq
OCLK_Freq =
⋅ N + 1 ⋅ M + 1 + 65536
X
1
+
where:
FRAC=256 x FRAC_H + FRAC_L (decimal)
These registers are a reference for 48 / 24 / 12 /
32 / 16 / 8KHz audio.
MSB
LSB
b6
FC6
b5
FC5
b4
FC4
b3
FC3
b2
FC2
b1
FC1
b0
FC0
FRAME_CNT_M
MSB
b7
b6
b5
AVERAGE_BITRATE
Address: 0x6A
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
b0
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
AVERAGE_BITRATE is a read-only register and
it contains the average bitrate of the incoming bitstream. The value is rounded with an accuracy of
1 Kbit/sec.
SOFTVERSION
FRAME_CNT_L
b7
FC7
Address: 0x67, 0x68, 0x69
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
b4
b3
b2
b1
FC15 FC14 FC13 FC12 FC11 FC10 FC9
LSB
b0
FC8
Address: 0x71
Type: RO
MSB
b7
SV7
b6
SV6
b5
SV5
b4
SV4
b3
SV3
b2
SV2
b1
SV1
LSB
b0
SV0
After the STA013 boot, this register contains the
version code of the embedded software.
23/38
STA013 - STA013B - STA013T
RUN
BASS_FREQUENCY_LOW
Address: 0x72
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
Address: 0x79
Software Reset: 0x00
Hardware Reset: 0x00
MSB
MSB
b7
X
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
LSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
b0
RUN
BF7
BF6
BF5
BF4
BF3
BF2
BF1
BF0
b2
b1
LSB
b0
BF9
BF8
BASS_FREQUENCY_HIGH
Setting this register to 1, STA013 leaves the idle
state, starting the decoding process.
The Microcontroller is allowed to set the RUN
flag, once all the control registers have been initialized.
Address: 0x7A
Software Reset: 0x00
Hardware Reset: 0x00
TREBLE_FREQUENCY_LOW
MSB
b7
Address: 0x77
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
BF15 BF14 BF13 BF12 BF11 BF10
MSB
b7
TF7
LSB
b6
TF6
b5
TF5
b4
TF4
b3
TF3
b2
TF2
b1
TF1
b0
TF0
b6
b5
b4
b3
The registers BASS_FREQUENCY_HIGH and
BASS_FREQUENCY_LOW, logically concatenated as a 16 bit wide register, are used to select
the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By
setting the BASS_FREQUENCY registers, the
following rules must be kept:
Bass_Freq <= Treble_Freq
TREBLE_FREQUENCY_HIGH
Bass_Freq > 0
(suggested range: 20 Hz < Bass_Freq < 750 Hz)
Example:
Bass = 200Hz
Treble = 3kHz
Address: 0x78
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
b6
b5
b4
b3
b2
TF15 TF14 TF13 TF12 TF11 TF10
b1
LSB
b0
TF9
TF8
The registers TREBLE_FREQUENCY-HIGH and
TREBLE_FREQUENCY-LOW, logically concatenated as a 16 bit wide register, are used to select
the frequency, in Hz, where the selected frequency is +12dB respect to the stop band.
By setting these registers, the following rule must
be kept:
Treble_Freq < Fs/2
24/38
TFS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
0
BFS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
STA013 - STA013B - STA013T
Signed number (2 complement)
This register is used to select the enhancement
or attenuation STA013 has to perform on Treble
Frequency range at the digital signal.
A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of
1.5dB.
The allowed Attenuation/Enhancement range is
[-18dB, +18dB].
TREBLE_ENHANCE
Address: 0x7B
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
TE7
LSB
b6
TE6
b5
TE5
b4
TE4
b3
TE3
b2
TE2
b1
TE1
b0
TE0
MSB
LSB
ENHANCE/ATTENUATION
b7
b6
b5
b4
b3
b2
b1
b0
1.5dB step
0
0
0
0
1
1
0
0
+18
0
0
0
0
1
0
1
1
+16.5
0
0
0
0
1
0
1
0
+15
0
0
0
0
1
0
0
1
+13.5
.
.
.
0
0
0
0
0
0
0
1
+1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-1
.
.
.
1
1
1
1
0
1
1
1
-13.5
1
1
1
1
0
1
1
0
-15
1
1
1
1
0
1
0
0
-16.5
1
1
1
1
0
1
0
0
-18
25/38
STA013 - STA013B - STA013T
Signed number (2 complement)
This register is used to select the enhancement
or attenuation STA013 has to perform on Bass
Frequency range at the digital signal.
A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of
1.5dB.
The allowed Attenuation/Enhancement range is
[-18dB, +18dB].
BASS_ENHANCE
Address: 0x7C
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
BE7
LSB
b6
BE6
b5
BE5
b4
BE4
b3
BE3
b2
BE2
b1
BE1
b0
BE0
MSB
LSB
ENHANCE/ATTENUATION
b7
b6
b5
b4
b3
b2
b1
b0
1.5dB step
0
0
0
0
1
1
0
0
+18
0
0
0
0
1
0
1
1
+16.5
0
0
0
0
1
0
1
0
+15
0
0
0
0
1
0
0
1
+13.5
.
.
.
0
0
0
0
0
0
0
1
+1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-1
.
.
.
1
1
1
1
0
1
1
1
-13.5
1
1
1
1
0
1
1
0
-15
1
1
1
1
0
1
0
0
-16.5
1
1
1
1
0
1
0
0
-18
26/38
STA013 - STA013B - STA013T
In the digital output audio, the full signal is
achieved with 0 dB of attenuation. For this reason, before applying Bass & Treble Control, the
user has to set the TONE_ATTEN register to the
maximum value of enhancement is going to perform.
For example, in case of a 0 dB signal (max. level)
only attenuation would be possible. If enhancement is desired, the signal has to be attenuated
accordingly before in order to reserve a margin in dB.
An increment of a decimal unit corresponds to a Tone
Attenuation step of 1.5dB.
TONE_ATTEN
Address: 0x7D
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
TA7
MSB
b7
0
0
0
0
LSB
b6
TA6
b6
0
0
0
0
b5
TA5
b4
TA4
b5
0
0
0
0
b3
TA3
b2
TA2
b4
0
0
0
0
b3
0
0
1
0
b1
TA1
b2
0
0
0
0
b0
TA0
LSB
b0
0
1
0
1
b1
0
0
1
1
ATTENUATION
-1.5dB step
0dB
-1.5dB
-3dB
-4.5dB
.
.
.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
1
0
-15dB
-16.5dB
-18dB
5. GENERAL INFORMATION
5.1. MPEG 2.5 Layer III Algorithm.
DEMULTIPLEXING
&
ERROR CHECK
INVERSE
QUANTISATION
&
DESCALING
HUFFMAN
DECODING
INVERSE
FILTERBANK
IMDCT
STEREOPHONIC AUDIO
SIGNAL (2*768Kbit/s)
SIDE INFORMATION
DECODING
ANCILLARY DATA
D98AU903
ENCODED AUDIO
BITSTREAM (8Kbit/s ... 128Kbit/s)
5.2 - MPEG Ancillary Data Description:
As specifyed in the ISO standard, the MPEG
Layer III frames have a variable bit lenght, and
are constant in time depending on the audio sam-
pling frequencies. The time duration of the Layer
III frames is shown in Tab 2.
Table2: MPEG Layer III Frames Time Duration
Sampling Frequency (KHz)
MPEG Frame Lenght (ms)
48
24
44.1
29
32
36
24
24
22.5
29
16
36
12
48
11.025
48
8
72
27/38
STA013 - STA013B - STA013T
The Ancillary Data extraction on STA013 can be
described as follow:
STA013 has a specific Ancillary Data buffer,
mapped into the I2C registers:
0x59
0x5A
0x5B
0x5C
0x5D
ANC_DATA_1
ANC_DATA_2
ANC_DATA_3
ANC_DATA_4
ANC_DATA_5
specific register, to require the new 5 byte slot to
STA003 is needed.
This register is:
0x16
CMD_INTERRUPT
The interrupt register, is sensitive to any non-zero
value written by the Microcontroller. When this
register is updated the Ancillary Data buffer is
filled up with new values and the registers
0x41
0x42
Since the content of Ancillary Data into an MPEG
Frame STA013 can extract is max. 56 bytes, a
ANCCOUNT_L
ANCCOUNT_H
are updated (decremented) accordingly.
5.3. I/O CELL DESCRIPTION
1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 9, 10, 11, 20, 28
EN
OUTPUT PIN
Z
Z
A
MAX LOAD
100pF
D98AU904
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 12
EN
OUTPUT
PIN
IO
IO
A
ZI
CAPACITANCE
5pF
OUTPUT
PIN
IO
MAX
LOAD
100pF
D98AU905
3) CMOS Inpud Pad Buffer / Pin numbers 4, 5, 6, 8, 21, 25
A
Z
INPUT PIN
A
CAPACITANCE
3.5pF
D98AU906
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 7, 24, 26
A
Z
D98AU907
28/38
INPUT PIN
CAPACITANCE
A
3.5pF
STA013 - STA013B - STA013T
5.4. TIMING DIAGRAMS
5.4.1. Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
D98AU969
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing
(Cload_ OCLK)
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing
(Cload_ OCLK)
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) pad_timing (Cload_ OCLK)
Pad-timing versus load
Load (pF)
25
Pad_timing
2.90ns
50
75
3.82ns
4.68ns
100
5.52ns
Cload_XXX is the load in pF on the XXX output.
pad_timing (Cload_XXX) is the propagation delay
added to the XXX pad due to the load.
b) OCLK in input.
OCLK (INPUT)
thi
tlo
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
toclk
D98AU970
Thi min = 3ns
Tlo min = 3ns
Toclk min = 25ns
tsdo = 5.5 + pad_timing (Cload_SDO) ns
tsckt = 6 + pad_timing (Cload_SCKT) ns
tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
29/38
STA013 - STA013B - STA013T
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN
t_biten
t_biten
tsckr_min_period
tsckr_min_low
SCKR
SCLK_POL=0
tsckr_min_high
IGNORED
SDI
IGNORED
VALID
tsdi_setup
tsdi_hold
D98AU971A
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
BIT_EN
t_biten
t_biten
tsckr_min_period
tsckr_min_low
SCKR
SDI
SCLK_POL=4
tsckr_min_high
IGNORED
IGNORED
VALID
tsdi_setup
tsdi_hold
IGNORED
D99AU1038
tsdi_setup_min = 2ns
tsdi_hold_min = 3ns
tsckr_min_hi = 10ns
tsckr_min_low = 10ns
tsckr_min_lperiod = 50ns
t_biten (min) = 2ns
5.4.3. SRC_INT
This is an asynchronous input used in "broadcast’ mode.
SRC_INT is active low
t_src_hi
SRC_INT
t_src_low
D98AU972
t_src_low min duration is 50ns (1DSP clock period)
t_src_high min duration is 50ns (1DSP clock period)
5.4.4. XTI,XTO and CLK_OUT timings
thi
XTI (INPUT)
tlo
XTO
txto
CLK_OUT
tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns
tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad.
30/38
STA013 - STA013B - STA013T
5.4.5. RESET
The Reset min duration (t_reset_low_min) is 100ns
RESET
treset_low_min
D98AU974
5.5. CONFIGURATION FLOW
HW RESET
set
PCM-DIVIDER
set
PCM-CONF.
set { PLL FRAC_441_H,
PLL FRAC_441_L,
PLL FRAC_H,
PLL FRAC_L }
PCM OUTPUT
INTERFACE
CONFIGURATION
PLL
CONFIGURATION
FOR:
set { MFS DF_441,
MFSDF }
• { 48, 44.1, 32
29, 22.05, 16
12, 11.025, 8 } KHz
set
• MULTIMEDIA
MODE see
{TAB 5 to TAB12}
PLL CTRL
set
SCLK_POL
INPUT SERIAL
CLOCK POLARITY
CONFIGURATION
set
DATA_REQ_ENABLE
DATA REQUEST
PIN ENABLE
REQ_POL
DATA REQUEST
POLARITY
CONFIGURATION
set
set
RUN
THE OVERALL
SETTING STEPS
ARE INCLUDED IN
THE STA013
CONFIGURATION
FILE AND CAN
BE DOWNLOADED
IN ONE STEP.
STM PROVIDES
A SPECIFIC
CONFIGURATION
FILE FOR EACH
SUPPORTED
INPUT CLOCK
FREQUENCY
D98AU975
31/38
STA013 - STA013B - STA013T
Table 5:
PLL Configuration Sequence For
10MHz Input Clock
256 Oversapling Clock
REGISTER
ADDRESS
6
Table 7:
PLL Configuration Sequence For
14.31818MHz Input Clock
256 Oversapling Rathio
reserved
18
REGISTER
ADDRESS
6
11
97
reserved
MFSDF (x)
3
15
NAME
VALUE
VALUE
reserved
12
11
97
reserved
MFSDF (x)
3
15
80
MFSDF-441
16
80
MFSDF-441
16
101
PLLFRAC-H
169
101
PLLFRAC-H
187
82
100
PLLFRAC-441-H
PLLFRAC-L
49
42
82
100
PLLFRAC-441-H
PLLFRAC-L
103
58
81
PLLFRAC-441-L
60
81
PLLFRAC-441-L
119
5
PLLCTRL
161
5
PLLCTRL
161
Table 6:
PLL Configuration Sequence For
10MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
32/38
NAME
NAME
Table 8:
PLL Configuration Sequence For
14.31818MHz Input Clock
384 Oversapling Rathio
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
17
6
reserved
11
11
97
80
reserved
MFSDF (x)
MFSDF-441
3
9
10
11
97
80
reserved
MFSDF (x)
MFSDF-441
3
6
7
101
82
PLLFRAC-H
PLLFRAC-441-H
110
160
101
82
PLLFRAC-H
PLLFRAC-441-H
3
157
100
81
5
PLLFRAC-L
152
186
161
100
81
5
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
PLLFRAC-441-L
PLLCTRL
211
157
161
STA013 - STA013B - STA013T
Table 9:
PLL Configuration Sequence For
14.31818MHz Input Clock
512 Oversapling Rathio
REGISTER
ADDRESS
6
Table 11:
PLL Configuration Sequence For
14.7456MHz Input Clock
384 Oversapling Rathio
reserved
11
REGISTER
ADDRESS
6
reserved
10
11
97
reserved
MFSDF (x)
3
6
11
97
reserved
MFSDF (x)
3
8
NAME
VALUE
NAME
VALUE
80
MFSDF-441
7
80
MFSDF-441
9
101
PLLFRAC-H
3
101
PLLFRAC-H
64
82
100
PLLFRAC-441-H
PLLFRAC-L
157
211
82
100
PLLFRAC-441-H
PLLFRAC-L
124
0
81
PLLFRAC-441-L
157
81
PLLFRAC-441-L
5
PLLCTRL
161
5
PLLCTRL
Table 10:
PLL Configuration Sequence For
14.7456MHz Input Clock
256 Oversapling Rathio
REGISTER
ADDRESS
NAME
0
161
Table 12:
PLL Configuration Sequence For
14.7456MHz Input Clock
512 Oversapling Rathio
VALUE
REGISTER
ADDRESS
NAME
VALUE
6
reserved
12
6
reserved
9
11
97
reserved
MFSDF (x)
3
15
11
97
reserved
MFSDF (x)
2
5
80
101
82
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
16
85
4
80
101
82
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
100
81
5
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
85
0
161
100
81
5
PLLFRAC-441-L
PLLCTRL
PLLFRAC-L
6
0
184
0
0
161
33/38
STA013 - STA013B - STA013T
5.6. STA013 CONFIGURATION FILE FORMAT
The STA013 Configuration File is an ASCII format. An example of the file format is the following:
58 1
42 4
128 15
............
It is a sequence of rows and each one can be interpreted as an I2C command.
The first part of the row is the I2C address (register) and the second one is the I2C data (value).
To download the STA013 configuration file into the device, a sequence of write operation to STA013 I2C
interface must be performed.
The following program describes the I2C routine to be implemented for the configuration driver:
42
4
2
I C REGISTER VALUE
I2C SUB-ADDRESS
D98AU976
STA013 Configuration Code (pseudo code)
download cfg - file
{
fopen (cfg_file);
fp:=1;
do {
I2C_start_cond;
I2C_write_dev_addr;
I2C_write_subaddress (fp);
I2C_write_data (fp);
I2C_stop_cond;
fp++;
}
while (!EDF)
}
/*set file pointer to first row */
/* generate I2C start condition for STA013 device address */
/* write STA013 device address
*/
/* write subaddress
*/
/* write data
*/
/* generate I2C stop condition
*/
/* update pointer to new file row
*/
/* repeat until End of File
/* End routine
*/
*/
Note:1
STA013 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation.
The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable.
Note 2:
Refer also to the application note 1090
34/38
STA013 - STA013B - STA013T
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
OUTLINE AND
MECHANICAL DATA
SO28
8 ° (max.)
35/38
STA013 - STA013B - STA013T
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
D
11.80
D1
9.80
D3
0.063
0.15
0.002
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.015
0.018
0.20
0.004
12.00
12.20
0.464
0.472
0.480
10.00
10.20
0.386
0.394
0.401
8.00
0.006
0.008
0.315
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
e
0.80
0.031
L
0.45
0.60
L1
0.75
0.018
1.00
k
OUTLINE AND
MECHANICAL DATA
MAX.
0.024
0.030
TQFP44 (10 x 10 x 1.4mm)
0.039
0˚(min.), 3.5˚(typ.), 7˚(max.)
D
D1
A
A2
A1
23
33
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
0076922 D
36/38
STA013 - STA013B - STA013T
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
A
A1
MIN.
TYP.
1.700
0.350
0.400
0.450
MAX.
0.067
0.014
0.016
A2
1.100
0.043
b
0.500
0.20
D
8.000
0.315
D1
5.600
0.220
e
0.800
0.031
E
8.000
0.315
E1
5.600
0.220
0.018
Body: 8 x 8 x 1.7mm
LFBGA64
f
1.200
0.047
0.15
BALL 1 IDENTIFICATION
A
D1
8
7
6
5
4
f
3
2
D
A1
1
f
A
B
C
D
E1
E
E
F
G
H
φ b (64 PLACES)
e
A2
LFBGA64M
37/38
STA013 - STA013B - STA013T
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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