STP100NF04 STB100NF04 N-channel 40V - 0.0043Ω - 120A - TO-220 - D2PAK STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID Pw STP100NF04 40V < 0.0046Ω 120A 300W STB100NF04 40V < 0.0046Ω 120A 300W ■ Standard threshold drive ■ 100% avalanche tested 3 1 D²PAK 3 1 2 TO-220 Description This Power MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STB100NF04 B100NF04 D²PAK Tape & Reel STP100NF04 P100NF04 TO-220 Tube February 2007 Rev 5 1/17 www.st.com 17 Contents: STB100NF04 - STP100NF04 Contents: 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 2.2 Spice Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STB100NF04 - STP100NF04 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source Voltage (VGS=0) 40 V VGS Gate-source Voltage ±20 V ID (1) Drain-current (continuous) at Tc=25°C 120 A ID (1) Drain-current (continuous) at Tc=100°C 120 A IDM(2) Drain-current (pulsed) 480 A PTOT Total dissipation at Tc=25°C 300 W Derating factor 2 W/°C dv/dt(3) Peak Diode Recovery voltage slope 6 V/ns EAS(4) Single Pulse Avalanche Energy 1.2 J Tj Tstg Operating Junction Temperature Storage Temperature -55 to 175 °C 1. Current limited by package 2. Pulse width limited by safe operating area. 3. ISD ≤120A, di/dt ≤300A/µs, VDD < V(BR)DSS. Tj < Tjmax 4. Starting Tj=25°C, ID=60A, VDD=30V Table 2. Symbol Thermal resistance Parameter Value Unit Rthj-case Thermal Resistance Junction-case Max 0.5 °C/W Rthj-pcb Thermal Resistance Junction-pcb Max (see Figure 13) °C/W Rthj-amb Thermal Resistance Junction-ambient (Free Air) Max 62.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C 3/17 Electrical characteristics 2 STB100NF04 - STP100NF04 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS Parameter Test conditions Drain-source Breakdown ID=250µA, VGS=0 Voltage IDSS Zero Gate Voltage Drain VDS=Max Rating Current (VGS=0) VDS=Max Rating Tc=125°C IGSS Gate-body Leakage Current (VDS=0) VGS=±20V VGS(th) Gate Threshold Voltage VDS=VGS, ID=250µA RDS(on) Static Drain-source On Resistance VGS=10V, ID=50A Table 4. Symbol Min. Typ. Max. 40 Unit V 2 1 10 µA µA ±100 nA 4 V 0.0043 0.0046 Ω Dynamic Parameter Test conditions Min Typ. Max. Unit Forward Transconductance VDS=15V, ID=50A 150 S Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS=25V, f=1MHz,VGS=0 5100 1300 160 pF pF pF Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge gfs td(on) tr td(off) tf 4/17 On/off Turn-on Delay Time Rise time Turn-off delay Time Fall Time VDD=32V, ID=120A VGS=10V VDD=20V, ID=60A RG=4.7Ω, VGS=10V (see Figure 21) 110 35 70 35 220 80 50 150 nC nC nC ns ns ns ns STB100NF04 - STP100NF04 Table 5. Symbol Electrical characteristics Source drain diode Parameter Test conditions ISD ISDM(1) Source-drain Current Source-drain Current (pulsed) VSD(2) Forward on Voltage ISD=120A, VGS=0 Reverse Recovery Time Reverse Recovery Charge Reverse recovery Current ISD=120A, VDD=20V, di/dt=100A/µs, Tj=150°C trr Qrr IRRM Min. Typ. 75 185 5 Max. Unit 120 480 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/17 Electrical characteristics STB100NF04 - STP100NF04 2.1 Electrical characteristics (curves) Figure 1. Power Derating vs. Tc Figure 2. Max Id Current vs. Tc Figure 3. Output Characteristics Figure 4. Transfer Characteristics Figure 5. Transconductance Figure 6. Static Drain-source on Resistance 6/17 STB100NF04 - STP100NF04 Electrical characteristics Figure 7. Gate Charge vs. Gate-source Voltage Figure 9. Normalized Gate Threshold Voltage Figure 10. Normalized on Resistance vs. vs. Temperature Temperature Figure 11. Source-Drain Diode Forward Characteristics Figure 8. Capacitance Variations Figure 12. Normalized BVdss vs. Temperature 7/17 Electrical characteristics STB100NF04 - STP100NF04 Figure 13. Thermal Resistance Rthj-pcb vs. PCB Copper Area Figure 14. Thermal Impedance Figure 15. Max Power Dissipation vs. PCB Copper Area Figure 16. Safe Operating Area 8/17 STB100NF04 - STP100NF04 Electrical characteristics Figure 17. Allowable Iav vs. Time in Avalanche The previous curve give the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) = 0.5*(1.3*BVDSS*IAV) EAS(AR) = PD(AVE) * tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche To de rate above 25°C, at fixed IAV, the following equation must be applied: IAV=2*(Tjmax - TCASE) / (1.3*BVDSS * Zth) Where: Zth= K*Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV 9/17 Electrical characteristics 2.2 Spice thermal model Table 6. Spice parameter Parameter Node Value CTHERM1 5-4 0.011 CTHERM1 4-3 0.0012 CTHERM3 3-2 0.05 CTHERM4 2-1 0.1 RTHERM1 5-4 0.09 RTHERM2 4-3 0.02 RTHERM3 3-2 0.11 RTHERM4 2-1 0.17 Figure 18. Spice model schematic 10/17 STB100NF04 - STP100NF04 STB100NF04 - STP100NF04 3 Test circuit Test circuit Figure 19. Unclamped inductive load test circuit Figure 20. Unclamped inductive waveform Figure 21. Switching times test circuit for resistive load Figure 22. Gate charge test circuit Figure 23. Test circuit for inductive load switching Figure 24. Switching time waveform 11/17 Package mechanical data 4 STB100NF04 - STP100NF04 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/17 STB100NF04 - STP100NF04 Package mechanical data TO-220 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 13/17 Package mechanical data STB100NF04 - STP100NF04 D2PAK MECHANICAL DATA TO-247 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 10.4 0.393 D1 E 8 10 E1 0.315 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 R 0º 0.126 0.015 4º 3 V2 0.4 1 14/17 STB100NF04 - STP100NF04 5 Packaging mechanical data Packaging mechanical data D2PAK FOOTPRINT TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0.075 0.082 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 26.4 0.960 1.039 0.059 0795 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 MAX. R 50 1.574 T 0.25 0.35 0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 15/17 Revision history 6 STB100NF04 - STP100NF04 Revision history Table 7. 16/17 Revision history Date Revision Changes 23-Mar-2005 2 New template 01-Mar-2006 3 Removed I²PAK and inserted D²PAK. 04-Sep-2006 4 New template, no content change 20-Feb-2007 5 Typo mistake on page 1 STB100NF04 - STP100NF04 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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