STMICROELECTRONICS STD6NC40

STD6NC40
N-CHANNEL 400V - 0.75Ω - 5A - DPAK / IPAK
PowerMesh™II MOSFET
■
■
■
■
■
■
TYPE
VDSS
RDS(on)
ID
STD6NC40
400V
<1Ω
5A
TYPICAL RDS(on) = 0.75Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
ADD SUFFIX “-1” FOR ORDERING IN IPAK
DESCRIPTION
The PowerMESH™II is the evolution of the first
generation of MESH OVERLAY™. The layout refinements introduced greatly improve the Ron*area
figure of merit while keeping the device at the leading edge for what concerns swithing speed, gate
charge and ruggedness.
3
3
2
1
1
DPAK
IPAK
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
SWITH MODE LOW POWER SUPPLIES
(SMPS)
■ CFL
■
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
VGS
Value
Unit
Drain-source Voltage (VGS = 0)
Parameter
400
V
Drain-gate Voltage (RGS = 20 kΩ)
400
V
Gate- source Voltage
±30
V
ID
Drain Current (continuos) at TC = 25°C
5
A
ID
Drain Current (continuos) at TC = 100°C
3
A
Drain Current (pulsed)
20
A
Total Dissipation at TC = 25°C
55
W
0.44
W/°C
3
V/ns
–65 to 150
°C
150
°C
IDM (■)
PTOT
Derating Factor
dv/dt(1)
Tstg
Tj
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
(•)Pulse width limited by safe operating area
March 2001
(1)ISD ≤5A, di/dt ≤100A/µs, VDD ≤ V (BR)DSS, T j ≤ T JMAX.
1/9
STD6NC40
THERMAL DATA
Rthj-case
Thermal Resistance Junction-case Max
2.27
°C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
100
°C/W
Rthc-sink
Thermal Resistance Case-sink Typ
1.5
°C/W
Maximum Lead Temperature For Soldering Purpose
275
°C
Tl
AVALANCHE CHARACTERISTICS
Symbol
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Max Value
Unit
6
A
320
mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
V(BR)DSS
IDSS
IGSS
Parameter
Test Conditions
Min.
Typ.
Max.
400
Unit
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0
V
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
1
µA
VDS = Max Rating, TC = 125 °C
50
µA
Gate-body Leakage
Current (VDS = 0)
VGS = ±30V
±100
nA
ON (1)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 3 A
ID(on)
On State Drain Current
VDS > ID(on) x RDS(on)max,
VGS = 10V
Min.
Typ.
Max.
Unit
2
3
4
V
0.75
1
Ω
6
A
DYNAMIC
Symbol
gfs (1)
2/9
Parameter
Forward Transconductance
Test Conditions
VDS > ID(on) x RDS(on)max,
ID =3A
VDS = 25V, f = 1 MHz, VGS = 0
Min.
Typ.
Max.
Unit
5.1
S
530
pF
Ciss
Input Capacitance
Coss
Output Capacitance
90
pF
Crss
Reverse Transfer
Capacitance
15
pF
STD6NC40
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
td(on)
tr
Qg
Qgs
Qgd
Parameter
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
Min.
VDD = 200V, ID = 3A,
RG = 4.7Ω VGS = 10V
(see test circuit, Figure 3)
VDD = 320V, ID = 6A,
VGS = 10V
Typ.
Max.
Unit
11
ns
15
ns
18
4
8.5
23
nC
nC
nC
Typ.
Max.
Unit
SWITCHING OFF
Symbol
tr(Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
Min.
VDD = 320V, ID = 6A,
RG = 4.7Ω, VGS = 10V
(see test circuit, Figure 5)
8
12
23
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
ISD
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Source-drain Current
6
A
ISDM (1)
Source-drain Current (pulsed)
24
A
VSD (2)
Forward On Voltage
ISD = 6A, VGS = 0
1.6
V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 6A, di/dt = 100A/µs,
VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
trr
Qrr
IRRM
280
1.4
10
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedence
3/9
STD6NC40
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/9
STD6NC40
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/9
STD6NC40
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9
STD6NC40
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.037
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
L2
0.8
0.047
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
7/9
STD6NC40
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.20
2.40
0.087
0.094
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
C
0.45
0.60
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
0.398
L2
0.8
0.031
L4
0.60
1.00
0.024
0.039
V2
0o
8o
0o
0o
P032P_B
8/9
STD6NC40
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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