STMICROELECTRONICS STL15DN4F5

STL15DN4F5
Dual N-channel 40 V, 8 mΩ, 15 A
PowerFLAT™(5x6) double island, STripFET™ V Power MOSFET
Features
Type
VDSS
RDS(on)
max.
ID
STL15DN4F5
40 V
9 mΩ
15 A (1)
1. The value is rated according Rthj-pcb
■
RDS(on) * Qg industry benchmark
■
Extremely low on-resistance RDS(on)
■
Very low switching gate charge
■
Low gate drive power losses
PowerFLAT™ (5x6)
Double island
Application
■
Switching applications
– Automotive
Figure 1.
Internal schematic diagram
Description
The device is a dual N-channel STripFET™ V.
This Power MOSFET technology is among the
latest improvements, which have been especially
tailored to achieve very low on-state resistance
providing also one of the best-in-class figure of
merit (FOM).
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL15DN4F5
15DN4F5
PowerFLAT™(5x6)
Double island
Tape and reel
September 2010
Doc ID 17739 Rev 1
1/12
www.st.com
12
Contents
STL15DN4F5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
.............................................. 8
Doc ID 17739 Rev 1
STL15DN4F5
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
40
V
± 20
V
60
A
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID(1)
Drain current (continuous) at TC = 25 °C
ID(2)
Drain current (continuous) at TC = 25 °C
15
A
ID (2)
Drain current (continuous) at TC = 100°C
10
A
IDM
(silicon limited)
(3)
Drain current (pulsed)
60
A
PTOT
(1)
Total dissipation at TC = 25°C
60
W
PTOT
(2)
Total dissipation at TC = 25°C, t < 10 sec
4.3
W
Derating factor
0.03
W/°C
-55 to 175
°C
TJ
Operating junction temperature
Storage temperature
Tstg
1. The value is rated according Rthj-c
2. The value is rated according Rthj-pcb
3. Pulse width limited by safe operating area
Table 3.
Thermal resistance
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) (steady state)
2.5
°C/W
Thermal resistance junction-ambient
35
°C/W
Value
Unit
Not-repetitive avalanche current,
(pulse width limited by Tj max.)
7.5
A
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAV , VDD = 24 V)
150
mJ
Rthj-pcb
(1)
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec (see Figure 3)
Table 4.
Avalanche data
Symbol
IAV
EAS(1)
Parameter
1. Tested at wafer level only.
Doc ID 17739 Rev 1
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Electrical characteristics
2
STL15DN4F5
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 7.5 A
Symbol
Ciss
Coss
Crss
Qg
Qgs
Qgd
Min.
Typ.
Max.
40
Unit
V
VDS = Max rating,
IDSS
Table 6.
4/12
On/off states
1
10
µA
µA
±100
nA
4
V
8
9
mΩ
Min.
Typ.
Max.
Unit
-
1550
230
25
-
pF
pF
pF
-
25
6
5.5
-
nC
nC
nC
VDS = Max rating @125 °C
2
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
VDS = 25 V, f = 1 MHz
VGS = 0
VDD= 20 V, ID = 15 A
VGS = 10 V
(see Figure 14)
Doc ID 17739 Rev 1
STL15DN4F5
Electrical characteristics
Table 7.
Switching times
Symbol
td(on)
tr
td(off)
tf
Table 8.
Symbol
ISD
Parameter
Turn-on delay time
Test conditions
Min.
Typ.
Max.
Unit
-
18
45
32
5
-
ns
ns
ns
ns
Min
Typ.
Max
Unit
VDD = 20 V, ID = 7.5 A,
Rise time
RG = 4.7 Ω, VGS = 10 V
Turn-off delay time
(see Figure 13)
Fall time
Source drain diode
Parameter
Test conditions
Source-drain current
-
15
A
ISDM(1)
Source-drain current (pulsed)
-
60
A
VSD(2)
Forward on voltage
ISD = 15 A, VGS = 0
-
1.1
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 15 A,
di/dt = 100 A/µs,
VDD = 32 V, Tj = 150 °C
trr
Qrr
IRRM
-
30
35
2.2
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %
Doc ID 17739 Rev 1
5/12
Electrical characteristics
STL15DN4F5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM07129v1
ID
(A)
Tj=175°C
Tc=25°C
Single pulse
a is
are n)
this RDS(o
n in ax
io
t
m
era by
Op ited
Lim
100
10ms
10
100ms
1
1s
0.1
0.01
0.1
Figure 4.
10
1
VDS(V)
Output characteristics
AM07130v1
ID (A)
VGS=10V
35
6V
5V
30
30
25
25
20
20
15
15
10
10
Figure 6.
VDS=0.4V
5
5
0
0
AM07131v1
ID
(A)
35
4V
0.2
0.4
0.6
Normalized BVDSS vs temperature
BVDSS
0
0
0.8 VDS(V)
AM07132v1
(norm)
Figure 7.
2
4
8
6
VGS(V)
Static drain-source on resistance
AM07133v1
RDS(on)
(mOhm)
VGS=10V
1.15
8.6
1.10
1.05
8.2
1.00
7.8
0.95
0.90
7.4
0.85
0.80
-75 -50 -25
6/12
0 25 50 75 100 125 150 TJ(°C)
7.0
0
Doc ID 17739 Rev 1
2
4
6
8
10
12
14
ID(A)
STL15DN4F5
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM07135v1
VGS
(V)
VDD=20V
ID=15A
Capacitance variations
AM07134v1
C
(pF)
10
Ciss
8
1000
6
Coss
100
4
2
Crss
10
0
0
10
5
15
20
0.1
25 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM07136v1
VGS(th)
(norm)
1
10
VDS(V)
Figure 11. Normalized on resistance vs
temperature
RDS(on)
(norm)
AM07137v1
2.0
1.00
1.5
0.8
1.0
0.6
0.5
0.4
-75 -50 -25
0 25 50 75 100 125 150 TJ(°C)
0
-75 -50 -25
0 25 50 75 100 125 150 TJ(°C)
Figure 12. Source-drain diode forward
characteristics
AM07138v1
VSD
(V)
TJ=-55°C
0.9
0.8
TJ=25°C
0.7
0.6
TJ=175°C
0.5
0.4
0
2
4
6
8
10
12
14
ISD(A)
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Test circuits
3
STL15DN4F5
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
VDD
2200
µF
3.3
µF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/12
0
Doc ID 17739 Rev 1
10%
AM01473v1
STL15DN4F5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and products status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 17739 Rev 1
9/12
Package mechanical data
STL15DN4F5
PowerFLAT™ (5x6) double island mechanical data
mm
Dim
Min
A
0.83
0.90
0.02
0.05
A3
0.20
0.35
0.40
D
5.00
D1
4.75
D2
4.11
4.21
E
6.00
E1
5.75
0.47
4.31
E2
3.51
3.61
3.71
E3
2.32
2.42
2.52
e
1.27
L
0.70
0.80
0.90
L1
0.48
0.58
0.68
8066312_A
10/12
Max
A1
b
0.80
Typ
Doc ID 17739 Rev 1
STL15DN4F5
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
02-Sep-2010
1
Changes
First release
Doc ID 17739 Rev 1
11/12
STL15DN4F5
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