STLC3055 WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT MONOCHIP SLIC OPTIMISED FOR WLL & ISDN-TA APPLICATIONS IMPLEMENT ALL KEY FEATURES OF THE BORSHT FUNCTION SINGLE SUPPLY (5.5 TO 15.8V) BUILT IN DC/DC CONVERTER CONTROLLER. SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR THRESHOLD METERING PULSE GENERATION AND FILTER INTEGRATED RINGING INTEGRATED RING TRIP PARALLEL CONTROL INTERFACE (3.3V LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT FEED SURFACE MOUNT PACKAGE INTEGRATED THERMAL PROTECTION -40 TO +85°C OPERATING RANGE BLOCK DIAGRAM D0 D1 TQFP44 ORDERING NUMBERS: STLC3055Q STLC3055QTR DESCRIPTION The STLC3055 is a SLIC device specifically designed for WLL (Wireless Local Loop) and ISDNTerminal Adaptors. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from +5.5V to +15.8V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch. The battery level is properly adjusted depending on the operating mode. A useful characteristic for D2 DET INPUT LOGICAND DECODER OUTPUT LOGIC BGND Status and functions TIP TX RX SUPERVISION LINE OUTPUT DR IVER STAGE ZAC1 ZAC RING AC PROC RS CR EV ZB DC PROC CLK R SENSE GATE VF DC/DC CKTTX CSVR CONV. CTTX1 CTTX2 TTX PROC REFERENCE FTTX Vcc Vss Agnd CVCC VPOS VBAT VOLT. REG. Vbat RTTX October 1999 CAC ILTF RD IREF RLIM RTH AGND 1/22 STLC3055 DESCRIPTION (continued) these applications is the integrated ringing generator. The control interface is a parallel type with open drain output and 3.3V logic levels. The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid pos- sible CODEC input saturation due to Metering pulse echo. Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, developed in BCD100II technology (100V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140°C. VBAT1 CREV N.C. TIP N.C. N.C. N.C. RING N.C. VBAT BGND PIN CONNECTION 44 43 42 41 40 39 38 37 36 35 34 RD PD 30 RTH RES 5 29 IREF N.C. 6 28 RLIM N.C. 7 27 AGND DET 8 26 CVCC CKTTX 9 25 VPOS CTTX1 10 24 RSENSE CTTX2 11 23 GATE 12 13 14 15 16 17 18 19 20 21 22 VF 31 4 CLK 3 TX D2 CAC ILTF ZB 32 RS 2 ZAC D1 ZAC1 CSVR RX 33 FTTX 1 RTTX D0 D97TL279A ABSOLUTE MAXIMUM RATINGS Symbol Vpos A/BGND Vdig Tj Vbtot (1) Parameter Positive Supply Voltage Value Unit -0.4 to +17 V -1 to +1 V AGND to BGND Pin D0, D1, D2, DET, CKTTX -0.4 to 5.5 V Max. junction Temperature 150 °C Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). 100 V (1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10) 2/22 STLC3055 OPERATING RANGE Symbol Parameter Value Unit Positive Supply Voltage 5.5 to +15.8 V AGND to BGND -100 to +100 V Vdig Pin D0, D1, D2, DET, CKTTX, PD -0.25 to 5.25 V Top Ambient Operating Temperature Range -40 to +85 °C -74 max. V Value Unit 60 °C/W Vpos A/BGND Vbat (1) Self Generated Battery Voltage (1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10) THERMAL DATA Symbol Parameter R th j-amb Thermal Resistance Junction to Ambient Typ. PIN DESCRIPTION N. Name 25 VPOS Positive supply input ranging from 5.5V to 15.8V. Function 34 BGND Battery Ground, must be shorted with AGND. 27 AGND Analog Ground, must be shorted with BGND. 16 ZAC 15 ZAC1 17 RS Protection resistors image (the image resistor is connected from this node to ZAC). 18 ZB Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). 20 TX 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. 14 RX 4 wire input port (RX input); 300KΩ input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. 19 CAC AC feedback input, AC/DC split capacitor (CAC). 32 ILTF Transversal line current image output. 41 TIP 2 wire port; TIP wire (Ia is the current sourced from this pin). 37 RING 2 wire port; RING wire (Ib is the current sunk into this pin). 28 RLIM Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and PCB layout should avoid noise injection on this pin. 30 RTH Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and PCB layout should avoid noise injection on this pin. 29 IREF Internal bias current setting pin. RREF should be connected close to this pin and PCB layout should avoid noise injection on this pin. 43 CREV Reverse polarity transition time control. One proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the ”trapezoidal ringing” during ringing injection. 31 RD AC impedance synthesis. RX buffer output, the AC impedance is connected from this node to ZAC. DC feedback and ring trip input. RD should be connected close to this pin and PCB layout should avoid noise injection on this pin. 3/22 STLC3055 PIN DESCRIPTION (continued) N. Name Function 4 PD 26 CVCC Internal positive voltage supply filter. 35 VBAT Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 23 GATE 21 VF 22 CLK 24 RSENSE 1 D0 Control Interface: input bit 0. 2 D1 Control Interface: input bit 1. 3 D2 Control interface: input bit 2. 8 DET 33 CSVR Battery supply filter capacitor. 12 RTTX Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used should be left open. Power Down input. Normally connected to CVCC (or to logic level high). Can be used to set TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0. Driver for external Power MOS transistor. Feedback input for DC/DC converter controller. Power Switch Controller Clock (typ. 125KHz). From version marked STLC3055 A5, this pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS pin. The PCB layout should minimize the extra resistance introduced by the copper tracks. Logic interface output of the supervision detector (active low). 13 FTTX Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering. 10 CTTX1 Metering burst shaping external capacitor. 11 CTTX2 Metering burst shaping external capacitor. 9 CKTTX Metering pulse clock input (12 KHz or 16KHz square wave). 44 VBAT1 Frame connection. Must be shorted to VBAT. 5 RES Reserved, must be connected to AGND. 6, 7,36, 38,39, 40,42 NC Not connected. FUNCTIONAL DESCRIPTION The STLC3055 is a device specifically developed for WLL and ISDN-TA applications. It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC’s operating modes are: Power Down 4/22 High Impedance Feeding (HI-Z) Active Ringing Table 1 shows how to set the different SLIC operating modes. Table 1. SLIC operating modes. PD D0 D1 D2 Operating Mode 0 0 0 X Power Down 1 0 0 X H.I. Feeding (HI-Z) 1 0 1 0 Active Normal Polarity 1 0 1 1 Active Reverse Polarity 1 1 1 0 Active TTX injection (N.P.) 1 1 1 1 Active TTX injection (R.P.) 1 1 0 0/1 Ring (D2 bit toggles @ fring) STLC3055 The DC/DC converter controller is driving an external power MOS transistor (P-Channel) in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHZ typ.). From version marked STLC3055 A5, it can be synchronised to an internal clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). The typical value is obtained for a sensing resistor equal to 110mΩ that will guarantee an average current consumption from Vpos < 700mA. When in on-hook the self generated battery voltage is set to a predefined value. This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is selected this value is increased to -70V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjust the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising in this way the power dissipation. This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode. The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1500W+Rp) in series (see fig.1), where Rp is the external protection resistance. Figure 1. DC Characteristic in HI-Z Mode. IL Vbat 2x(R1+Rp) Slope: 2x(R1+Rp) (R1=1500ohm) VL OPERATING MODES Power Down DC CHARACTERISTIC & SUPERVISION When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3055 in case of thermal overload (Tj > 140°C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. AC CHARACTERISTICS The 2W port is set in high impedance, the TX output buffer is a low impedance output, no AC transmission is possible. High Impedance Feeding (HI-Z) DC CHARACTERISTIC & SUPERVISION Vbat (-50V) AC CHARACTERISTICS The AC impedance shown at the 2W port (TIP/RING) is the same as the DC one. The TIP/RING AC impedance will be 2x(1500Ω + Rp) or high impedance. Active DC CHARACTERISTICS & SUPERVISION When this mode is selected the STLC3055 provides both DC feeding and AC transmission. The STLC3055 feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3055 behaves like a 40V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x41Ω) plus the internal resistance. Fig. 2 shows the typical DC characteristic in ACTIVE mode. 5/22 STLC3055 Figure 2. DC characteristic in ACTIVE mode IL Ilim (20 to 40mA) 2Rp VL 10V Vbat (-50V) The line status (on/off hook) is monitored by the SLIC’s supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 70mA typ. Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by the RSENSE resistor and it is typically 900mApk. POLARITY REVERSAL The D2 bit controls the line polarity, the transition between the two polarities is performed in a ”soft” way. This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig.3). The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 3. TIP/RING typical transition from Direct to Reverse Polarity GND TIP 4V typ. 40V typ ON-HOOK dV/dT set by CREV RING AC CHARACTERISTICS The SLIC provides the standard SLIC transmission functions: Input impedance synthesis: can be real or complex and is set by a scaled (x50) external ZAC impedance. Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB gain and from the RX input to the 2W port with a 0dB gain. 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB. Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 2). Table 2. SLIC states in ACTIVE mode D0 D1 D2 0 1 0 Active Normal Polarity 0 1 1 Active Reverse Polarity 1 1 0 Active TTX injection (N.P.) 1 1 1 Active TTX injection (R.P.) 6/22 Operating Mode METERING PULSE INJECTION (TTX) The metering pulses circuit consist of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the harmonic distortion of the output signal. The metering pulse is obtained starting from two logic signals: CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases). D0: enable the TTX generation circuit and define the TTX pulse duration. This two signals are then processed by a dedicated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig.4). Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of external components. In particular the amplitude is set by the two resistors RLV and the STLC3055 Figure 4. Metering pulse generation circuit. Low Pass Filter C1 CTTX1 RLV BURST SHAPING SQTTX CS GENERATOR R1 + CFL C2 Sinusoidal wave pulse metering RLV CTTX2 Required external components vs. filter order. Order CFL D0 CKTTX RTTX R2 FTTX OP1 1 2 3 R1 C! R2 C2 X X THD 13% X X X X 6% X X X X 3% Square wave pulse metering shaping by the capacitor CS. The waveform so generated is then filtered and injected on the line. The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1 non inverting input) and RTTX (OP1 output) (see fig.4) and implementing a ”Sallen and Key” configuration. Depending on the external components count it is possible to build an optimised application depending on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig.4). The circuit showed in the ”Application diagram” is related to the simple first order filter. Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins with a +6dB gain. It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation (obtained via proper setting of RTTX and CTTX). In addition the effective level obtained on the line will depend on the line impedance, the protection resistor value and the series switch (SW1 or SW2) on resistance. In the typical application (TTX line impedance =200Ω , RP = 41Ω, SW1,2 on resistance = 9Ω and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 times the level applied to the RTTX pin. As already mentioned the metering pulse echo cancellation is obtained by means of two external components (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network has a double effect: Synthesise a low output impedance at the TIP/RING pins at the TTX frequency. Cut the eventual TTX echo that will be transferred from the line to the TX output. Ringing When this mode is selected STLC3055 self generate an higher negative battery (-70V typ.) in order to allow a balanced ringing signal of typically 65Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1=reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.5). The shaping is defined by the CREV external capacitor. Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values 7/22 STLC3055 Figure 5. TIP/RING typical ringing waveform GND TIP 2.5V typ. 65V typ. dV/dT set by CREV RING VBAT 2.5V typ. If for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be reduced. In the typical application with RSENSE = 110mΩ the peak current from Vpos is limited to about 900mA, which correspond to an average current of 700mA max. In this condition the STLC3055 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard). In order to drive up to 5REN (1REN= 6930Ω + 8µF, US standard) it is necessary to modify the external components as follows: CREV = 15nF RD = 2.2KΩ obtained with a 20Hz and 25Hz ring frequency and with 1REN. This value are valid either with European or USA specification: CREV CREST FACTOR @20Hz CREST FACTOR @25Hz 22nF 1.2 1.26 27nF 1.25 1.32 33nF 1.33 Not significant (*) (*) Distorsion already less than 10%. The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500Ω ). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055 in the proper operating mode (normally ACTIVE). RING LEVEL IN PRESENCE OF MORE TELEPHONE IN PARALLEL As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. 8/22 Power On Requirements In order to avoid damage to the device when Vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0V) until Vpos is >5.5V. In case this power up sequence cannot be guaranteed it’s recommended to connect a shottky diode (BAT46 or equivalent) between VBAT and BGND see figure below. Figure 6. Shottky diode connection BGND STLC3055 VBAT BAT46 STLC3055 Layout Recommendation A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Fig. 7). The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point PGND. This point should show a resistance as low as possible, that means it should be a ground plane. Noise sources can be identified in not enough good grounds, not enough low impedance supplies and parasitic coupling between PCB tracks and high impedance pins of the device. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3055 using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS. External Components List In order to properly define the external components value the following system parameters have to be defined: The AC input impedance shown by the SLIC at the line terminals ”Zs” to which the return loss measurement is referred. It can be real (typ. 600Ω) or complex. The AC balance impedance, it is the equivalent impedance of the line ”Zl” used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The line impedance at the TTX frequency ”Zlttx”. The metering pulse level amplitude measured at line termination ”V LOTTX”. In case of low order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or 16KHz). Pulse metering envelope rise and decay time constant ”τ”. The slope of the ringing waveform ”∆VTR/∆T ”. The value of the constant current limit current ”Ilim”. The value of the off-hook current threshold ”ITH”. The value of the ring trip rectified average threshold current ”I RTH”. The value of the required self generated negative battery ”V BATR” in ring mode (max value is 70V). This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak sunk from Vpos ”IPK”. 9/22 STLC3055 EXTERNAL COMPONENTS Name Function Formula RREF Bias setting current RREF = 1.3/Ibias Ibias = 50µA CSVR Negative Battery Filter CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ) fp = 50Hz Ring Trip threshold setting resistor RD = 100/IRTH 2KΩ < RD < 5KΩ RD CAC AC/DC split capacitance Typ. Value 26kΩ 1% 1.5nF 10% 100VL 4.12kΩ 1% @ IRTH = 24mA 22µF 20% 15VL @ RD = 4.12kΩ RP Line protection resistor Rp > 30Ω RS Protection and series switches resistance image RS = 100 ⋅ (Rp + 9Ω) Two wire AC impedance ZAC = 50 ⋅ (Zs - 2Rp - 18Ω) 25kΩ 1% @ Zs = 600Ω ZA (1) SLIC impedance balancing network ZA = 50 ⋅ Zs 30kΩ 1% @ Zs = 600Ω ZB (1) Line impedance balancing network ZB = 50 ⋅ Zl 30kΩ 1% @ Zl = 600Ω AC feedback loop compensation CCOMP = 1/(2π⋅fo⋅100⋅(RP+9Ω)) fo = 250kHz 120pF 10% 10VL @ Rp = 41Ω CH Trans-Hybrid Loss frequency compensation CH = CCOMP 120pF 10% 10VL RLIM Current limiting programming RLIM = 1300/Ilim 32.5kΩ < RLIM < 65kΩ RTH Off-hook threshold programming (ACTIVE mode) RTH = 260/ITH 27kΩ < RTH < 52kΩ Reverse polarity transition time programming CREV = (1/3750) ⋅ ∆T/∆VTR) RTTX (3) Pulse metering cancellation resistor RTTX = 50Re[(Zlttx+2Rp+18Ω)] 15kΩ @Zlttx = 200Ω real CTTX (3) Pulse metering cancellation capacitor CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]} 100nF 10% 10V (2) @ Zlttx = 200Ω real RLV Pulse metering level resistor RLV = 63.3⋅10 ⋅α⋅VLOTTX α = (|Zlttx + 2Rp + 18Ω|/|Zlttx|) CS Pulse metering shaping capacitor CS = τ/(2⋅RLV) CFL Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV) ZAC CCOMP CREV RDD Pull up resistors 41Ω 1% 3 5kΩ @ Rp = 41Ω 52.3kΩ 1% @ Ilim = 25mA 28.7kΩ 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 27kΩ 1% @ VLOTTX = 275mVrms 100nF 10% 10V @ τ = 6ms, RLV = 27.1kΩ 1nF 10% 10V @fttx = 12kHz RLV = 27kΩ 100kΩ CVCC Internally supply filter capacitor 100nF 20% 10V CVpos Positive supply filter capacitor with low impedance for switch mode power supply 100µF(4) CV Battery supply filter capacitor with low impedance for switch mode power supply 100µF 20% 100V (5) CVB 10/22 High frequency noise filter 470nF 20% 100VL STLC3055 EXTERNAL COMPONENTS (continued) Name CRD (6) Function Formula Typ. Value High frequency noise filter 100nF 10% 15VL Possible choiches: IRF9510 or IRF9520 or IRF9120 or equivalent Q1 DC/DC converter switch P ch. MOS transistor RDS(ON)≤1.2Ω,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA D1 DC/DC converter series diode Vr > 100V, tRR ≤ 50ns SMBYW01-200 or equivalent RSENSE DC/DC converter peak current limiting RSENSE = 100mV/IPK 110mΩ @IPK = 900mA L (8) DC/DC converter inductor DC Resistance ≤ 0.1Ω (9) CF1 DC/DC converter feedback loop stability RF1 Negative battery programming level RF2 Negative battery programming level L=125µH RFP1304PV (Manuf.: All Inductive) or SUMIDA CDRH125 or equivalent 220pF to 470pF (10) 250KΩ<RF1<300KΩ (7) 300kW 1% @ VBATR = -70V 9.1kΩ 1% (1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. (2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz). (3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp+18Ω). (4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (5) For low ripple application use 2x47µF in parallel. (6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows: 267kΩ 280kΩ 294kW 300kΩ VBAT(ACTIVE) -46V -48V -49V -50V VBATR(RING) -62V -65V -68V -70V VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration. (8) Core: MICROMETALS T50-26C IRON POWDER, AL-VALUE 61nH/N2 Current rating: 2A (50/60Hz) Operating Temperature -25° to +60° Centigrades Inductance: 14µH +/-15% at 1KHz, 1mA DC resistance of winding: MAX.100 mOhm Code: RFY1303 Wire: UEW2, 0,60 mm Turns: 50 Inductance (f=1KHz): >125µH (9) For high efficiency in HI-Z mode coil resistance @125kHz must be <3ohm (10) Function of this capacitor is to introduce a zero at the resonance frequency for loop stability. In case some parasitic resistance are already present in the loop (Coil, CVBAT, PCB layout), the presence of this capacitor can degrade the device noise performances; in this case CF1 should be removed being the loop stability already guaranteed by the parasitic resistance. 11/22 STLC3055 Figure 6. Application Diagram. VPOS CVPOS CVCC RS RX TX RX TX AGND BGND CVCC VPOS RSENSE RS ZAC CCOMP RSENSE GATE VBAT CVB ZA ZB CH Q1 D1 ZAC1 ZAC CF1 RF1 VF ZB CV L RF2 VDD CLK RDD CLK RP TIP TIP RP CONTROL INTERFACE DET D0 D0 D1 D1 D2 D2 TTX CLOCK RING STLC3055 DET RING CSVR CREV CREV CKTTX RTH CTTX1 RLIM CSVR RLV RLV CS IREF CTTX2 RREF FTTX CAC RTTX RLIM RTH RD ILTF CFL RTTX RD CRD D96TL275D AGND CAC CTTX BGND SUPPLY GND SUGGESTED GROUND LAY-OUT PGND Figure 7. Application Diagram without Metering Pulse Generation. VPOS CVPOS CVCC RS RX TX RX TX AGND BGND CVCC VPOS RS RSENSE ZAC CCOMP RSENSE GATE VBAT CVB ZA ZB CH Q1 D1 ZAC1 ZAC RF1 CF1 VF ZB CV RF2 VDD CLK RDD RP STLC3055 CONTROL INTERFACE DET D0 D1 D1 D2 D2 TTX CLOCK CSVR CREV RTH CTTX1 RLIM CTTX2 IREF RREF RTTX CAC ILTF BGND 12/22 PGND CAC CSVR RLIM RTH RD RD AGND SUPPLY GND RING CREV CKTTX FTTX TIP RP RING DET D0 SUGGESTED GROUND LAY-OUT CLK TIP CRD D98TL380A L STLC3055 ELECTRICAL CHARACTERISTICS Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C. External components as listed in the ”Typical Values” column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. DC CHARACTERISTICS Symbol Min. Typ. Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) T amb = 0 to 85°C 44 50 V Vlohi Line voltage Il = 0, HI-Z (High impedance feeding) T amb = -40 to 85°C 42 48 V Vloa Line voltage Il = 0, ACTIVE T amb = 0 to 85°C 33 40 V Vloa Line voltage Il = 0, ACTIVE T amb = -40 to 85°C 31 37 V Ilim Lim. current programming range ACTIVE mode 20 40 mA Ilima Lim. current accuracy ACTIVE mode. Rel. to programmed value 20mA to 40mA -10 10 mA Feeding resistance HI-Z (High Impedance feeding) 2.4 3.6 kΩ Rfeed HI Zrx Parameter Test Condition RX port input impedance Max. 280 Unit kΩ AC CHARACTERISTICS L/T Long. to transv. (see Appendix for test circuit) Rp = 41Ω, 1% tol., ACTIVE N. P., R L = 600Ω (*) f = 300 to 3400Hz 48 50 dB T/L Transv. to long. (see Appendix for test circuit) Rp = 41Ω, 1% tol., ACTIVE N. P., R L = 600Ω (*) f = 300 to 3400Hz 40 45 dB T/L Transv. to long. (see Appendix for test circuit) Rp = 41Ω, 1% tol., ACTIVE N. P., R L = 600Ω (*) f = 1kHz 48 53 dB 2W return loss 300 to 3400Hz, ACTIVE N. P., R L = 600Ω (*) 22 26 dB THL Trans-hybrid loss 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., R L = 600Ω (*) 30 dB Ovl 2W overload level at line terminals on ref. imped. ACTIVE N. P., R L = 600Ω (*) 10 dBm TXoff TX output offset ACTIVE N. P., R L = 600Ω (*) -150 150 mV G24 Transmit gain abs. 0dBm @ 1020Hz, ACTIVE N. P., R L = 600Ω (*) -6.4 -5.6 dB G42 Receive gain abs. 0dBm @ 1020Hz, ACTIVE N. P., R L = 600Ω (*) -0.4 0.4 dB G24f TX gain variation vs. freq. rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., R L = 600Ω (*) -0.12 0.12 dB 2WRL 13/22 STLC3055 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. -0.12 G42f RX gain variation vs. freq. rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., R L = 600Ω (*) V2Wp Idle channel noise at line psophometric filtered ACTIVE N. P., R L = 600Ω (*) T amb = 0 to +85°C -73 V2Wp Idle channel noise at line psophometric filtered ACTIVE N. P., R L = 600Ω (*) T amb = -40 to +85°C -68 V4Wp Idle channel noise at line psophometric filtered ACTIVE N. P., R L = 600Ω (*) T amb = 0 to +85°C -75 V4Wp Idle channel noise at line psophometric filtered ACTIVE N. P., R L = 600Ω (*) T amb = -40 to +85°C -75 Thd Total Harmonic Distortion ACTIVE N. P., R L = 600Ω (*) Metering pulse level on line ACTIVE - TTX Zl = 200Ω fttx = 12kHz VTTX CLKfreq CLK operating range Max. Unit 0.12 dB -68 dBmp dBmp -70 dBmp -46 200 250 -10% 125 dBmp dB mVrms 10% kHz (*) RL: Line Resistance RING Vring Line voltage RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF T amb = 0 to +85°C 45 49 Vrms Vring Line voltage RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800Ω + 1.0µF T amb = -40 to +85°C 44 48 Vrms 10.5 DETECTORS IOFFTHA Off/hook current threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) ROFTHA Off/hook loop resistance threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 3.4 kΩ IONTHA On/hook current threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 6 mA RONTHA On/hook loop resistance threshold ACT. mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 8 kΩ IOFFTH I Off/hook current threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 10.5 mA ROFFTHI Off/hook loop resistance threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 800 Ω IONTHI On/hook current threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 6 mA RONTHI On/hook loop resistance threshold Hi Z mode, RTH = 28.7kΩ 1% (Prog. ITH = 9mA) 14/22 8 mA kΩ STLC3055 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit Irt Ring Trip detector threshold range RING 20 50 mA Irta Ring Trip detector threshold accuracy RING -15 15 % Trtd Ring trip detection time RING Td Dialling distortion ACTIVE Rlrt (1) Loop resistance ThAl TBD -1 ms 1 500 Tj for th. alarm activation ms Ω °C 160 (1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection. DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET Vih In put high voltage Vil Input low voltage 2 V 0.8 V Iih Input high current -10 10 µA Iil Input low current -10 10 µA 0.45 V Vol Output low voltage Iol = 1mA PSRR AND POWER CONSUMPTION PSERRC Ivpos Ipk Power supply rejection Vpos to 2W port Vripple = 100mVrms 50 to 4000Hz Vpos supply current @ ii = 0 HI-Z On-Hook ACTIVE On-Hook, RING (line open) Peak current limiting accuracy RING Off-Hook RSENSE = 110mΩ 26 -20% 36 dB 52 93 120 60 115 140 mA mA mA 950 +20% mApk 15/22 STLC3055 APPENDIX A STLC3055 Test Circuits Referring to the application diagram shown in fig. 7 of the STLC3055 datasheet and using as external components the Typ. Values specified in the ”External Components” Table (page 13) find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using ”Wandel & Goltermann DC Loop Holding Circuit GH-1” or equivalent. Figure A1. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs) W&G GH1 Zref TX TIP 600ohm 100µF Vs 1Kohm STLC3055 application circuit 100mA DC max E Zin = 100K 200 to 6kHz 100µF 1Kohm RX RING Figure A2. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx| W&G GH1 TIP TX 100µF 600ohm Vtx STLC3055 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100µF RING RX Vrx 16/22 STLC3055 Figure A3. G24 Transmit Gain G24 = 20Log|2Vtx/E| W&G GH1 TIP TX 100µF Vtx STLC3055 application circuit 100mA DC max 600ohm Zin = 100K 200 to 6kHz E 100µF RX RING Figure A4. G42 Receive Gain G42 = 20Log|VI/Vrx| W&G GH1 TIP TX 10 0µF Vl 600ohm STLC3055 application circuit 100mA DC max Zin = 100K 200 to 6kHz 10 0µF RX RING Vrx Figure A5. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl| W&G GH1 TIP TX 100µF Vl 600ohm STLC3055 application circuit 100mA DC max Zin = 100K 200 to 6kHz 100µF RING RX VPOS ~ Vn 17/22 STLC3055 Figure A6. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl| W&G GH1 300ohm 100µF TIP TX 100µF 100mA DC max Impedance matching better than 0.1% STLC3055 application circuit Vl Zin = 100K 200 to 6kHz Vcm 100µF RX RING 300ohm 100µF Figure A7. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm| 300ohm 100µF W&G GH1 TIP TX 100µF STLC3055 application circuit 100mA DC max Impedancematching better than 0.1% 600ohm Vcm Zin = 100K 200 to 6kHz 100µF RING 300ohm 100µF Figure A8. VTTX Metering Pulse level on line TIP Vlttx 200ohm TX STLC3055 application circuit RX RING CKTTX fttx (12 or 16kHz) 18/22 RX Vrx STLC3055 Figure A9. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|;V4Wp = 20Log|Vtx/0.774l| W&G GH1 TIP TX 100µF 100mA DC max 600ohm Zin = 100K 200 to 6kHz Vl psophometric filtered Vtx psophometric filtered STLC3055 application circuit 100µF RX RING APPENDIX B STLC3055 Overvoltage Protection Figure B1. Simplified configuration for indoor overvoltage protection BGND 2x SM4T39RX STLC3055 TIP RING RP1 RP2 TIP RP1 RP2 RING VBAT RP2: Fuse or PTC Figure B2. Standard overvoltage protection configuration for K20 compliance BGND 2x SM4T39RX STLC3055 TIP RP1 RP2 TIP RP2 RING LCP1511 RING RP1 VBAT RP2: Fuse or PTC 19/22 STLC3055 APPENDIX C TYPICAL STATE DIAGRAM FOR STLC3055 OPERATION Figure C1. Normally used for On Hook Transmission Tj>Tth PD=0, D0=D1=0 Power Down Active On Hook Ring Pause D0=0, D1=1, D2=0 Ring Burst Ring Burst D0=1, D1=0, D2=0/1 Ringing PD=1, D0=D1=0 On Hook Detection for T>Tref HI-Z Feeding Ring Trip Detection Active Off Hook On Hook Condition Off Hook Detection D0=0, D1=1, D2=0 Note: all state transitions are under the microprocessor control. 20/22 Off Hook Detection STLC3055 21/22 STLC3055 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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