STMICROELECTRONICS STLC30R81

STLC30R81
INTEGRATED RINGING SLIC
FOR SHORT LOOP APPLICATIONS
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MONOCHIP SLIC SUITABLE FOR SHORT
LOOP APPLICATIONS
3.3V SUPPLY
IMPLEMENTS ALL KEY FEATURES OF THE
BORSHT FUNCTION
DIFFERENTIAL OR SINGLE-ENDED Rx
INPUTS
INTEGRATED TRAPEZOIDAL WAVEFORM
RINGING plus SINUSOIDAL and PWM
WAVEFORM RINGING CAPABILITY
TWO SELECTABLE PATH FOR SINUSOIDAL
RING INJECTION
SOFT BATTERY REVERSAL WITH
PROGRAMMABLE TRANSITION TIME
ON HOOK TRANSMISSION
LOW POWER DISSIPATION IN ALL
OPERATING MODES
AUTOMATIC DUAL BATTERY OPERATION
LOOP START, GROUND START FEATURES
SURFACE MOUNT PACKAGE
-40 TO +85°C OPERATING RANGE
TEST FUNCTION
NO EXTERNAL COMPONENTS FOR POWER
DISSIPATION
TQFP44 (10 x 10) with slug
ORDERING NUMBER: STLC30R81
functions (phone detection, loop-back, short circuit
detection) are integrated in this device. It provides
three ringing modes: Sinusoidal, Trapezoidal and
PWM waveform.
In sinusoidal ringing modes, depending on the CODEC’s functionalities and characteristics Rxin+/Rxinor Rg+/Rg- paths can be selected. When CODEC
can manage low frequency signals Rxin+/ Rxin- will
be used.
This device can also limit the peak current during OnHook/Off-Hook transition and Ring-trip detection.
The device is based on BCD3S 90V technology and
it can work at 3.3V power supply.
The TQFP44 Package with SLUG increases the
SLIC performance in terms of power dissipation making unnecessary the use of any external power components.
DESCRIPTION
The STLC30R81 is a low voltage SLIC suitable for
short loop applications. All the BORSHT and test
BLOCK DIAGRAM
DET
GDK/AL
CRT
LINE STATUS
D0
ILT
D1
LOGIC
INTERFACE
&
DECODER
D2
D3
TIP
SUPERVISION
LINE
INTERFACE
ILL
RING
COMMANDS
RLPBK
CS
RES
AC+
DC
RG+
AC
RGRXin+
BGND
+
ILTF
DC
RXinZB
REFERENCE
&
BIAS SWITCHING
AC
PROCESSOR
TX
ZAC1
ZAC
RS
CAC
IREF
VCC
VDD
AGND
RLIM
DC
PROCESSOR
CREV
CSVR
RTH
RD
D01TL518
Rev. 2
January 2006
1/17
STLC30R81
N.C.
CSVR
N.C.
BGND
RING
RLPBK
N.C.
TIP
N.C.
DET
GDK/AL
PIN CONNECTION (Top view)
44 43 42 41 40 39 38 37 36 35 34
N.C.
1
33
IREF
CS
2
32
RLIM
D0
3
31
RTH
D1
4
30
N.C.
D2
5
29
AGND
D3
6
28
ILTF
RES
7
27
RD
N.C.
8
26
CAC
VDD
9
25
RG-
VCC
10
24
RG+
CRT
11
23
RXin-
RXin+
ZAC1
ZAC
RS
ZB
TX
VBAT2
N.C.
VBAT1
N.C.
CREV
12 13 14 15 16 17 18 19 20 21 22
D01TL512
PIN DESCRIPTION
N°
Pin
1
N.C.
Type
Function
2
CSI
In
Chip-Select for input control bits; active low.
3
D0
In
Control Interface input bit 0. *
4
DI
In
Control Interface input bit 1. *
5
D2
In
Control Interface input bit 2. *
6
D3
In
Control Interface input bit 3. *
7
RES
In
Reset pin active low
8
N.C.
No Connection
No Connection
9
VDD
In
Control Interface Power Supply
10
VCC
In
Positive Power Supply.
11
CRT
In
GNDK detection capacitor
12
CREV
In
13
N.C.
14
VBAT1
15
N.C.
16
VBAT2
In
17
TX
Out
18
ZB
In
Reverse polarity transition time programming capacitor
No Connection
In
Negative Battery Supply 1 (-38V Typ)
No Connection
Negative Battery Supply 2 (-74V Typ)
4 wires output stage (transmitting port)
Canceling input of balance network for 2 to 4 wires conversion.
19
RS
In
Protection resistors image. It is connected between this node and ZAC
20
ZAC
In
AC impedance synthesis
21
ZAC1
In
RX buffer output / AC impedance is connected between this node and ZAC
22
Rxin+
In
4 wires input stage (receiving port). A 100K external resistor must be connected to
AGND to bias the input stage
23
Rxin-
In
4 wires input stage (receiving port). A 100K external resistor must be connected to
AGND to bias the input stage. If not used must be tied to ground.
2/17
STLC30R81
PIN DESCRIPTION (continued)
N°
Pin
Type
24
RG+
In
Sinusoidal ring signals input stage. A 100K external resistor must be connected to
AGND to bias the input stage
Function
25
RG-
In
Sinusoidal ring signals input stage. A 100K external resistor must be connected to
AGND to bias the input stage. If not used must be tied to ground.
26
CAC
In
AC feed back input / AC-DC split capacitor is connected between this node and ILTF
27
RD
In
Ring trip threshold setting resistor
28
ILTF
In
Transversal Line Current Image
29
AGND
In
Analog Ground
30
N.C.
31
RTH
In
Off-Hook threshold programming pin
No Connection
32
RLIM
In
Limiting current programming pin
33
IREF
In
34
N.C.
35
CSVR
36
N.C.
37
BGND
In
38
RING
Out
39
RLPBK
In
40
N.C.
41
TIP
Voltage reference output to generate internal reference current
No Connection.
In
Battery supply filter capacitor.
No Connection
Battery Ground
B wire termination output. IB is the current sunk into this pin.
External loop back resistor connects with this pin and tip
No Connection.
Out
A wire termination output. IA is the current sourced from this pin.
42
N.C.
43
DET
Out
Off-Hook and Ring-Trip detection bit active low
No Connection.
44
GDK/AL
Out
Ground-key detection bit active low
* Input pins provided with 15µA sink to AGND pull-down
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VBAT
Battery voltage
-82 +VCC
V
VCC
Positive supply voltage
-0.4 to +7
V
VDD
Control interface Supply Voltage
-0.4 to +7
V
-2 to +2
V
A/R/BGND
Parameter
AGND respect BGND
Note: 1. In case of power up, power failure or hot insertion with VBAT1, VCC present and VBAT2 floating the Absolute Maximum Rating can
be exceeded. This effect can be prevented ensuring that VBAT2 is always present before VBAT1and VCC or connecting one schottky
diode (e.g. BAT49X or equivalent between .VBAT1and VBAT2).
OPERATING RANGE
Symbol
Value
Unit
Topt
Operating temperature range
Parameter
-40 to 85
°C
VCC
Positive supply voltage
3.3 to 3.6
V
VDD
Control interface Supply Voltage
3 to 5.5
V
-40 to –22
V
Battery voltage
-74 to –65
V
AGND respect BGND
-0.3 to +0.3
V
VBAT1
Battery voltage
VBAT2
A/BGND
3/17
STLC30R81
THERMAL DATA
Symbol
Value
Unit
Rth j-amb
Thermal resistance Junction to Ambient (2 layer board) Typ.
Parameter
32
°C/W
Rth j-amb
Thermal resistance Junction to Ambient (1 layer board) Typ.
56
°C/W
OPERATING MODES
It is possible to choose several operating modes just setting the proper Input D0, D1, D2, and D3. The table
below (Tab.1) shows these modes:
Table 1. Ctrl Interface
Inputs
Operating Mode
Output
D0
D1
D2
D3
DET
GDK/AL
0
0
0
0
Power down
Disable
Disable
0
0
0
1
Power down
Disable
Disable
1
1
0
1
Power down
Disable
Disable
0
0
1
0
Stand-by
Off-Hook
Gnd-Key
0
1
0
0
Active normal polarity
Off-Hook
Gnd-Key
0
1
1
0
Active reverse polarity
Off-Hook
Gnd-Key
1
0
0
0
Trapezoidal ringing normal polarity
Ringing trip
Gnd-Key
1
0
1
0
Trapezoidal ringing reverse polarity
Ringing trip
Gnd-Key
1
1
0
0
Ground start
Off-Hook
Gnd-Key
1
1
1
0
High impedance feeding
Off-Hook
Disable
0
1
0
1
Active normal polarity (On-Hook transmission)
Off-Hook
Gnd-Key
0
1
1
1
Active reverse polarity (On-Hook transmission)
Off-Hook
Gnd-Key
1
0
0
1
Ringing In Sinusoidal (or PWM) wave Rxin+/- In
Ringing trip
Gnd-Key
1
0
1
1
Ringing In Sinusoidal (or PWM) wave Rg+/- In
Ringing trip
Gnd-Key
Phone detect
Disable
Off-Hook
Disable
Phone short
Disable
0110⇒1110
Test mode: phone detection
0
0
1
1
Test mode: loop back
1
1
1
1
Test mode: short circuit detection
Power Down
It's an idle state characterized by very low power consumption; any functionality is disabled. It can be set during
out of service periods just to reduce the power consumption.
It is worth remarking that two other conditions can set the SLIC in IDLE state but with some differences as reported in the table below.
Table 2. Power down
IDLE STATE
DET
GDK/AL
Power down command
Disable
Disable
Reset
Disable
Disable
Thermal alarm
Low
Low
Stand By
Mode selected in On-Hook condition when high immunity to the common mode currents is needed to prevent
false Off-Hook detection. To reduce the current consumption, AC feedback loop is disabled. Only DET and
4/17
STLC30R81
GDK/AL detectors are active. DC line loop current is limited at 15mA (not programmable). DC characteristic is
shown in Fig.1. The line feeding voltage in On-Hook is typically 42V @ VBAT2 = -74V.
Figure 1. Characteristic in StBy Mode
I
15mA
RFEED = 2RP
D03TL590
42V
V
Active - NP (normal polarity) or RP (reverse polarity)
Mode selected to allow voice signal transmission. When in ACTIVE mode VBAT1 is selected automatically and
the voltage drop in on-hook condition is 7.8V. Concerning AC characteristic the STLC30R81 allows to set 2Wire
termination impedance by means of external scaled impedance.
In ACTIVE mode the SLIC can perform battery reversal in a soft way, with programmable transition time, without
affecting the AC signal transmission. It is possible to program, by means of an external resistor RLIM, the value
of the current limitation in a range of 20 to 45mA. During On/Off-Hook transition, the SLIC line drivers limit the
transient current at Ilim +13mA.
Figure 2. DC Characteristic in Active mode
IL
20mA ~ 45mA
RFEED = 2RP
D03TL591
VBAT1 -7.8V
VL
Active - ON-Hook transmission
This mode is selected to allow caller ID transmission in On-Hook line condition. The line feeding voltage in OnHook transmission is 42V @ VBAT2 = -74V.
High Impedance feeding
As in Stand-By, this mode is set in On-Hook condition, with further reduced power consumption. Higher power
efficiency turns back to a lower immunity of the Off-Hook detector to line common mode currents. The DC feeding shows a constant current characteristic (Ilim = 18mA) followed by a resistive range with an equivalent series
resistance Rfeed = 1600Ω+ 2Rp (Fig.3). The line feeding voltage in On-Hook is 50V @ VBAT2 = -74
Thermal protection circuit is still active, preventing the junction temperature, in case of fault condition, to exceed
150°C. In High Impedance Feeding most of the circuit is switched off, only the circuit, dedicated to Off-Hook
detection, is powered. This allows reducing the total power consumption in On-hook to 30mW (typical).
5/17
STLC30R81
Figure 3. DC Characteristic in Hi-Z Feeding
I
18mA
RFEED = 1600Ω+2RP
D03TL592
50V
V
RINGING
The STLC30R81 can provide three kind of signal waveform modes: Sinusoidal, trapezoidal, PWM. When this
mode is selected, the SLIC is switched to VBAT2 (-74V); both DC/AC feedback loop are disabled and the SLIC
line drivers operate as voltage buffers.
Trapezoidal Ringing Waveform
The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in facts, controls
the line polarity: 0 = direct, 1 = reverse. The transition between the two polarities is performed in a "soft" way.
This means that TIP and RING wire exchange their polarities following a ramp transition (see Fig.4).
The CREV is capacitor sets the shape of the ringing trapezoidal waveform. Once ring trip is detected, the DET
output is set low and remains latched keeping the STLC30R81 in Stand-by mode until the operative mode is
modified by any Input Word.
Figure 4. Typical Ringing Waveform
GND
3V typ
TYP
dV/dT
set by CREV
RING
3V typ
VBAT2
D03TL593
CREV
Crest Factor @ 20Hz
Crest Factor @ 25Hz
22nF
1.2
1.26
27nF
1.25
1.32
33nF
1.33
Not significant (*)
* Distortion already less than 10%
Sinusoidal Ringing Waveform
The STLC30R81 has two couple of inputs: Rxin+/Rxin- and Rg+/Rg-; this means that it is possible to select two
different paths to generate the sinusoidal waveform ringing.
6/17
STLC30R81
– Selecting Rxin+/Rxin- (first path), the sinusoidal waveform can be applied in differential mode (using
both inputs) or single ended mode (connecting one of the two input pins directly to the GND). This signal
comes from STLC5048 or other Codec
– Selecting Rg+/Rg- (second path), the sinusoidal (or PWM) waveform ringing, can be applied in differential mode (using both inputs) or single ended mode (connecting one of the two input pins directly to
the GND). The ring source (codec, waveform generators) can be always active and shared by multiple
lines.
Both DC/AC feedback loops are disabled except for the first path (Rxin+/Rxin-) that remains enabled. This functionality will be managed through an "Input Word" that allows the ringing signal, to flow through the line. The
Table 3 shows how to select the proper input word.
Table 3. Control Word
Control Word
Input Selected Mode
D0
D1
D2
D3
1
0
0
1
Rxin+/ Rxin- Input selected
1
0
1
1
Rg+/Rg- Input selected
Figure 5. Ringing internal block
D0 D1 D2 D3
Logic interface
Ring Trip
Ring
Det
Rxin+
Rxin-
DET
OpAmp 1
Internal switch
Ring
Gain
+
-
Rg+
Rg-
OpAmp 2
In On-Hook condition, Tip and Ring are biased at -VBAT2/2; the input signal is typically amplified at 35dB.
Ring trip detection is performed sensing the variation of the AC line impedance from High (On-Hook) to Low
(Off-Hook). This particular ring trip method, allows to operate without DC offset superimposed on the ring signal
and therefore, obtain the maximum possible load driving capability, from a given negative battery. After Ring/
Trip detection, DET pin is set Low and remains latched keeping the STLC30R81 in Stand-by mode until the operative mode is modified by Input Word.
PWM Ringing Waveform
A pulse-width modulated (PWM) signal may be used to provide the ringing input to Rg inputs. The signal is applied through a low-pass filter and AC-coupled into Rg+. This approach gives a sine wave output at tip and ringing circuit.
7/17
STLC30R81
Figure 6. PWM signal Input vs Sinusoidal Output
Rxin+
Rxin-
OpAmp 1
CODEC
Rg+
IN
PWM Ring
LPF
Rg-
OpAmp 2
GROUND START
This mode is selected when the SLIC is adopted in a system using the Ground Start feature.
In this mode, the TIP termination is set in High Impedance ( 100KΩ ) while the RING one is active and fixed at
-33V @ Vbat1 (= -38V). In case RING termination is connected to GND the sinked current is limited to 35mA.
When RING is connected to GND both Off-Hook and Ground-Key detectors are set low.
TEST MODES
This device can provide three kind of tests:
1. Phone Detection
2. Short circuit
3. Loop back
Phone Detection
This test feature checks whether a phone is connected to the line.
Starting from Active Reverse Polarity status, just changing the D0 input bit, it is possible to perform the Phone
Detection function.
The MCU measures the time span of DET. Time longer then 4ms indicates that a phone is hooked up with the
line, if no phone is connected, the time span is less than 2ms.
Table 4. Phone detection - D0 variation
Control Word
Operating Mode
D0
D1
D2
D3
0
1
1
0
Active - Reverse Polarity
1
1
1
0
High Impedance Feeding - Normal Polarity
8/17
STLC30R81
Figure 7. Phone detection Diagram
Active R.P.
HiZ
Phone
DET
T>4ms
No Phone
DET
T<2ms
Short Circuit
DET signal pin changes its logical level depending on the presence (or not) of short circuit at the output of the
Line Card (See Tab.5).
Table 5. Short Circuit Detection
Control Word
DET
D0
D1
D2
D3
Short Circuit
No Short Circuit
1
1
1
1
0
1
Loop back
The test is aimed at cheking detection and feeding circuitry functionalities as described in fig. 8. The external
resistor RLPCK is closed internally between TIP and RING and emulates the phone resistance. Starting from
ACTIVE mode, when loop back mode is selected DET pin will change its level.
If DET pin is low it means that detection and feeding circuits work properly. If DET remains high it means that a
failure has been detected.
Table 6. Loop Back Detection
Control Word
DET
D0
D1
D2
D3
Good
Fail
0
0
1
1
0
1
Figure 8. loop back detection diagram
Active
Loop Back
Active
DET
Protection Mode
Suggested protection circuit is based on programmable LCP1521S Trisil and the surge current is limited by the
resistors RPT2 and RPR2, which are PTC types, protecting the device against both lightning and power-cross.
Thermal overload: the integrated thermal protection is activated when Tj reaches 150°C typ.; the Slic is forced
in Power-down mode, DET and AL are set Low.
For external applications, two diodes 1N4148 are suggested (Pls. see application diagram).
9/17
STLC30R81
Figure 9. Logic interface Input Timing
t1
t3
t2
Min
t1
100ns
t2
100ns
t3
500ns
t4
100ns
t5
100ns
t6
500ns
CS
D0/D1/D2/D3
DET/GDK
t4
t6
t5
EXTERNAL COMPONENTS
Table 7. External Components
Name
RREF
CSVR
Function
Internal current programming resistor
Battery ripple rejection capacitance
Formula
IREF = 0.6/RREF
CSVR = 1/(2π ⋅ /P⋅ 1.3MΩ)
Typ. Value
30.1KΩ±1%
100nF ±10% 100V @ 1.22Hz
CVCC
Power supply filter
100nF±20%
CVB1
CVB2
Battery supply filter
Battery supply filter
100nF±20% 100V
100nF±20% 100V
RD
CRT
Ring Trip threshold setting resistor
Ground Key capacitance
RD=100/IRT(*); 2KΩ<RD<5KΩ
CRT = (25/Fring) ⋅ 470nF
4.12KΩ±1% @IRTH =24mA
470nF±20% 6V @25Hz
CAC
AC/DC splitter Capacitance
CAC = 1/(2π⋅ /sp/RD)
10µF ±20% 15V @/sp = 10Hz
RS
ZAC
Protection resistor image
2 Wire AC impedance
Rs = 25*2RP
ZAC = 25[ZS-2RP]
2.5KΩ±1%
12.5KΩ±1%
ZA
SLIC impedance balancing network
ZA= 25 · ZS
15KΩ±1%
ZB
CCOMP
Line impedance balancing network
AC feedback compensation Capacitance
ZB = 25 · ZL
CCOMP = 2 / (2π ⋅ /o⋅ 100·RP] )
15KΩ±1%
220pF ±20% @ /o = 250KHz
RPT1
RPT2
RPR1
RPR2
RLIM
Line series Resistor
Line series Resistor
Line series Resistor
Line series Resistor
Current limiting setting resistor
≥30
≥15Ω
≥30
≥15Ω
30Ω - 1/4W±1%
20Ω
30Ω - 1/4W±1%
20Ω
26KΩ±1%
RTH*
OFF/HOOK detection threshold setting
resistor
CREV
Polarity/reversal/transition time
programming
Trans-Hybrid Freq. Comp Cap
CH
LCP15xx
RLPCK
D1
D2
D3
DS1 (**)
RLIM = 103·(0.6)/ILIM
RTH = 200·[(0.6)/ITH]
23.7KΩ to 86.6KΩ
CREV = K/(∆VTR/∆T); K= 1/3750
47nF for 5.67V/ms
CH=Ccomp
220pF ±20%
Loop Back resistor
500Ω 1.5W ±20%
Over voltage protection
Over voltage protection
Over voltage protection
Power Up sequencer
1N4148
1N4148
1N4148
BAT 49X
(*) IRT≤ILIM+10mA. The line drivers have output current limitation correspond to ILIM during the Ringing mode.
(**) Alternative to a controlled power up sequence
10/17
26.1KΩ±1%
CAP
CI
CO
CCLK
CS
INT
M1
M0
TSX
MCLK
FS
DRB
DXB
DRA
DXA
SUB
VSS
VDD
40
6
5
7
4
3
54
27
12
13
14
16
15
10
11
41
8
9
GND
49
34
ILIM
STLC5048
VBG
VEE
47
VCC
ITH
(*) ALTERNATIVE TO A CONTROLLED POWER UP SEQUENCE
CAP
0.1µF
SERIAL
CONTROL
PORTS
VCC
PCM
INTERFACE
0.1µF
VDD
46
48
43
42
38
39
52
53
29
28
24
23
22
21
20
19
35
33
VFXI3
VFRO3
VFXI2
VFRO2
VFXI1
VFRO1
CS3
CS2
CS1
CS0
CRT
7
2
6
5
4
3
44
43
17
23
22
19
18
20
21
VDD
11
9
10
RTH
RTH
VCC
37
BGND
GTX=-12dB
GRX=+6dB
0.1µF
0.1µF
31
RLIM
RLIM
32
REF
IREF
STLC30R81
VDD(3.3V) VCC(3.3V)
CRT
RES
CS
D3
D2
IO5
IO4
D0
D1
IO3
IO2
DET
GDK/AL
TX
RXin-
RXin+
RS
ZB
IO1
TO
OTHER
SLICs
100K
TO OTHER SLICs
CTX 100nF
CRX
RS
ZAC
ZAC1
IO0
VFXI0
VFRO0
IO11
IO10
58
57
IO9
IO8
IO7
59
60
61
VCC
VCC(3.3V)
0.1µF
12
AGND
CREV
CREV
35
16
14
24
25
38
41
39
26
28
27
TO OTHER
SLICs
33
29
CSRV
VBAT2
VBAT1
RPR1
RPT1
CSRV
RG+
D2
RPR2
RPT2
D1
D3
D01TL516A
DS1
(*)
LCP
1521S
RLPBK
CAC
RD
RG-
VBAT2
RING
TIP
RLPBK
CAC
ILTF
RD
VB2 (-74V)
VB1 (-38V)
RING
TIP
STLC30R81
STLC5048 plus STLC30R81: Application Diagram
Figure 10. STLC5048 / STLC30R81 Application Diagram. (Single Ended Configuration)
11/17
STLC30R81
STLC30R81 plus external generic CODEC or Ringing Waveform Generator
Figure 11. STLC30R81 plus Generic Ringing Source - Application Diagram
VDD(3.3V) VCC(3.3V)
0.1µF
0.1µF
VDD
ZAC1
CH
ZA
21
VCC
9
AGND
BGND
10
RD
29
37
27
RD
ZAC
ZB
ZAC
ZB
CCOM
RS
RS
CRX+
ILTF
18
28
GRX=+6dB
20
CAC
CAC
26
GTX=-12dB
19
RLPBK
39
22
RXin+
RLPBK
23
CRX-
100K
RXin100K
TX
CTX 100nF
DET
GDK/AL
D0
CONTROL
WORD
D1
D2
D3
TO OTHER SLICs
CS
RES
41
RPT1
TIP
TIP
VBAT2
17
STLC30R81
38
43
25
44
24
5
14
2
7
16
11
CRT
CRT
32
31
33
RTH
RLIM
IREF
RTH
RLIM
REF
12
35
RING
RPR1
Rg-
RPR2
from external
CODEC or
Ringing Waveform
Generator
Rg+
(*)
6
LCP
1521S
RING
3
4
RPT2
100K
D2
100K
D3
VBAT1
DS1
(**)
VBAT2
D1
CSRV
CREV
CREV
CSRV
D01TL515A
(*) Single ended mode: Rg-pin connected to GND. Differential mode
(**) ALTERNATIVE TO A CONTROLLED POWER UP SEQUENCE
ELECTRICAL CHARACTERISTICS
The limits listed below are guaranteed with the specified test condition and in the 0 to 70°C temperature range.
Performance over -40 to +85°C range are guaranteed by product characterization.
(Test condition, unless otherwise specified: VCC and VDD = 3.3V, VBAT1=-38V, VBAT2=-74V, Tamb=25°C)
AC CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
40
Ω
Zil
Long Impedance
Each Wire
Iil
Long Current Capability AC
H.I feeding / wire (On-Hook)
5
mApk
Standby
13
mApk
Ilim+
13-IT
mApk
Active per wire Ilim=current
limited in active mode (see also
Rlim) IT = transversal current(*)
L/T
Long. To Transv.
T/L
Transv. To Long.
2wRL
12/17
2W return loss
With normal Rp value
@ f = 1KHz
60
dB
40
dB
300 to 3400Hz
22
dB
STLC30R81
AC CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
THL
Trans-hybrid loss
1020Hz; 20Log |VRX/VTX |
30
dB
OVI
2W overload level
Active Mode at line terminals on
Ref. impedance
3.2
dBm
G24
Transmit gain abs
0dBm 1020Hz
-11.95
-12.11
-12.25
G42
Receive gains abs.
0dBm 1020Hz
5.75
5.90
6.05
dB
G24fq
Tx gain variation vs frequency
-0.1
0.1
dB
G42fq
Rx gain variation vs frequency
Rel. 1020Hz, 0dBm 300 to
3400Hz
0.1
dB
V2wp
Idle channel noise at line
terminals
Psophometric, Active on-Hook
-82
-78
dBmp
V4wp
Idle channel noise at TX port
Psophometric, Active On Hook
-90
-84
dBmp
Total harm. Dist. 2w-4w, 4w-2w
0dBm, 1KHz, I1 = 20 to 45mA
-50
dB
Thd
-0.1
dB
DC CHARACTERISTICS
Symbol
Parameter
Test Condition
Il = 0, H.I. feeding
Min.
Typ.
Max.
Unit
48
50.1
52
V
Vloih
Line voltage
Vlo
Line voltage
Il = 0, Stby
40
42
44
V
Vlo
Line voltage
Active On-Hook TX
28
29.5
31
V
Ilims
Short circuit current
Rloop = 0, STby
15
18
mA
Ilimb
Short circuit current
Rloop = 0, H.I.feeding
18
22
mA
Ilima
Lim. current accuracy
Rel to progr. Val. 20 to 45mA
Active NP, RP
10
%
VIREF
Band GAP reference
V
Rfeed H.I.
Feeding resistance
H.I. feeding
ITIP
Tip leakage current
Ground Start
IGS
Ring lead current
Ground Start Ring to GND
TXoff
TX output offset
Active Mode
-10
0.56
0.60
0.64
1100
1600
2100
Ω
100
µA
25
35
-200
45
mA
200
mV
DETECTORS
Symbol
Idet
Parameter
Off-Hook current threshold Stby,
Active
Max.
Unit
Rel. to progr. Val. 6 to 11mA
Active, NP, RP
Test Condition
Min.
-10
Typ.
+10
%
Rel. to progr. val. 3 to 6mA
-10
+20
%
Off-Hook current thershold
H.I. feeding
5
8
mA
Hys
Off/On Hook Hyst.
Stby Active
10%
30%
mΑ
Td
Dialling distortion
Active
+1
ms
ILL
Ground Key current
TIP and RING to GND or Ring to
GND
Igst
Ground Start detection threshold
ILL=IB-IA
Igst = 2 x Idet
IRTA
Rintrip detection threshold
Accuracy
Idet H.I.
20%
Idet
-1
-9.4
mA
-5
+5
%
-15
+15
%
13/17
STLC30R81
DIGITAL INTERFACE
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Inputs: D0, D1, D2, D3, CSIN
Vih
Input high voltage
VDD = 3.3V
Vil
Input low voltage
VDD = 3.3V
Iih
Iil
2
V
0.8
V
Input High current
30
µA
Input low current
10
µA
Outputs: DET, GDK/AL
Voh
Input high voltage
Iol = 0.1mA; CS = low
Vol
Input low voltage
VDD = 3.3V
2
V
0.5
V
Max.
Unit
Note: All digital inputs are TTL compatible
POWER SUPPLY REJECTION
Symbol
Parameter
Test Condition
Min.
Typ.
PSRRC
VCC to 2W port
Vripple = 0.1 Vrms 50 to 4KHz
27
dB
PSRRB
VBAT to 2W port
Vripple = 0.1 Vrms 50 to 4KHz
30
dB
POWER CONSUMPTION
Symbol
ICC
IBAT1
IBAT2
IDD
Parameter
VCC
VBAT1 supply current
VBAT2 supply current
VDD supply current
Max.
Unit
H.I. feeding On-Hook
(Open Line)
Test Condition
Min.
Typ.
1.0
mA
Stby On-Hook
3.5
mA
Active On-Hook
6.0
mA
Power Down
1.0
mA
On-Hook Tx
6.0
mA
H.I. feeding On-Hook
(Open Line)
100
µA
Stby On-Hook
200
µA
Active On-Hook
5.0
mA
Power Down
100
µA
On-Hook Tx
3.0
µA
H.I. feeding On-Hook
(Open Line)
0.5
mA
Stby On-Hook
2.5
mA
Active On-Hook
0.5
mA
Power Down
0.5
µA
Any operating mode
300
µA
Max.
Unit
+3
V
35
37
dB
3
5
%
SINUSOIDAL RING
Symbol
Parameter
Line Offset
14/17
Test Condition
Min.
No Signal
-3
Gain
From Rx and Rg input
Both differential and Single
Ended
33
THD
Vin 1Vpp / 1 REN
Typ.
STLC30R81
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
MAX.
0.063
A1
0.05
0.15
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
b
0.30
0.37
0.45
0.012
0.014
0.018
c
0.09
0.20
0.003
D
11.80
12.00
12.20
0.464
D1
9.80
10.00
10.20
0.386
0.006
0.008
0.472
0.480
0.394
0.401
D3
8.00
0.315
e
0.80
0.031
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
H
5.89
0.232
L
0.45
L1
6.00
S1
6.00
ccc
0.75
0.018
1.00
S
K
0.60
OUTLINE AND
MECHANICAL DATA
0.024
0.030
0.039
0.236
0.236
TQFP44 (10x10x1.40mm)
with Slug Down
0˚ (min.), 3.5˚ (typ.), 7˚(max.)
0.10
0.004
0049510 D
15/17
STLC30R81
Table 8. Revision History
Date
Revision
July 2003
1
First Issue
January 2006
2
Modified Table 7 (RPR2 and RPT2 formula) and the Figures 10 and 11.
16/17
Description of Changes
STLC30R81
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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17/17