OKI ML63611A

OKI Semiconductor
ML63611A
FEDL63611A-01
Issue Date: Jan. 28, 2004
4-Bit Microcontroller that Operates under Ultra-Low Supply Current, with RC Oscillation Type
A/D Converter Built-In
GENERAL DESCRIPTION
The ML63611A is a CMOS 4-bit microcontroller using Oki’s original CPU core nX-4/250.
The ML63611A is provided with the mask options of eight items of selection including (1.5 V or 3.0 V)
power supply specifications and (With or Without) the regulator circuit for the LCD bias reference voltage.
When a 3.0 V power supply specification is selected, the halver circuit can be used to decrease power
consumption. The halver circuit cannot be used when a 1.5 V power supply specification is selected.
When “With the regulator circuit for the LCD bias reference voltage” is selected, the LCD bias reference
voltage will be generated based on the output voltage of the regulator circuit. When “Without the regulator
circuit for the LCD bias reference voltage” is selected, the LCD bias reference voltage will be generated
based on the power supply voltage; for this reason, the LCD bias voltage decreases as the power supply
voltage decreases, causing the display density of the LCD panel to thin down.
The ML63611A has incorporated in it an 8K-word program memory, a 1K-nibble data memory, four input
ports, four output ports (only when the mask option of LCD driver pins is selected), 16 I/O ports, a melody
circuit, a serial port, four 8-bit timers, and a 64-segment LCD driver (60 segment lines and 4 common lines,
max.). (A part of the SEG pins can also be selected as output port pins or COM pins depending on the mask
option.)
!
Note:
In this datasheet, for convenience of description, the symbols OPTION A, OPTION B, OPTION C, and
OPTION D are used in accordance with the mask option selection of a power supply specification (1.5 V or 3.0
V) and the regulator circuit for the LCD bias reference voltage (With or Without), as shown below.
• OPTION A:
1.5 V power supply specification (halver circuit disabled), without the regulator circuit for the
LCD bias reference voltage
• OPTION B:
1.5 V power supply specification (halver circuit disabled), with the regulator circuit for the
LCD bias reference voltage
• OPTION C:
3.0 V power supply specification (halver circuit enabled), without the regulator circuit for the
LCD bias reference voltage
• OPTION D:
3.0 V power supply specification (halver circuit enabled), with the regulator circuit for the
LCD bias reference voltage
FEATURES
The ML63611A has the following features.
a. Extensive instruction set
•
407 instructions
Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask
operations, bit operations, ROM table reference, stack operations, flag operations, jump,
conditional branch, call/return, control
b. Wide variety of addressing modes
•
Indirect addressing mode for 4 types of data memory with current bank register, extra bank
register, HL register and XY register
•
Data memory bank internal direct addressing mode
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ML63611A
c. Processing speed
•
2 clocks per machine cycle, with most instructions executed in 1 machine cycle
•
Minimum instruction execution time: 61 µs (@ 32.768 kHz system clock)
10 µs (@ 200 kHz system clock)
2.86 µs (@ 700 kHz system clock)
d. Clock generator circuit
•
Low-speed clock:
Crystal oscillation (32.768 kHz)
•
High-speed clock:
OPTION A, OPTION B: RC oscillation (200 kHz max.)
OPTION C, OPTION D: Ceramic oscillation or RC oscillation selected with software (700 kHz
max.)
e. Program memory space
•
8K words
•
The basic instruction length is 16 bits per word.
f. Data memory space
•
1024 nibbles
g. Stack level
•
Call stack level: 16
•
Register stack level: 16
h. Ports
Input port (Port 0.0 to Port 0.3):
Selectable as input with pull-up resistor/high-impedance input
Provided with the reset function that resets the system when there is a simultaneous
key depression of multiple bits (2, 3, or 4 bits).
Output port:
Selectable as N-channel open drain output/CMOS output
Enabled only when the SEG pins (L32 to L35) are selected as the output port by the
mask option.
Input-output port (Port A.0 to Port A.3, Port B.0 to Port B.3, Port C.0 to Port C.3, Port E.0 to Port E.3):
Selectable
as
input
with
pull-up
resistor/input
with
pull-down
resistor/high-impedance input
Selectable as P-channel open drain output/N-channel open drain output/CMOS
output/high-impedance output
Number of ports:
Input ports
Output ports
Input-output ports
Chip products
1 port × 4 bits
1 port × 4 bits
4 ports × 4 bits
(mask option)
i. Melody output
•
Melody frequency:
•
Tone length:
•
Tempo:
•
Melody data:
•
Buzzer driver signal output:
529 Hz to 2979 Hz (@ 32.768 kHz)
63 varieties
15 varieties
Stored in program memory
4 kHz (@ 32.768 kHz)
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ML63611A
j. LCD driver
Segment-type LCD drivers built-in
The following pin modes can be specified for L0 to L63 by the mask option generator setting. (Refer to
the “MOGTOOL Mask Option Generator User’s Manual”.)
“z” in the table below indicates that that particular function can be selected.
SEG Pins
COM Pins
Output Port Pins
*1
*2
L0 to L3
z
z*1
—
L4 to L31
z
—
—
L32 to L35
z
—
z*2
L36 to L39
z
z*1
—
L40 to L63
z
—
—
Can be selected as a COM pin in 1-bit unit (L0 to L3, L36 to L39). A maximum of four pins
can be selected as COM pins.
Can be selected as an output port in 4-bit unit (L32 to L35).
N-channel open drain output or CMOS output can be specified for each bit.
64 (60 SEG. × 4 COM. Max.)
1/1 to 1/4 duty (fixed to 1/2 duty when at 1/2 bias)
Selectable as 1/2 or 1/3 bias (Selectable by the mask option. Refer to the
Mask Option Generator User’s Manual”.)
OPTION B, OPTION D: Regulator circuit used (0.95/1.90/2.85 V)
OPTION A, OPTION C: Regulator circuit not used (directly connected to the
power supply voltage (1.5/3.0/4.5 V))
: 64 Hz (at 1/1, 1/2, 1/4 duty), 85.3 Hz (at 1/3 duty)
: OPTION B, OPTION D: Adjustable up to 16 levels (in steps of 0.03 V)
OPTION A, OPTION C: Adjustment not available
: Selectable as all-ON mode/all-OFF mode/power down mode/normal display
mode
Number of segments :
Duty
:
Bias
:
“MOGTOOL
Frame frequency
Contrast
Display modes
k. RC oscillation type A/D converter
•
2 channels (time sharing is used)
l. System reset function
•
System reset by RESET pin (2 kHz sampling function provided)
•
System reset that resets the system when the combined bits (2, 3, or 4 bits) of the input port (Port 0)
are all set to a “H” level
(Whether system reset is disabled or enabled, the number of bits to be combined, and the polarity
can be specified by mask option. Refer to the “MOGTOOL Mask Option Generator User’s
Manual”.)
2 bits
: P0.0, P0.1
3 bits
: P0.0, P0.1, P0.2
4 bits
: P0.0, P0.1, P0.2, P0.3
m. Battery check
•
Applies to the OPTION C and OPTION D. Does not apply to the OPTION A and OPTION B.
•
Function that detects battery low voltage
•
Selection of judgment voltage by software (LD1 and LD0 bit settings of BLDCON)
•
Judgment voltage
1.80 ±0.10 V, 2.00 ±0.10 V,2.40 ±0.10 V, 2.60 ±0.10 V(Ta = 25°C)
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n. Timers, counters
•
8-bit timer:
•
•
mode
Watchdog timer:
100 Hz timer:
•
15-bit TBC:
ML63611A
4 channels
Selectable as auto-reload mode, capture mode, clock frequency measurement
1 channel
1 channel
1/100 sec. measurement possible
1 channel
1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 128 Hz signals can be read
o. Serial port
•
Mode: UART mode, synchronous mode
•
Communication speed in UART mode: 1200 bps, 2400 bps, 4800 bps, 9600 bps
•
Clock frequency in synchronous mode: 32.768 kHz (internal clock mode); external clock
frequency
•
Data length: 5 to 8 bits
p. Interrupt factors
•
External interrupt (4 sources) : Selectable as rising edge/falling edge/both rising and falling
edges
•
Internal interrupt (14 sources) : Watchdog timer interrupt × 1
Melody end interrupt × 1
ADC interrupt × 1
Timer interrupt × 4
Serial port reception interrupt × 1
Serial port transmission interrupt × 1
1/100 timer (10 Hz) interrupt × 1
Time base interrupt × 4 (2, 4, 16, and 32 Hz)
q. Operating temperature
•
–20 to +70°C
r. Power supply voltage
OPTION A, OPTION B (1.5 V versions): 1.3 to 1.7 V
Note: The operation will only be at the battery voltage and no voltage halver circuit can be used.
OPTION C, OPTION D (3.0 V versions): 1.8 to 3.6 V
Note: It is possible to select by software to use the output of the halver circuit as the power supply
of the voltage regulator circuit when the battery voltage is in the range 2.4 to 3.6 V, and to
use the battery voltage itself as the power supply of the voltage regulator circuit when the
battery voltage is in the range 1.8 to 2.4 V.
It is possible to detect whether the battery voltage is 2.4 V or 1.8 V using the BLD function.
• When the halver circuit is ON: 2.4 to 3.6 V
• When the halver circuit is OFF: 1.8 to 2.4 V
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ML63611A
s. Supply current
•
In the HALT mode, with the LCD display OFF, low-speed operation, –20 to +70°C:
OPTION A (1.5 V power supply specification, without the regulator circuit for the LCD
reference voltage):
Typ. 1.4 µA / Max. 2.8µA
OPTION B (1.5 V power supply specification, with the regulator circuit for the LCD
reference voltage):
Typ. 1.6 µA / Max. 3.0µA
OPTION C (3.0 V power supply specification, without the regulator circuit for the LCD
reference voltage):
Typ. 0.53 µA / Max. 1.2µA
OPTION D (3.0 V power supply specification, with the regulator circuit for the LCD
reference voltage):
Typ. 0.70 µA / Max. 1.4µA
bias
bias
bias
bias
t. Packages available
Package
Chip (116-pad)
Product name
ML63611A-xxxWA
(Here, ‘xxx’ denotes the code number.)
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ML63611A
MASK OPTIONS
There are nine items in the mask option of the ML63611A.
Make the settings for the following items using the MOGTOOL mask option generator. Refer to the
“MOGTOOL Mask Option Generator User’s Manual” for details of the method of making the settings.
1)
Selection of power supply voltage
Select a power supply specification for the power supply voltage to be used as either a 1.5 V power
supply specification (1.3 to 1.7 V) or a 3.0 V power supply specification (1.8 to 3.6 V).
!
Note:
When a 1.5 V power supply specification (OPTION A and OPTION B) is selected, the halver circuit and the
battery low detect circuit cannot be used.
2)
Selection of the regulator circuit for the LCD bias reference voltage
Select the LCD bias reference voltage as either the output of the regulator circuit or the power supply
voltage.
!
Note:
When power is supplied from the battery:
When “Without the regulator circuit for the LCD bias reference voltage” is selected with the mask option, the
LCD bias reference voltage will be generated based on the power supply voltage. When a 1.5 V power supply
specification is selected, VDD1 will be the pin for the LCD bias reference voltage, and when a 3.0 V power
supply specification is selected, VDD2 will be the pin for the LCD bias reference voltage. In addition, the LCD
bias voltage will decrease as the power supply voltage decreases, causing the display density of the LCD
panel to thin down.
When “With the regulator circuit for the LCD bias reference voltage” is selected, the display density will be kept
constant even if the battery voltage decreases.
3)
Selection of the initial state of Port 0
Select the initial state of Port 0 as either “input with pull-down resistor” or “input with pull-up resistor”.
This selection determines the initial value of P0PUD (P0CON1).
!
Note:
This selection applies to all four bits and it is not possible to make this selection separately for each bit.
4)
Selection of simultaneous key depression reset function of Port 0
Select the simultaneous key depression reset function and the number of bits (pins) that can be pressed
simultaneously.
The pins that are set according to the number of bits pressed simultaneously are fixed as follows:
2 bits: P0.0, P0.1; 3 bits: P0.0, P0.1, P0.2; 4 bits: P0.0, P0.1, P0.2, P0.3.
!
Note:
The system reset mode will be entered at the second falling edge of the 1 Hz signal.
5)
Selection of MDB pin output voltage level
Select whether to make the output voltage level of the melody output pin (MDB: negative logic) either
VDD or VSS when the melody is OFF.
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6)
ML63611A
SEG/COM/PORT/DATA selection of the LCD driver pins
It is possible to make the pins L0 to L3 and L36 to L39 either SEG pins or COM pins. However, it is a
maximum of four pins that can be selected as COM pins.
It is possible to make the pins L32 to L35 either SEG pins or output port pins.
The pins L4 to L31 and L40 to L63 are always SEG pins.
The segment register corresponding to the pins L0 to L63 can also be used as a DATA area.
!
Notes:
• When the selection is made as output port pins, the selection applies to all four bits.
• When the segment register is selected as the DATA area, the corresponding pins will still be outputting the
segment waveforms, and hence should be left open.
7)
Selection of the register address and data of the LCD driver pins
The allocation of the register address and data is set for each LCD driver pin.
!
Note:
It is not possible to make multiple settings for the same address and the same bit.
8)
Selection of whether or not to detect stoppage of low-speed clock oscillations
Select whether or not to detect stoppage of the low-speed clock oscillations and to transfer to the system
reset mode.
9)
Selection of the LCD bias
1/3 or 1/2 bias is selected for the LCD bias.
!
Note:
The setting of the mask option should match the setting of bit 3 of display control register 0. Otherwise, normal
waveforms are not output.
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ML63611A
BLOCK DIAGRAM
Figures 1 through 4 show the block diagram of OPTION A to D
Asterisks (*) indicate the port secondary functions.
CPU CORE : nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
Z
ALU
RSP
STACK
CAL.S:16 levels
REG.S:16 levels
G
PC
MIE
INSTRUCTION
DECODER
BUS
CONTROL
IR
INT
4
RAM
(1 KN)
HSCLK*
OSC0
OSC1
TBCCLK*
XT0
XT1
VDD3
VDD2
VDD1
C1
C2
VDD
(open) VHF
(open) HC1
(open) HC2
INT
4
TBC
DATA BUS
TST1
TST2
RST
TST
OSC
INT
100HzTC
1
INT
1
XT
INT
1
RXC*
TXC*
RXD*
TXD*
MELODY
MD
MDB
INPUT
PORT
OUTPUT
PORT
WDT
V/R2
BIAS
V/R1
VSS
P0.0 to P0.3
LP0.0 to LP0.3
(mask option of LCD
segments)
I/O
PORT
PA.0 to PA.3
PB.0 to PB.3
PC.0 to PC.3
PE.0 to PE.3
LCD
&
DSPR
L0 to L63
ADC
VCH
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
(Sync/Async)
INT
1
INT
3
V/H
TIMER
(8-bit, 4ch)
INT
2
INT
RESET
ROM
(8 KW)
INT
1
RT0
CRT0
RS0
CS0
IN0
RT1
RS1
CS1
IN1
MON*
Figure 1 OPTION A Block Diagram
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ML63611A
CPU CORE : nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
Z
ALU
RSP
STACK
CAL.S:16 levels
REG.S:16 levels
G
PC
MIE
INSTRUCTION
DECODER
BUS
CONTROL
IR
INT
4
RAM
(1 KN)
HSCLK*
OSC0
OSC1
TBCCLK*
XT0
XT1
VDD3
VDD2
VDD1
C1
C2
VDD
(open) VHF
(open) HC1
(open) HC2
INT
4
TBC
DATA BUS
TST1
TST2
RST
TST
OSC
INT
100HzTC
1
INT
1
XT
INT
1
RXC*
TXC*
RXD*
TXD*
MELODY
MD
MDB
INPUT
PORT
OUTPUT
PORT
WDT
V/R2
BIAS
V/R3
V/R1
VSS
P0.0 to P0.3
LP0.0 to LP0.3
(mask option of LCD
segments)
I/O
PORT
PA.0 to PA.3
PB.0 to PB.3
PC.0 to PC.3
PE.0 to PE.3
LCD
&
DSPR
L0 to L63
ADC
VCH
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
(Sync/Async)
INT
1
INT
3
V/H
TIMER
(8-bit, 4ch)
INT
2
INT
RESET
ROM
(8 KW)
INT
1
RT0
CRT0
RS0
CS0
IN0
RT1
RS1
CS1
IN1
MON*
Figure 2 Option B Block Diagram
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ML63611A
CPU CORE : nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
G
PC
Z
ALU
RSP
MIE
STACK
CAL.S:16 levels
REG.S:16 levels
INSTRUCTION
DECODER
BUS
CONTROL
IR
INT
4
RAM
(1 KN)
HSCLK*
OSC0
OSC1
TBCCLK*
XT0
XT1
VDD3
VDD2
VDD1
C1
C2
VHF
HC1
HC2
INT
4
TST
OSC
BLD
INT
100HzTC
1
INT
1
XT
TBC
DATA BUS
TST1
TST2
RST
INT
1
V/R2
BIAS
(use/nonuse
selected by
software)
RXC*
TXC*
RXD*
TXD*
MELODY
MD
MDB
INPUT
PORT
OUTPUT
PORT
WDT
V/R1
VSS
P0.0 to P0.3
LP0.0 to LP0.3
(mask option of LCD
segments)
I/O
PORT
PA.0 to PA.3
PB.0 to PB.3
PC.0 to PC.3
PE.0 to PE.3
LCD
&
DSPR
L0 to L63
ADC
VCH
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
(Sync/Async)
INT
1
INT
3
V/H
TIMER
(8-bit, 4ch)
INT
2
INT
RESET
ROM
(8 KW)
INT
1
RT0
CRT0
RS0
CS0
IN0
RT1
RS1
CS1
IN1
MON*
Figure 3 Option C Block Diagram
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ML63611A
CPU CORE : nX-4/250
TIMING
CONTROL
CBR
H
L
RA
EBR
X
Y
A
SP
C
G
PC
Z
ALU
RSP
MIE
STACK
CAL.S:16 levels
REG.S:16 levels
INSTRUCTION
DECODER
BUS
CONTROL
IR
INT
4
RAM
(1 KN)
HSCLK*
OSC0
OSC1
TBCCLK*
XT0
XT1
VDD3
VDD2
VDD1
C1
C2
VHF
HC1
HC2
INT
4
TST
OSC
BLD
INT
100HzTC
1
INT
1
XT
TBC
DATA BUS
TST1
TST2
RST
INT
1
V/R2
BIAS
V/R3
(use/nonuse
selected by
software)
RXC*
TXC*
RXD*
TXD*
MELODY
MD
MDB
INPUT
PORT
OUTPUT
PORT
WDT
V/R1
VSS
P0.0 to P0.3
LP0.0 to LP0.3
(mask option of LCD
segments)
I/O
PORT
PA.0 to PA.3
PB.0 to PB.3
PC.0 to PC.3
PE.0 to PE.3
LCD
&
DSPR
L0 to L63
ADC
VCH
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
(Sync/Async)
INT
1
INT
3
V/H
TIMER
(8-bit, 4ch)
INT
2
INT
RESET
ROM
(8 KW)
INT
1
RT0
CRT0
RS0
CS0
IN0
RT1
RS1
CS1
IN1
MON*
Figure 4 Option D Block Diagram
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ML63611A
PAD CONFIGURATION
L3
L2
L1
L0
96
97
98
99
TRIMB5
TRIMB4
TRIMB3
TRIMDB1
TRIMB2
TRIMB1
TRIMB0
TRIMDB2
TRIM3
TRIM2
TRIMD
TRIM1
TRIM0
100
101
102
103
104
105
106
107
108
109
110
111
112
VDD1
VDD2
VDD3
C1
C2
VCH
VXT
VHF
HC1
HC2
VSS
OSC1
OSC0
RESET
XT1
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
No-connection pads
66 L33
67 L32
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
The ML63611A chip pin configuration and the pad coordinates are shown in Figure 5 and Table 1, respectively.
Y
( 0.0 )
X
ML63611
L34
L35
VSS
PE.3
PE.2
PE.1
PE.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P0.3
P0.2
P0.1
P0.0
MDB
MD
TST2
TST1
VDD
RT1
RS1
CS1
IN1
IN0
L63
L62
L61
L60
L59
L58
L57
L56
L55
L54
L53
L52
L51
L50
L49
L48
L47
L46
L45
L44
L43
L42
L41
L40
L39
L38
L37
L36
RT0
CRT0
RS0
CS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XT0 128
VDD 129
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Chip Size
: 5.20 mm × 5.20 mm
Chip Thickness
: 350 µm (typ.) (280 µm: available as required)
Coordinate Origin
: Chip center
Pad Hole Size
: 80 µm × 80 µm
Pad Size
: 90 µm × 90 µm
Minimum Pad Pitch : 115 µm
Number of bonding pads: 116 (total number of pads: 129)
Notes: The chip substrate voltage is VSS.
Do not bond pins 100 to 112 (marked by “
”). Leave them open.
Figure 5 ML63611A Chip Pin Configuration (Top View)
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Table 1 ML63611A Pad Coordinates
Chip center: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
1
L63
-2109
-2454
34
IN1
2474
-2119
2
L62
-1987
-2454
35
CS1
2474
-1997
3
L61
-1865
-2454
36
RS1
2474
-1876
4
L60
-1742
-2454
37
RT1
2474
-1754
5
L59
-1620
-2454
38
VDD
2474
-1517
6
L58
-1498
-2454
39
TST1
2474
-1402
7
L57
-1376
-2454
40
TST2
2474
-1287
8
L56
-1254
-2454
41
MD
2474
-1157
9
L55
-1131
-2454
42
MDB
2474
-1042
10
L54
-1009
-2454
43
P0.0
2474
-912
11
L53
-887
-2454
44
P0.1
2474
-797
12
L52
-765
-2454
45
P0.2
2474
-682
13
L51
-643
-2454
46
P0.3
2474
-566
14
L50
-520
-2454
47
PA.0
2474
-448
15
L49
-398
-2454
48
PA.1
2474
-327
16
L48
-276
-2454
49
PA.2
2474
-205
17
L47
-154
-2454
50
PA.3
2474
-84
18
L46
-32
-2454
51
PB.0
2474
38
19
L45
91
-2454
52
PB.1
2474
160
20
L44
213
-2454
53
PB.2
2474
281
21
L43
335
-2454
54
PB.3
2474
403
22
L42
457
-2454
55
PC.0
2474
524
23
L41
579
-2454
56
PC.1
2474
646
24
L40
702
-2454
57
PC.2
2474
767
25
L39
824
-2454
58
PC.3
2474
889
26
L38
946
-2454
59
PE.0
2474
1010
27
L37
1068
-2454
60
PE.1
2474
1132
28
L36
1190
-2454
61
PE.2
2474
1254
29
RT0
1442
-2474
62
PE.3
2474
1375
30
CRT0
1563
-2474
63
VSS
2474
1493
31
RS0
1685
-2474
64
L35
2440
1713
32
CS0
1806
-2474
65
L34
2440
1950
33
IN0
2474
-2240
66
L33
1944
2440
13/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Table 1 ML63611A Pad Coordinates (continued)
Chip center: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
67
L32
1707
2440
99
L0
-2362
1898
68
L31
1563
2440
100
TRIMB5
69
L30
1441
2440
101
TRIMB4
70
L29
1319
2440
102
TRIMB3
71
L28
1197
2440
103
TRIMDB1
72
L27
1074
2440
104
TRIMB2
73
L26
952
2440
105
TRIMB1
74
L25
830
2440
106
TRIMB0
75
L24
708
2440
107
TRIMDB2
76
L23
586
2440
108
TRIM3
77
L22
463
2440
109
TRIM2
78
L21
341
2440
110
TRIMD
79
L20
219
2440
111
TRIM1
80
L19
97
2440
112
TRIM0
81
L18
-25
2440
113
VDD1
-2474
82
L17
-148
2440
114
VDD2
-2474
58
83
L16
-270
2440
115
VDD3
-2474
-63
84
L15
-392
2440
116
C1
-2474
-184
85
L14
-514
2440
117
C2
-2474
-305
86
L13
-636
2440
118
VCH
-2474
-426
87
L12
-759
2440
119
VXT
-2474
-547
88
L11
-881
2440
120
VHF
-2474
-668
89
L10
-1003
2440
121
HC1
-2474
-788
No-connection
179
90
L9
-1125
2440
122
HC2
-2474
-909
91
L8
-1247
2440
123
VSS
-2474
-1042
92
L7
-1370
2440
124
OSC1
-2474
-1175
93
L6
-1492
2440
125
OSC0
-2474
-1296
94
L5
-1614
2440
126
RESET
-2474
-1461
95
L4
-1736
2440
127
XT1
-2474
-1596
96
L3
-2362
2265
128
XT0
-2474
-1921
97
L2
-2362
2143
129
VDD
-2474
-2063
98
L1
-2362
2021
14/49
FEDL63611A-01
OKI Semiconductor
ML63611A
PIN DESCRIPTIONS
The basic functions of each pin of the ML63611A are described in Table 2.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 3 for secondary functions.
For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin.
Table 2 Pin Description (Basic Functions)
Classification
Power Supply
Pin
name
VDD
VSS
VDD1
VDD2
Pad No.
I/O
38, 129
63, 123
113
114
VDD3
115
C1
116
C2
117
VHF
120
VXT
119
VCH
118
HC1
121
HC2
122
XT0
128
I
XT1
127
O
OSC0
125
I
OSC1
124
O
TST1
TST2
39
40
I
—
Oscillation
Test
Function
Positive power supply
Negative power supply
Power supply pins for LCD bias voltage (internally
generated):
A capacitor (1.0 µF) should be connected between VDD1
and VSS, between VDD2 and VSS, and between VDD3 and
VSS.
For the OPTION A, connect VDD1 with VDD; for the OPTION
C, connect VDD2 with VDD.
Capacitor connection pins for LCD bias voltage generation:
A capacitor (1.0 µF) should be connected between C1 and
C2.
Power supply pin for the internal regulator:
A capacitor (0.1 µF) should be connected between this pin
and VSS. Leave this pin open for the OPTION A and
OPTION B.
Power supply pin for the voltage regulator circuit for
low-speed oscillation:
A capacitor (1.0 µF) should be connected between this pin
and VSS.
Power supply pin for the voltage regulator circuit for internal
logic:
A capacitor C1 (1.0 µF) should be connected between this
pin and VSS.
Capacitor connection pins for the halver circuit:
A capacitor (0.1 µF) should be connected between HC1
and HC2. Leave these pins open for the OPTION A and
OPTION B.
Low-speed clock oscillation pins:
Connect a crystal between XT0 and XT1, and connect
capacitor (CG) between XT0 and VSS.
High-speed clock oscillation pins:
Ceramic oscillation or RC oscillation is selected by the
software. In the OPTION A and OPTION B, only RC
oscillation is available.
If ceramic oscillation is selected, connect a ceramic
resonator between OSC0 and OSC1, and connect
capacitor (CL0, CL1) between OSC0 and VSS and between
OSC1 and VSS.
If RC oscillation is selected, connect external oscillation
resistor (ROSH) between OSC0 and OSC1.
Input pins for testing:
A pull-down resistor is internally connected to these pins.
15/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Table 2 Pin Description (Basic Functions) (continued)
Classification
Reset
Melody
Port
Pin
name
Pad No.
RESET
126
MD
41
MDB
42
P0.0
P0.1
P0.2
43
44
45
P0.3
46
PA.0
PA.1
PA.2
PA.3
PB.0
PB.1
PB.2
PB.3
PC.0
PC.1
PC.2
PC.3
PE.0
PE.1
PE.2
PE.3
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
I/O
I
O
I
Function
Reset input pin:
2 kHz sampling circuit is equipped.
Holding this pin to “H” level for 1 ms or more puts this
device into a reset state. Then, setting this pin to “L” level
starts executing an instruction from address 0000H.
A pull-down resistor is internally connected to this pin.
Melody output pin (Positive logic)
Melody output pin (Negative logic):
VDD or VSS is selectable for the pin output voltage when
melody output is turned off (mask option).
4-bit input port: Pull-up resistor input, pull-down resistor
input, or high-impedance input is selectable for each bit.
A system reset function is provided that resets the system
when there is a simultaneous key depression of multiple
bits (mask option).
4-bit input-output ports:
I/O
In input mode, pull-up resistor input, pull-down resistor
input, or high-impedance input is selectable for each bit.
In output mode, P-channel open drain output, N-channel
open drain output, CMOS output, or high-impedance
output is selectable for each bit.
I/O
I/O
I/O
16/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Table 2 Pin Description (Basic Functions) (continued)
Classification
LCD
Pin
name
L0
L1
L2
Pad No.
99
98
97
L3
96
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32/
LP0.3
L33/
LP0.2
L34/
LP0.1
L35/
LP0.0
L36
L37
L38
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
L39
25
I/O
O
Function
These pins can be selected as LCD segment signal output
pins (L0 to L3) or common signal output pins by the mask
option.
The common signal can be selected from among COM1 to
COM4.
Output pins dedicated to the LCD segment signal (L4 to
L31).
O
These pins can be selected as LCD segment signal output
pins (L32 to L35) or output port pins (LP0.0 to LP0.3) by the
mask option.
67
66
O
65
64
28
27
26
O
These pins can be selected as output pins dedicated to the
LCD segment signal (L36 to L39) or common signal output
pins by the mask option.
The common signal can be selected from among COM1 to
COM4.
17/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Table 2 Pin Description (Basic Functions) (continued)
Classification
LCD
A/D Converter
Pin
name
L40
L41
L42
L43
L44
L45
L46
L47
L48
L49
L50
L51
L52
L53
L54
L55
L56
L57
L58
L59
L60
L61
L62
L63
Pad No.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
I/O
Function
Output pins dedicated to the LCD segment signal (L40 to
L63).
O
RT0
29
CRT0
30
O
RS0
CS0
IN0
IN1
CS1
RS1
31
32
33
34
35
36
I
RT1
37
O
Resistance temperature sensor connection pin
(for channel 0)
Resistance/capacitance temperature sensor connection
pin (for channel 0)
Reference resistor connection pin (for channel 0)
Reference capacitor connection pin (for channel 0)
Input pin for RC oscillator circuit (for channel 0)
Input pin for RC oscillator circuit (for channel 1)
Reference capacitor connection pin (for channel 1)
Reference resistor connection pin (for channel 1)
Resistance temperature sensor connection pin
(for channel 1)
18/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Table 3 shows the secondary functions of each pin of the ML63611A
Table 3 Pin Description (Secondary Functions)
Classification
External
Interrupt
Capture
Timer
Pin name
Pad No.
I/O
PB.0/INT0
PB.1/INT0
PB.2/INT0
51
52
53
PB.3/INT0
54
PC.0/INT1
PC.1/INT1
PC.2/INT1
55
56
57
PC.3/INT1
58
PE.3/INT2
62
I
P0.0/INT5
P0.1/INT5
P0.2/INT5
43
44
45
I
P0.3/INT5
46
PB.0/TM0CAP
PB.1/TM1CAP
PB.0/TM0OVF
PB.1/TM1OVF
51
52
51
52
PB.2/T02CK
53
PB.3/T13CK
54
PC.0/RXD
55
PC.1/TXC
56
I
I
I
O
I
I/O
Serial Port
Monitor
I
PC.2/RXC
57
PC.3/TXD
58
O
PE.0/MON
59
O
PE.1/TBCCLK
60
O
PE.2/HSCLK
61
O
Function
External 0 interrupt input pins:
The change of input signal level causes an interrupt
to occur.
The Port B Interrupt Enable register (PBIE) enables
or disables an interrupt for each bit.
External 1 interrupt input pins:
The change of input signal level causes an interrupt
to occur.
The Port C Interrupt Enable register (PCIE) enables
or disables an interrupt for each bit.
External 2 interrupt input pin:
The change of input signal level causes an interrupt
to occur.
External 5 interrupt input pins:
The change of input signal level causes an interrupt
to occur.
The Port 0 Interrupt Enable register (P0IE) enables
or disables an interrupt for each bit.
Timer 0 capture trigger input pin
Timer 1 capture trigger input pin
Timer 0 (TM0) overflow flag output pin
Timer 1 (TM1) overflow flag output pin
External clock input pin for Timer 0 (TM0) and Timer
2 (TM2)
External clock input pin for Timer 1 (TM1) and Timer
3 (TM3)
Serial port receive data input pin
Sync serial port clock input-output pin:
Transmit sync clock input-output pin when a serial
port is used synchronously.
Transmit clock output when this device is used as a
master processor.
Transmit clock input when this device is used as a
slave processor.
Sync serial port clock input-output pin:
Receive sync clock input-output pin when a serial
port is used synchronously.
Receive clock output when this device is used as a
master processor.
Receive clock input when this device is used as a
slave processor.
Serial port transmit data output pin
Pin for monitoring the RC oscillation clock for the
A/D converter
Low-speed oscillation clock (TBCCLK) monitoring
pin
High-speed oscillation clock (HSCLK) monitoring pin
19/49
FEDL63611A-01
OKI Semiconductor
ML63611A
POWER SUPPLY CIRCUIT CONFIGURATION
Figures 6 through 9 show the power supply circuit configuration of OPTION A to D.
VDD
1.3 to 1.7 V
1.5 V
CV
Fixed in the hardware
VHF
VHF
Halver circuit
1/2VDD
LCD bias circuit
0.1 µF
Open
HC2
Open
HC1
Open
VDD3
C3
1.0 µF
VDD2
C2
1.0 µF
C12
1.0 µF
VDD1
C2
C1
XT0
V/R2
0.7 V
VXT
Low-speed clock
generator circuit
32.768 kHz
VCH
CXT
1.0 µF
CCH
1.0 µF
ENOSC (bit 1 of FCON) = “0”
or
STV (bit 2 of ADCON0) = “0”
VCH
ENOSC (bit 1 of FCON) = “1”
or
STV (bit 2 of ADCON0) = “1”
5 to 25 pF
XT1
VXT
V/R1
1.15 V
CG
Internal logic circuits (ROM, RAM, CPU, etc.)
30 pF
High-speed clock generator circuit
OSC0
OSC1
VSS
CL0
CL1
Ceramic resonator
ML63611A
Figure 6 OPTION A Power Supply Circuit Configuration
20/49
FEDL63611A-01
OKI Semiconductor
ML63611A
VDD
1.3 to 1.7 V
1.5 V
CV
Fixed in the hardware
VHF
VHF
Halver circuit
1/2VDD
V/R3
0.95 V
VDD1
LCD bias circuit
0.95 V min.
1.19 V max.
Open
HC2
Open
HC1
Open
VDD3
C3
1.0 µF
VDD2
C2
1.0 µF
VDD1
C1
1.0 µF
C12
1.0 µF
C2
C1
XT0
V/R2
0.7 V
VXT
Low-speed clock
generator circuit
5 to 25 pF
32.768 kHz
VCH
CXT
1.0 µF
CCH
1.0 µF
ENOSC (bit 1 of FCON) = “0”
or
STV (bit 2 of ADCON0) = “0”
VCH
ENOSC (bit 1 of FCON) = “1”
or
STV (bit 2 of ADCON0) = “1”
CG
XT1
VXT
V/R1
1.15 V
0.1 µF
Internal logic circuits (ROM, RAM, CPU, etc.)
30 pF
High-speed clock generator circuit
OSC0
OSC1
VSS
CL0
CL1
Ceramic resonator
ML63611A
Figure 7 OPTION B Power Supply Circuit Configuration
21/49
FEDL63611A-01
OKI Semiconductor
ML63611A
VDD
Software selection
During heavy load
(when VDD = 1.8 to 2.4 V)
VH (bit 0 of VHCON) = “1”
VHF
During normal load
(when VDD = 2.4 to 3.6 V)
VH (bit 0 of VHCON) = “0”
1.8 to 3.6 V
Halver circuit
1/2VDD
VHF
3.0 V
CV
CHF
0.1 µF
0.1 µF
HC2
HC1
CH12 0.1 µF
VDD3
C3
1.0 µF
C1
1.0 µF
C12
1.0 µF
VDD2
LCD bias circuit
VDD1
C2
C1
XT0
V/R2
0.7 V
VXT
Low-speed clock
generator circuit
32.768 kHz
VCH
CXT
1.0 µF
CCH
1.0 µF
ENOSC (bit 1 of FCON) = “0”
or
STV (bit 2 of ADCON0) = “0”
VCH
ENOSC (bit 1 of FCON) = “1”
or
STV (bit 2 of ADCON0) = “1”
5 to 25 pF
XT1
VXT
V/R1
1.15 V
CG
Internal logic circuits (ROM, RAM, CPU, etc.)
30 pF
High-speed clock generator circuit
OSC0
OSC1
VSS
CL0
CL1
Ceramic resonator
ML63611A
Figure 8 OPTION C Power Supply Circuit Configuration
22/49
FEDL63611A-01
OKI Semiconductor
ML63611A
VDD
Software selection
During heavy load
(when VDD = 1.8 to 2.4 V)
VH (bit 0 of VHCON) = “1”
VHF
During normal load
(when VDD = 2.4 to 3.6 V)
VH (bit 0 of VHCON) = “0”
V/R3
0.95 V
1.8 to 3.6 V
Halver circuit
1/2VDD
VDD1
LCD bias circuit
0.95 V min.
1.40 V max.
VHF
3.0 V
CV
CHF
VXT
HC1
CH12 0.1 µF
VDD3
C3
1.0 µF
VDD2
C2
1.0 µF
VDD1
C1
1.0 µF
C12
1.0 µF
C2
C1
Low-speed clock
generator circuit
5 to 25 pF
32.768 kHz
VCH
CXT
1.0 µF
CCH
1.0 µF
ENOSC (bit 1 of FCON) = “0”
or
STV (bit 2 of ADCON0) = “0”
VCH
ENOSC (bit 1 of FCON) = “1”
or
STV (bit 2 of ADCON0) = “1”
CG
XT1
VXT
V/R1
1.15 V
0.1 µF
HC2
XT0
V/R2
0.7 V
0.1 µF
Internal logic circuits (ROM, RAM, CPU, etc.)
30 pF
High-speed clock generator circuit
OSC0
OSC1
VSS
CL0
CL1
Ceramic resonator
ML63611A
Figure 9 OPTION D Power Supply Circuit Configuration
23/49
FEDL63611A-01
OKI Semiconductor
ML63611A
ELECTRICAL CHARACTERISTICS (3.0 V)
Absolute Maximum Ratings
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Power Supply Voltage 7
Input Voltage 1
Output Voltage 1
Output Voltage 2
Output Voltage 3
Output Voltage 4
Power Dissipation
Storage Temperature
Symbol
VDD1
VDD2
VDD3
VDD
VHF
VCH
VXT
VIN1
VOUT1
VOUT2
VOUT3
VOUT4
PD
TSTG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
VDD input, Ta = 25°C
VDD1 input, Ta = 25°C
VDD2 input, Ta = 25°C
VDD3 input, Ta = 25°C
VDD input, Ta = 25°C
Ta = 25°C
—
(VSS = 0 V)
Rating
Unit
–0.3 to +1.8
V
–0.3 to +3.6
V
–0.3 to +5.4
V
–0.3 to +3.9
V
–0.3 to +3.9
V
–0.3 to +3.9
V
–0.3 to +3.9
V
V
–0.3 to VDD+0.3
V
–0.3 to VDD1+0.3
V
–0.3 to VDD2+0.3
V
–0.3 to VDD3+0.3
V
–0.3 to VDD+0.3
8
mW
–55 to +150
°C
Recommended Operating Conditions
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
High-Speed RC Oscillator
Frequency
High-Speed Ceramic
Oscillation Frequency
(VSS = 0 V)
Unit
Symbol
TOP
VDD
fXT
Condition
—
—
CG = 5 to 25 pF
Range
–20 to +70
1.8 to 3.6
32.768k
fCRH
VDD = 1.8 to 3.6 V, ROSH = 75 kΩ
700k ±30%
Hz
fCH
VDD = 1.8 to 3.6 V
700k Max.
Hz
°C
V
Hz
24/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (1)
The regulator for the LCD bias reference is not used.
(VDD = VDD2 = 3.0 V, VSS = 0 V, 1/3 bias, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Measuring
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Circuit
CPU in HALT state,
Supply
IDD1
LCD is turned OFF
—
0.53
1.2
µA
Current 1
(High-speed clock oscillation stopped)
CPU in HALT state,
Supply
IDD2
LCD in Power Down mode
—
0.45
0.9
µA
Current 2
(High-speed clock oscillation stopped)
1
CPU operating,
LCD is turned OFF
Supply
—
2
4
µA
IDD3
Current 3
(Low-speed clock oscillation; 32.768
kHz crystal oscillation)
CPU operating
Supply
IDD4
(High-speed clock oscillation; approx.
—
450
700
µA
Current 4
700 kHz RC oscillation)
The regulator for the LCD bias reference is used
Parameter
Supply
Current 1
Supply
Current 2
Supply
Current 3
Supply
Current 4
(VDD = 3.0 V, VSS = 0 V, 1/3 bias, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
Circuit
CPU in HALT state,
IDD1
LCD is turned OFF
—
0.70
1.4
µA
(High-speed clock oscillation stopped)
CPU in HALT state,
IDD2
LCD in Power Down mode
—
0.45
0.9
µA
(High-speed clock oscillation stopped)
1
CPU operating,
LCD is turned OFF
—
2.2
4.5
µA
IDD3
(Low-speed clock oscillation; 32.768
kHz crystal oscillation)
CPU operating
IDD4
(High-speed clock oscillation; approx.
—
450
700
µA
700 kHz RC oscillation)
25/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (2)
The regulator for the LCD bias reference is not used
Parameter
(Pin Name)
Symbol
VDD1 Voltage
VDD1
VDD2 Voltage
VDD2
VDD3 Voltage
VDD3
(VDD = VDD 2= 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
1/3 bias,
V
Typ.–0.1
1/2 × VDD Typ.+0.1
1/2 bias
1/3 bias,
Typ.–0.1
VDD
Typ.+0.1
V
1/2 bias
1
1/3 bias
Typ.–0.2
V
3/2 × VDD Typ.+0.2
1/2 bias
(connected to
Typ.–0.1
VDD
Typ.+0.1
V
VDD2)
The regulator for the LCD bias reference is used
Parameter
(Pin Name)
Symbol
VDD1 Voltage
VDD1
VDD1 Voltage
Temperature
Deviation
∆VDD1
VDD2 Voltage
VDD2
VDD3 Voltage
VDD3
(VDD = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
1/3 bias,
1/2 bias
0.85
0.95
1.05
V
(Ta = 25°C)
—
—
–4
—
mV/°C
1/3 bias
1/2 bias
(connected to
VDD1)
1/3 bias
1/2 bias
Typ.–0.3
2 × VDD1
Typ.+0.3
V
Typ.–0.2
VDD1
Typ.+0.2
V
Typ.–0.4
Typ.–0.3
3 × VDD1
2 × VDD1
Typ.+0.4
Typ.+0.3
V
V
1
26/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (3)
(VDD = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
(Pin Name)
VHF Voltage
VHF
—
—
1/2 × VDD
(under a normal load)
0.8
1.15
VCH Voltage
VCH
(under a heavy load)
VDD–0.2
VDD
Crystal
Oscillation start time:
Oscillation Start
VSTA
1.8
—
within 5 seconds
Voltage
Crystal
Oscillation Hold
VHOLD
—
1.8
—
Voltage
External Crystal
Oscillator
CG
—
5
—
Capacitance
Internal Crystal
Oscillator
CD
—
20
25
Capacitance
External
Ceramic
CL0, CL1
700kHz
—
33
Oscillator
Capacitance
Internal
RC
Oscillator
COS
—
8
12
Capacitance
LD1 = 1, LD0 = 1,
2.5
2.6
Ta = 25°C
LD1 = 1, LD0 = 0,
2.3
2.4
BLD Judgment
Ta = 25°C
VBLDC
Voltage
LD1 = 0, LD0 = 1,
1.9
2.0
Ta = 25°C
LD1 = 0, LD0 = 0,
1.7
1.8
Ta = 25°C
BLD Judgment
—
1.70
Ta = –20 to +25°C
Voltage
∆VBLDC
Temperature
—
1.50
Ta = +25 to +70°C
Deviation
Max.
Unit
—
1.5
VDD+0.1
V
V
V
—
V
—
V
25
pF
30
pF
—
pF
16
pF
2.7
V
2.5
V
2.1
V
1.9
V
2.10
mV/°C
2.00
mV/°C
Measuring
Circuit
1
—
27/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (4)
(VDD = 3.0 V, VDD1 = 1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
(Pin Name)
Circuit
Output Current 1
(PA.0 to PA.3)
VOH1 = VDD–0.5 V
–6.0
–3.5
–1.0
mA
(PB.0 to PB.3)
IOH1
(PC.0 to PC.3)
(PE.0 to PE.3)
IOL1
VOL1 = 0.5 V
1.0
3.5
6.0
mA
Output Current 2
IOH2
VOH2 = VDD–0.7 V
–20.0
–11.0
–3.5
mA
(MD, MDB)
VOL2 = 0.7 V
1.0
3.5
6.0
mA
IOL2
IOH3
VOH3 = VDD3–0.2 V (VDD3 level)
—
—
–4
µA
IOMH3
VOMH3 = VDD2+0.2 V (VDD2 level)
4
—
—
µA
VOMH3S = VDD2–0.2 V (VDD2 level)
—
—
–4
µA
Output Current 3 IOMH3S
(L0 to L63)
IOML3
VOML3 = VDD1+0.2 V (VDD1 level)
4
—
—
µA
IOML3S
VOML3S = VDD1–0.2 V (VDD1 level)
—
—
–4
µA
VOL3 = VSS+0.2 V (VSS level)
4
—
—
IOL3
µA
Output Current 4*
(L32 to L35)
IOH4
VOH4 = VDD–0.5 V
–12.0
–6.5
–2.0
mA
IOL4
VOL4 = 0.5 V
VOH5R = VDD–0.5 V (RC
oscillation)
VOL5R = 0.5 V (RC oscillation)
VOH5C = VDD–0.5 V (ceramic
oscillation)
VOL5C = 0.5 V (ceramic
oscillation)
1.0
3.5
6.0
mA
–2.5
–1.3
–0.25
mA
0.25
1.5
2.5
mA
–500
–250
–100
µA
200
500
800
µA
IOH5R
Output Current 5
(OSC1)
IOL5R
IOH5C
IOL5C
Output Current 6
(RT0, RT1, RS0,
RS1, CRT0,
CS0, CS1)
Output Leakage
Current
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
IOH6
VOH6 = VDD–0.1 V
–2.5
–0.8
–0.3
mA
IOL6
VOL6 = 0.1 V
0.3
1.3
2.5
mA
IOOH
VOH = VDD
—
—
0.3
µA
IOOL
VOL = VSS
–0.3
—
—
µA
2
* Applies only when L32 to L35 are selected as the output port in a mask option.
28/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (5)
(VDD = 3.0 V, VDD1 = 1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
(Pin Name)
Circuit
IIH1
VIH1 = VDD (when pulled down)
7.5
50
100
µA
Input Current 1
VIL1 = VSS
(P0.0 to P0.3)
IIL1
–100
–50
–7.5
µA
(when pulled up)
(PA.0 to PA.3)
VIH1 = VDD
(PB.0 to PB.3)
IIH1Z
0
—
1
µA
(in a high impedance state)
(PC.0 to PC.3)
VIL1 = VSS
(PE.0 to PE.3)
IIL1Z
–1
—
0
µA
(in a high impedance state)
IIL2
VIL2 = VSS (when pulled up)
–350
–170
–30
µA
IIH2R
VIH2R = VDD (RC oscillation)
0
—
1
µA
Input Current 2
IIL2R
VIL2R = VSS (RC oscillation)
–1
—
0
µA
(OSC0)
3
IIH2C
VIH2C = VDD (ceramic oscillation)
0.5
1.8
4.0
µA
IIL2C
VIL2C = VSS (ceramic oscillation)
–4.0
–1.8
–0.5
µA
IIH3
VIH3 = VDD (when pulled down)
80
250
500
µA
VIH3 = VDD
Input Current 3
IIH3Z
0
—
1
µA
(in a high impedance state)
(IN0, IN1)
VIL3 = VSS
–1
—
0
µA
IIL3Z
(in a high impedance state)
Input Current 4
IIH4
VIH4 = VDD
150
1100
2400
µA
(RESET)
VIL4 = VSS
–1
—
0
µA
IIL4
IIH5
VIH5 = VDD
0.5
3.0
5.5
mA
Input Current 5
(TST1, TST2)
IIL5
VIL5 = VSS
–1.0
—
0
µA
29/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (6)
(VDD = 3.0 V, VDD1 = 1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
(Pin Name)
Circuit
Input Voltage 1
(P0.0 to P0.3)
VIH1
—
2.4
—
3.0
V
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
VIL1
—
0
—
0.6
V
(PE.0 to PE.3)
Input Voltage 2
VIH2
—
2.4
—
3.0
V
(OSC0)
VIL2
—
0
—
0.6
V
Input Voltage 3
VIH3
—
2.4
—
3.0
V
(IN0, IN1)
VIL3
—
0
—
0.6
V
Input Voltage 4
VIH4
—
2.4
—
3.0
V
(RESET, TST1,
4
VIL4
—
0
—
0.6
V
TST2)
Hysteresis Width 1
(P0.0 to P0.3)
(PA.0 to PA.3)
—
0.2
0.5
1.0
V
∆VT1
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
Hysteresis Width 2
(RESET, TST1,
—
0.2
0.5
1.0
V
∆VT2
TST2)
Input Pin
Capacitance
(P0.0 to P0.3)
(PA.0 to PA.3)
CIN
—
—
—
5
pF
—
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
30/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Measuring circuit 1
RT0
HC1
CS0
RT0
RI0
CS0
IN0
CG
XT0
CH12
HC2
XT1
32.768 kHz
C1
C12
crystal
C2
1
OSC0
2
OSC1
VSS
VDD
A
VDD1
VDD2
C1
C2
V
CCH, CHT, CXT, C12
C1, C2, C3, CH12
CG
CL0, CL1
RT0
CS0
RI0
Ceramic resonator
VCH
VDD3
CCH
C3
V
CHF
CXT
V
V
VXT
VHF
V
*1 RC Oscillation
: 0.1 µF
: 1.0 µF
: 15 pF
: 33 pF
: 10 kΩ/2 kΩ
: 820 pF
: 10 kΩ
: 700kHz
1
ROSH
2
Ceramic Oscillator
CL0
1
Ceramic
resonator
2
CL1
Measuring circuit 2
(*3)
VIH
(*2)
VIL
A
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
VXT
*2 Input logic circuit to determine a specified state.
*3 To be repeated for the specified output pins.
31/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Measuring circuit 3
(*4)
A
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
VXT
Measuring circuit 4
VIH
(*4)
VIL
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
Waveform
Monitoring
VXT
*4 To be repeated for the specified input pins.
32/49
FEDL63611A-01
OKI Semiconductor
ML63611A
AC Characteristics (Serial Interface, Serial Port)
(VDD = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Synchronous Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
tf
—
—
—
1
µs
TXC/RXC Input Rise Time
tr
—
—
—
1
µs
tCWL
—
0.8
—
—
µs
tCWH
—
0.8
—
—
µs
TXC/RXC Input “L” Level
Pulse Width
TXC/RXC Input “H” Level
Pulse Width
TXC/RXC Input Cycle Time
tCYC
—
2
—
—
µs
TXC/RXC Output Cycle Time
tCYC (0)
CPU operating at 32.768 kHz
—
30.5
—
µs
TXD Output Delay Time
tDDR
Output load capacitance 10 pF
—
—
0.4
µs
RXD Input Setup Time
tDS
—
0.5
—
—
µs
RXD Input Hold Time
tDH
—
0.8
—
—
µs
Synchronous communication timing
(“H” level = 2.4 V, “L” level = 0.6 V)
tCYC
VDD
TXC (PC.1)/
RXC (PC.2)
tr
VSS
tf
tCWH
tCWL
tDDR
tDD
VDD
TXD (PC.3)
VSS
tDS
tDH
tDS
VDD
RXD (PC.0)
VSS
33/49
FEDL63611A-01
OKI Semiconductor
ML63611A
UART Communication
Parameter
Symbol
Transmit Baud Rate
TBRT
Receive Baud Rate
RBRT
Condition
TBRT = 1/fBRT
TCR = 1/fOSC
RBRT = 1/fBRT
Min.
Typ.
Max.
Unit
TBRT—TCR
TBRT
TBRT+TCR
s
RBRT×0.97
RBRT
RBRT×1.03
s
fBRT: Baud rates (9600, 4800, 2400 and 1200 bps)
UART communication timing
(“H” level = 2.4 V, “L” level = 0.6 V)
TBRT
VDD
TXD(PC.3)
VSS
RBRT
RXD(PC.0)
VDD
VSS
34/49
FEDL63611A-01
OKI Semiconductor
ML63611A
AC Characteristics (RC Oscillation Type A/D Converter)
(VDD = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Resistor for
Oscillation
RS0,
RS1,
RT0,
RT0-1,
RT1
CS0, CT0, CS1 ≥ 740 pF
1
—
—
kΩ
Input Current
Limiting Resistor
RI0,
Rl1
—
1
10
—
kΩ
fOSC1
Resistor for oscillation = 2 kΩ
170
210
250
kHz
fOSC2
Resistor for oscillation = 10 kΩ
38.0
47.0
56.0
kHz
fOSC3
Resistor for oscillation = 200 kΩ
2.30
2.80
3.30
kHz
Kf1
RT0, RT0-1, RT1 = 2 kΩ
3.9
4.2
4.5
—
Kf2
RT0, RT0-1, RT1 = 10 kΩ
0.990
1.0
1.010
—
Kf3
RT0, RT0-1, RT1 = 200 kΩ
0.057
0.061
0.065
—
(Pin Name)
Oscillation
Frequency
RS•RT Oscillation
Frequency Ratio
(*)
Measuring
Circuit
5
* Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor
in the same condition.
fOSCX (RT0 – CS0 Oscillation)
fOSCX (RS0 – CS0 Oscillation) ,
fOSCX (RT0-1 – CS0 Oscillation)
Kfx =
fOSCX (RS0 – CS0 Oscillation) ,
fOSCX (RT1 – CS1 Oscillation)
fOSCX (RS1 – CS1 Oscillation)
(x = 1, 2, 3)
Measuring circuit 5
Oscillation Mode Specified
RT1 RS1 CS1 IN1
RESET
TST1
TST2
P0.0
P0.1
P0.2
P0.3
VDD
IN0 CS0 RS0
CRT0
RT0
RT0-1
CT0
RS0
RI0
CS0
(CROSC0)
RI1
CS1
RS1
RT1
(CROSC1)
RT0
PE.0
Frequency
Measurement
(fOSCX)
D.U.T
VSS
RT0,RT0-1,RT1=2 kΩ / 10 kΩ / 200 kΩ
RS0,RS1=10 kΩ
RI0,RI1=10 kΩ
CS0,CT0,CS1 = 820 pF
35/49
FEDL63611A-01
OKI Semiconductor
ML63611A
ELECTRICAL CHARACTERISTICS (1.5 V)
Absolute Maximum Ratings
Symbol
VDD1
VDD2
VDD3
VDD
VCH
VXT
VIN1
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
VDD input, Ta = 25°C
(VSS = 0 V)
Rating
Unit
–0.3 to +1.8
V
–0.3 to +3.4
V
–0.3 to +5.1
V
–0.3 to +2.0
V
–0.3 to +2.0
V
–0.3 to +2.0
V
V
–0.3 to VDD+0.3
Output Voltage 1
VOUT1
VDD1 input, Ta = 25°C
–0.3 to VDD1+0.3
V
Output Voltage 2
VOUT2
VDD2 input, Ta = 25°C
–0.3 to VDD2+0.3
V
Output Voltage 3
VOUT3
VDD3 input, Ta = 25°C
–0.3 to VDD3+0.3
V
Output Voltage 4
VOUT4
VDD input, Ta = 25°C
–0.3 to VDD+0.3
V
PD
Ta = 25°C
1
mW
TSTG
—
–55 to +150
°C
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Input Voltage 1
Power Dissipation
Storage Temperature
Recommended Operating Conditions
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation
Frequency
High-Speed RC Oscillator
Frequency
Symbol
TOP
VDD
Condition
—
—
Range
–20 to +70
1.3 to 1.7
Unit
°C
V
fXT
CG = 5 to 25 pF
32.768 k
Hz
fCRH
VDD = 1.3 to 1.7V, ROSH = 200 kΩ
200 k ± 30 %
Hz
36/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (1)
The regulator for the LCD bias reference is not used.
(VDD = VDD1 = 1.5 V, VSS = 0 V, 1/3 bias, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Supply
Current 1
IDD1
Supply
Current 2
IDD2
Supply
Current 3
IDD3
Supply
Current 4
IDD4
Condition
CPU in HALT state,
LCD is turned OFF
(High-speed clock oscillation stopped)
CPU in HALT state,
LCD in Power Down mode
(High-speed clock oscillation stopped)
CPU operating,
LCD is turned OFF
(Low-speed clock oscillation; 32.768
kHz crystal oscillation)
CPU operating
(High-speed clock oscillation; approx.
200 kHz RC oscillation)
Min.
Typ.
Max.
Unit
—
1.4
2.8
µA
—
0.9
1.8
µA
Measuring
Circuit
1
—
4.0
8.0
µA
—
80
150
µA
The regulator for the LCD bias reference is used.
Parameter
Supply
Current 1
Supply
Current 2
Supply
Current 3
Supply
Current 4
(VDD = 1.5 V, VSS = 0 V, 1/3 bais, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
Circuit
CPU in HALT state,
LCD is turned OFF
—
1.6
3.0
µA
IDD1
(High-speed clock oscillation
stopped)
CPU in HALT state,
LCD in Power Down mode
IDD2
—
0.9
1.8
µA
(High-speed clock oscillation
stopped)
1
CPU operating,
LCD is turned OFF
IDD3
—
4.2
8.5
µA
(Low-speed clock oscillation; 32.768
kHz crystal oscillation)
CPU operating
(High-speed clock oscillation; approx.
—
80
150
µA
IDD4
200 kHz RC oscillation)
37/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (2)
The regulator for the LCD bias reference is not used.
Parameter
(Pin Name)
Symbol
VDD1 Voltage
VDD1
VDD2 Voltage
VDD2
VDD3 Voltage
VDD3
(VDD = VDD 1= 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
1/3 bias,
Typ.+0.1
V
Typ.–0.1
VDD
1/2 bias
1/3 bias
Typ.–0.2
Typ.+0.2
V
2 × VDD
1/2 bias
1
Typ.–0.1
VDD
Typ.+0.1
V
(connected to VDD1)
1/3 bias
Typ.–0.3
Typ.+0.3
V
3 × VDD
1/2 bias
Typ.–0.2
Typ.+0.2
V
2 × VDD
The regulator for the LCD bias reference is used.
Parameter
(Pin Name)
Symbol
VDD1 Voltage
VDD1
VDD1 Voltage
Temperature
Deviation
∆VDD1
VDD2 Voltage
VDD2
VDD3 Voltage
VDD3
(VDD = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
1/3 bias,
1/2 bias
0.85
0.95
1.05
V
(Ta = 25°C)
—
—
–4
—
mV/
°C
1/3 bias
1/2 bias
(connected to VDD1)
1/3 bias
1/2 bias
Typ.–0.3
2 × VDD1
Typ.+0.3
V
Typ.–0.2
VDD1
Typ.+0.2
V
Typ.–0.4
Typ.–0.3
3 × VDD1
2 × VDD1
Typ.+0.4
Typ.+0.3
V
V
1
38/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (3)
Parameter
(Pin Name)
Symbol
VCH Voltage
VCH
Crystal Oscillation
Start Voltage
VSTA
Crystal Oscillation
Hold Voltage
External Crystal
Oscillator
Capacitance
Internal Crystal
Oscillator
Capacitance
Internal RC
Oscillator
Capacitance
VHOLD
(VDD = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
(under a normal
0.8
1.15
1.5
V
load)
(under a heavy
VDD
VDD+0.1
V
VDD–0.2
load)
Oscillation start
time:
1.3
—
—
V
within 5 seconds
—
1.3
—
—
V
1
CG
—
5
—
25
pF
CD
—
20
25
30
pF
COS
—
8
12
16
pF
39/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (4)
(VDD = 1.5 V, VDD1 =1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
(Pin Name)
Circuit
Output Current 1
(PA.0 to PA.3)
IOH1
VOH1 = VDD –0.5 V
–2.5
–1.4
–0.4
mA
(PB.0 to PB.3)
(PC.0 to PC.3)
IOL1
VOL1 = 0.5 V
0.4
1.4
2.5
mA
(PE.0 to PE.3)
Output Current 2
IOH2
VOH2 = VDD –0.7 V
–4.0
–2.0
–0.5
mA
(MD,MDB)
IOL2
VOL2 = 0.7 V
0.5
2.0
4.0
mA
IOH3
VOH3 = VDD3–0.2 V (VDD3 level)
—
—
–4
µA
IOMH3
VOMH3 = VDD2 +0.2 V (VDD2 level)
4
—
—
µA
VOMH3S = VDD2 –0.2 V (VDD2 level)
—
—
–4
µA
Output Current 3 IOMH3S
(L0 to L63)
IOML3
VOML3 = VDD1 +0.2 V (VDD1 level)
4
—
—
µA
IOML3S
VOML3S = VDD1 –0.2 V (VDD1 level)
—
—
–4
µA
IOL3
VOL3 = VSS +0.2 V (VSS level)
4
—
—
µA
Output Current
IOH4
VOH4 = VDD –0.5 V
–3.5
–1.7
–0.6
mA
2
4*
(L32 to L35)
VOL4 = 0.5 V
0.4
1.4
2.5
mA
IOL4
VOH5R = VDD –0.5 V
Output Current 5 IOH5R
–1.4
–0.7
–0.1
mA
(RC oscillation)
(OSC1)
IOL5R
VOL5R = 0.5 V (RC oscillation)
0.1
0.8
1.4
mA
Output Current 6
IOH6
VOH6 = VDD –0.1 V
–1.1
–0.4
–0.1
mA
(RT0,RT1,RS0 ,
RS1,CRT0,
VOL6 = 0.1 V
0.1
0.6
1.2
mA
IOL6
CS0,CS1)
Output Leakage
IOOH
VOH = VDD
—
—
0.3
µA
Current
(PA.0 to PA.3)
(PB.0 to PB.3)
IOOL
VOL = VSS
–0.3
—
—
(PC.0 to PC.3)
µA
(PE.0 to PE.3)
* Applies only when L32 to L35 are selected as the output port in a mask option.
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FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (5)
(VDD = 1.5 V, VDD1 =1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ. Max.
Unit
(Pin Name)
Circuit
Input Current 1
(P0.0 to P0.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
Input Current 2
(OSC0)
Input Current 3
(IN0, IN1)
IIH1
VIH1 = VDD (when pulled down)
1.2
5.0
11.0
µA
IIL1
VIL1 = VSS (when pulled up)
–11.0
–5.0
–1.2
µA
0
—
1
µA
–1
—
0
µA
–100
0
–1
10
–50
—
—
50
–10
1
0
100
µA
µA
µA
µA
0
—
1
µA
–1
—
0
µA
10
–1
50
–1.0
180
—
750
—
350
0
1500
0
µA
µA
µA
µA
IIH1Z
IIL1Z
IIL2
IIH2R
IIL2R
IIH3
IIH3Z
IIL3Z
Input Current 4
(RESET)
Input Current 5
(TST1, TST2)
IIH4
IIL4
IIH5
IIL5
VIH1 = VDD
(in a high impedance state)
VIL1 = VSS
(in a high impedance state)
VIL2 = VSS (when pulled up)
VIH2R = VDD (RC oscillation)
VIL2R = VSS (RC oscillation)
VIH3 = VDD (when pulled up)
VIH3 = VDD
(in a high impedance state)
VIL3 = VSS
(in a high impedance state)
VIH4 = VDD
VIL4 = VSS
VIH5 = VDD
VIL5 = VSS
3
41/49
FEDL63611A-01
OKI Semiconductor
ML63611A
DC Characteristics (6)
(VDD = 1.5 V, VDD1 =1.50 V, VDD2 = 3.00 V, VDD3 = 4.50 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
(Pin Name)
Circuit
Input Voltage 1
(P0.0 to P0.3)
VIH1
—
1.2
—
1.5
V
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)
—
0
—
0.3
V
VIL1
(PE.0 to PE.3)
Input Voltage 2
VIH2
—
1.2
—
1.5
V
(OSC0)
VIL2
—
0
—
0.3
V
Input Voltage 3
VIH3
—
1.2
—
1.5
V
(IN0, IN1)
—
0
—
0.3
V
VIL3
Input Voltage 4
VIH4
—
1.2
—
1.5
V
4
(RESET, TST1,
VIL4
—
0
—
0.3
V
TST2)
Hysteresis Width 1
(P0.0 to P0.3)
(PA.0 to PA.3)
—
0.05
0.1
0.3
V
∆VT1
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
Hysteresis Width 2
—
0.05
0.1
0.3
V
(RESET, TST1,
∆VT2
TST2)
Input Pin
Capacitance
(P0.0 to P0.3)
(PA.0 to PA.3)
CIN
—
—
—
5
pF
—
(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
42/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Measuring circuit 1
RT0
CS0
RT0
RI0
CS0
CG
IN0
XT0
C1
XT1
C12
C2
1
OSC0
2
OSC1
32.768 kHz
crystal
(*1)
VSS
VDD
VDD2
VDD1
A
C1
C2
V
CCH,CXT
C1,C2,C3,C12
CG
RT0
CS0
RI0
:
:
:
:
:
:
VDD3
VCH
C3
V
CCH
CXT
V
V
0.1 µF
1.0 µF
15 pF
10 k Ω / 2 k Ω
820 pF
10 k Ω
VXT
*1 RC Oscillation
1
ROSH
2
Measuring circuit 2
(*3)
VIH
(*2)
VIL
A
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
VXT
*2 Input logic circuit to determine a specified state.
*3 To be repeated for the specified output pins.
43/49
FEDL63611A-01
OKI Semiconductor
ML63611A
Measuring circuit 3
(*4)
A
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
VXT
Measuring circuit 4
VIH
(*4)
VIL
INPUT
VSS
OUTPUT
VDD
VDD1
VDD2
VDD3
VCH
VHF
Waveform
Monitoring
VXT
*4 To be repeated for the specified input pins.
44/49
FEDL63611A-01
OKI Semiconductor
ML63611A
AC Characteristics (Serial Interface, Serial Port)
(VDD = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Synchronous Communication
Parameter
TXC/RXC Input Fall Time
TXC/RXC Input Rise Time
TXC/RXC Input “L” Level
Pulse Width
TXC/RXC Input “H” Level
Pulse Width
TXC/RXC Input Cycle Time
TXC/RXC Output Cycle Time
Symbol
tf
tr
Condition
—
—
Min.
—
—
Typ.
—
—
Max.
1
1
Unit
µs
µs
tCWL
—
0.8
—
—
µs
tCWH
—
0.8
—
—
µs
tCYC
tCYC (0)
2
—
—
30.5
—
—
µs
µs
TXD Output Delay Time
tDDR
—
—
0.4
µs
RXD Input Setup Time
RXD Input Hold Time
tDS
tDH
—
CPU operating at 32.768 kHz
Output load capacitance 10
pF
—
—
0.5
0.8
—
—
—
—
µs
µs
Synchronous communication timing
(“H” level = 1.2 V, “L” level = 0.3 V)
tCYC
VDD
TXC (PC.1)/
RXC (PC.2)
tr
VSS
tf
tCWH
tCWL
tDDR
tDD
VDD
TXD (PC.3)
VSS
tDS
tDH
tDS
VDD
RXD (PC.0)
VSS
45/49
FEDL63611A-01
OKI Semiconductor
ML63611A
UART Communication
Parameter
Symbol
Transmit Baud Rate
TBRT
Receive Baud Rate
RBRT
Condition
TBRT = 1/fBRT
TCR = 1/fOSC
RBRT = 1/fBRT
Min.
Typ.
Max.
Unit
TBRT—TCR
TBRT
TBRT+TCR
s
RBRT×0.97
RBRT
RBRT×1.03
s
fBRT: Baud rates (9600, 4800, 2400 and 1200bps)
UART communication timing
(“H” level = 1.2 V, “L” level = 0.3 V)
TBRT
VDD
TXD(PC.3)
VSS
RBRT
RXD(PC.0)
VDD
VSS
46/49
FEDL63611A-01
OKI Semiconductor
ML63611A
AC Characteristics (RC Oscillation Type A/D Converter)
(VDD = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
Circuit
Parameter
Symbol
Resistor for
Oscillation
RS0, RS1,
RT0,
RT0-1,
RT1
CS0, CT0, CS1 ≥ 740 pF
1
—
—
kΩ
Input Current
Limiting Resistor
RI0, RI1
—
1
10
—
kΩ
fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
Resistor for Oscillation = 2 kΩ
Resistor for Oscillation = 10 kΩ
Resistor for Oscillation = 200 kΩ
RT0, RT0-1, RT1 = 2 kΩ
RT0, RT0-1, RT1 = 10 kΩ
RT0, RT0-1, RT1 = 200 kΩ
180
41.0
2.30
3.9
0.990
0.053
220
50.0
2.80
4.2
1.0
0.057
260
59.0
3.30
4.5
1.010
0.061
kHz
kHz
kHz
—
—
—
Oscillation
Frequency
RS•RT Oscillation
Frequency Ratio
(*)
5
Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor
in the same condition.
fOSCX (RT0 – CS0 Oscillation)
Kfx =
fOSCX (RS0 – CS0 Oscillation) ,
fOSCX (RT0-1 – CS0 Oscillation)
fOSCX (RS0 – CS0 Oscillation) ,
fOSCX (RT1 – CS1 Oscillation)
fOSCX (RS1 – CS1 Oscillation)
(x = 1, 2, 3)
Measuring circuit 5
Oscillation Mode Specified
RT1 RS1 CS1 IN1
RESET
TST1
TST2
P0.0
P0.1
P0.2
P0.3
VDD
IN0 CS0 RS0
CRT0
RT0
RT0-1
CT0
RS0
RI0
CS0
(CROSC0)
RI1
CS1
RS1
RT1
(CROSC1)
RT0
PE.0
Frequency
Measurement
(fOSCX)
D.U.T
VSS
RT0,RT0-1,RT1=2 kW / 10 kW / 200 kW
RS0,RS1=10 kW
RI0,RI1=10 kW
CS0,CT0,CS1 = 820 pF
47/49
FEDL63611A-01
OKI Semiconductor
ML63611A
REVISION HISTORY
Document
No.
FEDL63611A-01
Date
Jan 28. 2004
Page
Previous Current
Edition
Edition
–
–
Description
Final edition 1
48/49
FEDL63611A-01
OKI Semiconductor
ML63611A
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
49/49