STMICROELECTRONICS STM8AF5X27TAY

STM8AF61xx, STM8H61xx
STM8AF51xx, STM8AH51xx
Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM,
10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V
Features
Core
■
Max fCPU: 24 MHz
■ Advanced STM8A core with Harvard
architecture and 3-stage pipeline
■ Average 1.6 cycles/instruction resulting in 10
MIPS at 16 MHz fCPU for industry standard
benchmark
Memories
■
Program memory: 48 to 128 Kbytes Flash; data
retention 20 years at 55 °C after 1 kcycle
■ Data memory: 1.5 to 2 Kbytes true data
EEPROM; endurance 300 kcycles
■ RAM: 3 to 6 Kbytes
Clock management
■
Low power crystal resonator oscillator with
external clock input
■ Internal, user-trimmable 16 MHz RC and low
power 128 kHz RC oscillators
■ Clock security system with clock monitor
Reset and supply management
■
Multiple low power modes (wait, slow, auto
wake-up, halt) with user definable clock gating
■ Low consumption power-on and power-down
reset
LQFP48 7x7
LQFP80 14x14
LQFP32 7x7
Communication interfaces
■
High speed 1 Mbit/s active CAN 2.0B interface
USART with clock output for synchronous
operation - LIN master mode
■ LINUART LIN 2.1 compliant, master/slave
modes with automatic resynchronization
■ SPI interface up to 10 Mbit/s or (fCPU/2)
2
■ I C interface up to 400 Kbit/s
■
Analog to digital converter (ADC)
■
Nested interrupt controller with 32 interrupt
vectors
■ Up to 37 external interrupts on 5 vectors
Timers
■
■
■
■
■
Up to 2 auto-reload 16-bit PWM timers with up
to 3 CAPCOM channels each (IC, OC or PWM)
Multipurpose timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
8-bit AR system timer with 8-bit prescaler
Auto wake-up timer
2 watchdog timers: Window and standard
August 2008
10-bit, 3 LSB ADC with up to 16 multiplexed
channels
I/Os
■
Up to 70 user pins including 10 high sink I/Os
■
Highly robust I/O design, immune against
current injection
Table 1.
Device summary(1)
STM8AF61xx/STM8AH61xx (without CAN)
Interrupt management
■
LQFP64 10x10
STM8AF/H61AA, STM8AF/H619A, STM8AF/H61A9,
STM8AF/H6199, STM8AF/H6189, STM8AF/H6179,
STM8AF/H6169, STM8AF/H61A8, STM8AF/H6198,
STM8AF/H6188, STM8AF/H6178, STM8AF/H6186,
STM8AF/H6176
STM8AF51xx/STM8AH51xx (with CAN)
STM8AF/H51AA, STM8AF/H519A, STM8AF/H51A9,
STM8AF/H5199, STM8AF/H5189, STM8AF/H5179,
STM8AF/H5169, STM8AF/H51A8, STM8AF/H5198,
STM8AF/H5188, STM8AF/H5178
1. This datasheet applies to product versions with and
without data EEPROM. The order code identifier is ‘F’
or ‘H’ respectively, only one of which appears in an
order code.
Rev 2
1/100
www.st.com
1
Contents
STM8AF61xx, STM8AF51xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
5.1.1
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.3
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Single wire interface module (SWIM) and debug module . . . . . . . . . . . . 13
5.2.1
SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4
Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.2
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4.3
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4.4
Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5
Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7
2/100
Central processing unit STM8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.2
Internal 16 MHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6.3
Internal 128 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6.4
Internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6.5
External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6.6
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7.1
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7.2
Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7.3
Multipurpose and PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM8AF61xx, STM8AF51xx
5.7.4
Timer 4: System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.10
6
Contents
5.9.1
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9.2
LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9.3
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9.4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9.5
CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.1
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8
Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3.1
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.3.2
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
11.3.3
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69
11.3.4
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.3.5
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3/100
Contents
STM8AF61xx, STM8AF51xx
11.3.6
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
11.3.7
TIM 1, 2, 3, and 4 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.3.8
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.3.9
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.4
12
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.4.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 89
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.2
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.3
15
4/100
14.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
STM8AF61xx, STM8AF51xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8AF/H51xx product line-up - with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8AF/H61xx product line-up - without CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STM8A timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviation for Table 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stack and RAM partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM8A I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM8A general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in run, wait and slow mode at VDD = 5.0 V. . . . . . . . . . . . . . . . 59
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption in run, wait and slow mode at VDD = 3.3 V. . . . . . . . . . . . . . . . 61
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TIM 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5/100
List of tables
Table 47.
6/100
STM8AF61xx, STM8AF51xx
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
STM8AF61xx, STM8AF51xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8A products: Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical HSI frequency vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical LSI frequency vs VDD @ room temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical pull-up resistance RPU vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 73
Typical pull-up current Ipu vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typ. VDD - VOH @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typical NRST VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical NRST pull-up resistance RPU vs VDD @ four temperatures. . . . . . . . . . . . . . . . . . 77
Typical NRST pull-up current Ipu vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . 77
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
STM8A order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7/100
Introduction
1
STM8AF61xx, STM8AF51xx
Introduction
This datasheet refers to the STM8AF61xx, STM8AH61xx, STM8AF51xx, STM8AH51xx
products with 48 to 128 Kbytes of program memory. The STM8AF51xx and STM8AH51xx
are hereafter referred to as the STM8AF/H51xx and the STM8AF61xx and STM8AH61xx
are hereafter referred to as the STM8AF/H61xx. ‘F’ refers to product versions with data
EEPROM and ‘H’ refers to product versions without EEPROM. The identifiers ‘F’ and ‘H’ do
not both appear in an order code.
The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.
8/100
●
For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8A microcontroller family reference manual (RM0009).
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8 Flash programming manual (PM0047).
●
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
STM8AF61xx, STM8AF51xx
2
Description
Description
The STM8A automotive 8-bit microcontrollers offer from 48 to 128 Kbytes of program
memory and integrated true data EEPROM.
The STM8AF/H51xx series feature a CAN interface.
All devices of the STM8A product line provide the following benefits:
●
●
●
●
Reduced system cost
–
Integrated true data EEPROM for up to 300 k write/erase cycles
–
High system integration level with internal clock oscillators, watchdog and brownout reset
Performance and robustness
–
Peak performance 20 MIPS at 24 MHz and average performance 10 MIPS at 16
MHz CPU clock frequency
–
Robust I/O, independent watchdogs with separate clock source
–
Clock security system
Short development cycles
–
Applications scalability across a common family product architecture with
compatible pinout, memory map and and modular peripherals.
–
Full documentation and a wide choice of development tools
Product longevity
–
Advanced core and peripherals made in a state-of-the art technology
–
Native automotive product family operating both at 3.3 V and 5 V supply
All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool (for more details, see Section 14: STM8 development tools on
page 96).
9/100
Product line-up
3
STM8AF61xx, STM8AF51xx
Product line-up
.
Table 2.
STM8AF/H51xx product line-up - with CAN
Order code
Package
STM8AF/H51AAT
LQFP80
(14x14)
STM8AF/H519AT
Prog.
RAM Data EE 10-bit
(bytes) (bytes) (bytes) A/D ch.
72/37
96 K
2K
16
96 K
LQFP64
(10x10)
64 K
4K
48 K
3K
STM8AF/H5169T
32 K
2K
1K
STM8AF/H51A8T
128 K
6K
2K
STM8AF/H5188T
LQFP48
(7x7)(1)
1x8-bit: TIM4
CAN,
3x16-bit: TIM1, LIN(UART),
TIM2, TIM3
SPI, USART,
(9/9/9)
I²C
1.5 K
STM8AF/H5179T
STM8AF/H5198T
I/0 wakeup
pins
128 K
STM8AF/H5199T
STM8AF/H5189T
Serial
interfaces
128 K
6K
STM8AF/H51A9T
Timers
(IC/OC/PWM)
56/36
96 K
10
64 K
4K
48 K
3K
40/35
1.5 K
STM8AF/H5178T
1. QFN package planned
²
Table 3.
STM8AF/H61xx product line-up - without CAN
Order code
Package
STM8AF/H61AAT
LQFP80
(14x14)
STM8AF/H619AT
Prog.
RAM Data EE 10-bit
(bytes) (bytes) (bytes) A/D ch.
72/37
96 K
2K
96 K
LQFP64
(10x10)
64 K
16
4K
48 K
3K
STM8AF/H6169T
32 K
2K
1K
STM8AF/H61A8T
128 K
6K
2K
STM8AF/H6188T
LQFP48
(7x7)(1)
STM8AF/H6178T
STM8AF/H6186T
STM8AF/H6176T
LQFP32
(7x7)(1)
1. QFN package planned
10/100
1x8-bit: TIM4
3x16-bit: TIM1,
TIM2, TIM3
(9/9/9)
1.5 K
STM8AF/H6179T
STM8AF/H6198T
I/0
wakeup
pins
128 K
STM8AF/H6199T
STM8AF/H6189T
Serial
interfaces
128 K
6K
STM8AF/H61A9T
Timers
(IC/OC/PWM)
LIN(UART),
SPI, USART,
I²C
56/36
96 K
10
64 K
4K
48 K
3K
64 K
4K
1.5 K
7
48 K
3K
40/35
1x8-bit: TIM4
3x16-bit: TIM1,
TIM2, TIM3
(8/8/8)
LIN(UART),
SPI, I²C
25/23
STM8AF61xx, STM8AF51xx
Block diagram
Figure 1.
STM8A block diagram
Reset block
XTAL 1-24 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
PDR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8A CORE
WDG
Single wire
debug interf.
Debug/SWIM
Master/slave
autosynchro
LINUART
400 Kbit/s
10 Mbit/s
I2C
SPI
Up to 128 Kbyte
program
Flash
Address and data bus
4
Block diagram
Up to 2 Kbytes
data EEPROM
Up to 6 Kbytes
RAM
Boot ROM
LIN master
SPI emul.
USART
16-bit multi-purpose
timer (TIM1)
1 Mbit/s
beCAN
16-bit PWM timers
(TIM2, TIM3)
16 channels
10-bit ADC
Up to
9 CAPCOM
channels
8-bit AR timer
(TIM4)
AWU timer
11/100
Product overview
5
STM8AF61xx, STM8AF51xx
Product overview
The following section intends to give an overview of the basic features of the STM8A
functional modules and peripherals.
For more detailed information please refer to the STM8A microcontroller family reference
manual (RM0009).
5.1
Central processing unit STM8A
The 8-bit STM8A core is designed for code efficiency and performance.
It contains 21 internal registers (six directly addressable in each execution context), 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
5.1.1
5.1.2
5.1.3
12/100
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus with single cycle fetching for most instructions
●
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter with 16-Mbyte linear memory space
●
16-bit stack pointer with access to a 64 Kbyte stack
●
8-bit condition code register with seven condition flags for the result of the last
instruction
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
STM8AF61xx, STM8AF51xx
5.2
Product overview
Single wire interface module (SWIM) and debug module
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming.
5.2.1
SWIM
Single wire interface for direct access to the debugging module and memory programming.
The interface can be activated in all device operation modes and supports hot-plugging. The
maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
5.3
5.4
5.4.1
●
R/W of RAM and peripheral registers in real-time
●
R/W for all resources when the application is stopped
●
Breakpoints on all program-memory instructions (software breakpoints) except the
vector table
●
Two advanced breakpoints and 23 predefined configurations
Interrupt controller
●
Nested interrupts with three software priority levels
●
32 interrupt vectors with hardware priority
●
Up to 37 external interrupts on five vectors
●
Trap and reset interrupts
Non-volatile memory
●
Up to 128 Kbytes of program single voltage Flash memory
●
Up to 2 Kbytes true (not emulated) data EEPROM
●
Read while write: Writing in the data memory is possible while executing code in the
program memory
●
128 user option bytes permit permanent device set up
Architecture
●
Array: Up to 128 Kbytes of Flash program memory organized in blocks of 128 bytes
each
●
Read granularity: 1 word = 4 bytes
●
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
Writing, erasing, word and block register management is handled automatically by the
memory interface.
13/100
Product overview
5.4.2
STM8AF61xx, STM8AF51xx
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the
memory in case of user software malfunction. Code update in user mode is still possible
after execution of a specific MASS key sequence.
The program memory is divided into two areas:
●
Main program memory: Up to 128 Kbytes minus user-specific boot code (UBC)
●
UBC: Configurable up to 128 Kbytes
The UBC area also remains write-protected during in-application programming. It permits
storage of the boot program or specific code libraries.
The boot area is a part of the program memory that contains the reset and interrupt vectors,
the reset routine and usually the IAP and communication routines. The UBC area has a
second level of protection to prevent unintentional erasing or modification during IAP
programming. This means that the MASS keys do not unlock the UBC area.
The size of the UBC is programmable through the UBC option byte, in increments of 512
bytes, by programming the UBC option byte in ICP mode.
Figure 2.
STM8A products: Flash memory organization
UBC area
Remains write protected during IAP
Flash
program
memory
Program memory area
Write access possible for IAP
Data
EEPROM
memory
Data memory area (2 Kbytes)
Option bytes
14/100
Programmable area from 1 Kbyte
(first two pages) up to program memory
end - maximum 128 Kbytes
STM8AF61xx, STM8AF51xx
5.4.3
Product overview
Read-out protection (ROP)
STM8A devices provide a read-out protection of the code and data memory by
programming the lock byte at address 4800h with the value AAh.
Read-out protection prevents reading and writing the program and data memory via the
debug module and SWIM interface. This protection is active in all device operation modes.
Any attempt to remove the protection by overwriting the lock byte triggers a global erase of
the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. This is a
specific product option and must be specified while ordering STM8A products.
Temporary read access is protected by a user defined, 8-byte keyword that is different from
00h or FFh. The keys are stored in the option byte area.
Temporary read-out can be permanently disabled by means of the option byte TMU_DIS.
For enabling temporary read access the eight access keys have to be written in the TMU
registers. A wrong code does not change the protection status. More than eight
unsuccessful access trials trigger an erase of the program and data memory.
Entering the right key sequence enables a temporary read access to the code and data
memory after a delay of several milliseconds.
The procedure for temporary read access is as follows:
●
Activate SWIM mode under device reset - the CPU is stalled, code and data memory
are not visible by the debug module.
●
Enable the internal 128 KHz LSI oscillator
●
Write the 8eight key bytes into the TMU registers
●
Set the bit(0) of the TMU status register to 1. A dedicated state machine on an isolated
bus, compares the TMU register content with the key stored in the TMU option bytes.
During this periode read and write operations have no effect. A reset re-activates the
initial protection status. The comparison can be monitored by means of the TU_CTL_ST
register.
●
In case of a successful key comparison, the SWIM interface enables read access to the
code and data memory and program execution. A comparison error does not change
the protection status but increments the counter MAXATT. If the counter content
exceedes eight unsuccessful trials, a global erase of the data and code memory is
triggered.
The read access is temporary. A device reset restores the initial protection.
5.4.4
Speed
●
Operation at up to 16 MHz CPU clock frequency without wait states. At a higher clock
frequency, a single wait state has to be inserted.
●
Programming time modes (same for word or block)
–
Fast programming: Without erase
–
Standard programming: Erase and program
15/100
Product overview
5.5
STM8AF61xx, STM8AF51xx
Low-power operating modes
The product features various low-power modes:
●
Slow mode: Prescaled CPU clock, selected peripherals at full clock speed
●
Active halt mode: CPU and peripheral clocks are stopped
●
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wake-up is triggered by an external interrupt.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules.
The RAM content is preserved and the brown-out reset circuit remains activated.
5.6
Clock and clock controller
The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low power modes and ensures clock
robustness.
5.6.1
Features
●
16/100
Clock sources:
–
Internal 16 MHz and 128 kHz RC oscillators
–
Crystal oscillator
–
External clock input
●
Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock
(16 MHz/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
Wake-up: Recovery from halt and AWU (auto wake-up) low power modes uses the
internal RC oscillator (16 MHz/8) for quick start-up and then switches to the last
selected clock source before halt mode is entered.
●
Clock security system (CSS): The CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
●
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
STM8AF61xx, STM8AF51xx
5.6.2
Product overview
Internal 16 MHz RC oscillator
●
Default clock after reset 2 MHz (16 MHz/8)
●
Wake-up time: < 2 µs
User trimming
The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign permits
frequency tuning to a precision of 1% by the application program. The trimming step
granularity is 1.5 %.
The adjustment range covers all possible frequency variations versus supply voltage and
temperature. This trimming does not change the initial production setting.
5.6.3
Internal 128 kHz RC oscillator
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the watchdog or the AWU wake-up timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3, LSI_EN).
5.6.4
Internal high-speed crystal oscillator
The internal high-speed crystal oscillator delivers the main clock in normal run mode. It
operates with quartz crystals and ceramic resonators.
●
Frequency range: 1 to 24 MHz
●
Crystal oscillation mode: Preferred fundamental
●
I/Os: Standard I/O pins multiplexed with OSCIN, OSCOUT
Optionally, an external clock signal can be injected into the OSCIN input pin.
5.6.5
External clock input
The external clock signal is applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.
5.6.6
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8). This function can be enabled
using the CSS register (CLK_CSSR).
The CSS operates by detecting when the external clock signal (crystal or external clock)
falls below 500 kHz. With active CSS this is the minimum operating frequency.
17/100
Product overview
5.7
Timers
5.7.1
Watchdog timers
STM8AF61xx, STM8AF51xx
The watchdog system is based on two independent timers providing maximum security to
the applications.
The WDG timer activity is controlled by the application program or option bytes. Once the
watchdog is activated, it cannot be disabled by the user program without a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1.
Timeout
2.
Refresh out of window: The downcounter is refreshed before its value is lower then the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.
The IWDG time base spans from 60 µs to 1 s. It can be adjusted by setting the registers of
the 7-bit prescaler and 8-bit down-counter.
5.7.2
18/100
Auto wake-up counter
●
Used for auto wake-up from active halt mode.
●
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock.
STM8AF61xx, STM8AF51xx
5.7.3
Product overview
Multipurpose and PWM timers
STM8A devices described in this datasheet, contain up to three 16-bit multipurpose and
PWM timers providing nine CAPCOM channels in total.
Table 4.
Timer
STM8A timer configuration
Counter
Timer1
Timer2
16
Timer3
Timer4
Prescaler
Type
CAPCOM
16
Up/down
4
3
Yes
0
No
3
15-bit fixed power
of 2 ratios
Up
8
Complementary Synchronization
outputs
module
7-bit fixed power
of 2 ratios
2
0
Timer 1: Multipurpose PWM timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
●
16-bit up, down and up/down AR (auto-reload) counter with 16-bit prescaler
●
Four independent CAPCOM channels configurable as input capture, output compare,
PWM generation (edge and center aligned mode) and single pulse mode output
●
Trigger module which allows the interaction of timer 1 with other timers or the ADC to
be controlled
●
Break input to force the timer outputs into a defined state
●
Three complementary outputs with adjustable dead time
●
Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break
Timer 2 and 3: 16-bit PWM timers
5.7.4
●
16-bit auto-reload up-counter
●
15-bit prescaler adjustable to fixed power of two ratios 1…32768
●
Timers with three or two individually configurable CAPCOM channels
●
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
Timer 4: System timer
●
8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128
●
Clock source: master clock
●
Interrupt source: 1 x overflow/update
19/100
Product overview
5.8
STM8AF61xx, STM8AF51xx
ADC
The STM8A products described in this datasheet, contain a 10-bit successive approximation
ADC with 16 multiplexed input channels.
General features:
●
10-bit ADC with up to 16 channels
●
Input voltage range: 0 to VDDA
●
Acqusition modes
●
–
Single conversion
–
Continous acquisition - up to 100 ksamples/s effective sampling rate
–
Trigger register and external trigger input
Interrupts
–
5.9
End of conversion (EOC) - can be masked
Communication interfaces
The following communication interfaces are implemented on STM8A products:
5.9.1
●
USART: Full feature UART, SPI emulation, LIN master capability
●
LINUART: LIN2.1 master/slave capability, full feature UART
●
SPI - full and half-duplex, 10 Mbit/s
●
I²C - up to 400 Kbit/s
●
CAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s
●
SWIM for debugging and device programming
USART
Main features
20/100
●
1 Mbit/s full duplex SCI
●
LIN master capable
●
SPI emulation
●
16-bit baud-rate prescaler
STM8AF61xx, STM8AF51xx
Product overview
Full duplex, asynchronous communication
●
NRZ standard format (mark/space)
●
High-precision baud rate generator system
–
Common programmable transmit and receive baud rates up to 2.5 M baud
●
Programmable data word length (8 or 9 bits)
●
Configurable stop bits providing support for 1 or 2 stop bits
●
LIN master mode
–
LIN break and delimiter generation
–
LIN break and delimiter detection with separate flag and interrupt source for readback checking
●
Transmitter clock output for synchronous communication
●
Single wire half duplex communication
●
Separate enable bits for transmitter and receiver
●
●
●
●
●
Transfer detection flags
–
Receive buffer full
–
Transmit buffer empty
–
End of transmission flags
Parity control:
–
Transmit parity bit
–
Check parity of received data byte
Four error detection flags
–
Overrun error
–
Noise error
–
Frame error
–
Parity error
Six interrupt sources with flags
–
Transmit data register empty
–
Transmission complete
–
Receive data register full
–
Idle line received
–
Parity error
–
LIN break and delimiter detection
Two interrupt vectors
–
Transmitter interrupt
–
Receiver interrupt
●
Reduced power consumption mode
●
Multi-processor communication, allowing entry into mute mode if address match does
not occur
●
Wakeup from mute mode (by idle line detection or address mark detection)
●
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line
21/100
Product overview
5.9.2
STM8AF61xx, STM8AF51xx
LINUART
Main features
●
LIN master/slave rev. 2.1 compliant
●
Auto-synchronization in LIN slave mode
●
16-bit baud rate prescaler
●
1 Mbit full duplex SCI
LIN master
●
Autonomous header handling
●
13-bit LIN synch break generation
LIN slave
●
Autonomous header handling - one single interrupt per valid message header
●
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
●
Synch delimiter checking
●
11-bit LIN synch break detection - break detection always active
●
Parity check on the LIN identifier field
●
LIN error management
●
Hot plugging support
Asynchronous communication (UART)
5.9.3
22/100
●
Full duplex, asynchronous communications - NRZ standard format (mark/space)
●
Independently programmable transmit and receive baud rates up to 500 Kbit/s
●
Programmable data word length (8 or 9 bits)
●
Low-power standby mode - two receiver wake-up modes:
–
Address bit (MSB)
–
Idle line
●
Muting function for multiprocessor configurations
●
Overrun, noise and frame error detection
●
Six interrupt sources
●
Tx, Rx parity control
SPI
●
Maximum speed: 10 Mbit/s or fCPU/2 both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on two lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
CRC calculation
●
1 byte Tx and Rx buffer
●
Slave/master selection input pin
STM8AF61xx, STM8AF51xx
5.9.4
I2C
●
●
I2C master features:
–
Clock generation
–
Start and stop generation
I2C
slave features:
–
Programmable I2C address detection
–
Stop bit detection
●
Generation and detection of 7-bit/10-bit addressing and general call
●
Supports different communication speeds:
●
●
5.9.5
Product overview
–
Standard speed (up to 100 kHz),
–
Fast speed (up to 400 kHz)
Interrupt:
–
Successful address/data communication
–
Error condition
–
Wake-up from halt
Wake-up from halt on address detection in slave mode
CAN
The beCAN3 controller (basic enhanced CAN), interfaces the CAN network and supports
the CAN protocol version 2.0A and B. It has been designed to manage a high number of
incoming messages efficiently with a minimum CPU load.
For safety-critical applications, the CAN controller provides all hardware functions to support
the CAN time triggered communication option (TTCAN).
The maximum transmission speed is 1 Mbit.
Transmission
●
Three transmit mailboxes
●
Configurable transmit priority by identifier or order request
●
Time stamp on SOF transmission
Reception
●
11- and 29-bit ID
●
1 receive FIFO (3 messages deep)
●
Software-efficient mailbox mapping at a unique address space
●
FMI (filter match index) stored with message
●
Configurable FIFO overrun
●
Time stamp on SOF reception
●
6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID
23/100
Product overview
●
●
STM8AF61xx, STM8AF51xx
Filtering modes:
–
Mask mode permitting ID range filtering
–
ID list mode
Time triggered communication option
–
Disable automatic retransmission mode
–
16-bit free running timer
–
Configurable timer resolution
–
Time stamp sent in last two data bytes
Interrupt management
5.10
●
Maskable interrupt
●
Software-efficient mailbox mapping at a unique address space
Input/output specifications
The product features four different I/O types:
●
Standard I/O 2 MHz
●
Fast I/O 10 MHz
●
High sink 8 mA, 2 MHz
●
True open drain (I2C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os. Selected I/Os include
a low leakage analog switch.
STM8A I/Os are designed to withstand current injection. For a negative injection current of
4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. External
protection diodes are no longer required.
24/100
STM8AF61xx, STM8AF51xx
Pinouts and pin description
6
Pinouts and pin description
6.1
Package pinouts
LQFP 80-pin pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2
PD2 (HS)/TIM3_CC1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2
PI7
PI6
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I 2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
PI5
PI4
Figure 3.
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PI3
PI2
PI1
PI0
PG4
PG3
PG2
PG1/CAN_RX(1)
PG0/CAN_TX(1)
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1
PC0/ADC_ETR
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1
AIN0/PB0
TIM1_ETR/PH4
TIM1_NCC3/PH5
TIM1_NCC2/PH6
TIM1_NCC1/PH7
AIN8/PE7
AIN9/PE6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CC3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
(HS) PH0
(HS) PH1
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
25/100
Pinouts and pin description
LQFP 64-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/ BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
Figure 4.
STM8AF61xx, STM8AF51xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PI0
PG4
PG3
PG2
PG1/CAN_RX(1)
PG0/CAN_TX(1)
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CC3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
26/100
STM8AF61xx, STM8AF51xx
LQFP 48-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
PE3/TIM1_BKIN
Figure 5.
Pinouts and pin description
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 2223 24
PG1
PG0
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CC3/PA3
PA4
PA5
PA6
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
27/100
Pinouts and pin description
LQFP 32-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CC1/BEEP
PD3 (HS)/TIM2_CC2/ADC_ETR
PD2 (HS)/TIM3_CC1/TIM2_CC3
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CC2/CLK_CCO/TIM1_BRK
Figure 6.
STM8AF61xx, STM8AF51xx
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CC4
PC3 (HS)/TIM1_CC3
PC2 (HS)/TIM1_CC2
PC1 (HS)/TIM1_CC1
PE5/SPI_NSS
VDDA
VSSA
I2C_SDA/AIN5/PB5
I2C_SCL/AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_NCC3/AIN2/PB2
TIM1_NCC2/AIN1/PB1
TIM1_NCC1/AIN0/PB0
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
(HS) high sink capability
6.2
Pin description
Table 5.
Legend/abbreviation for Table 6
Type
I= input, O = output, S = power supply
Level
Input
CM = CMOS (standard for all I/Os)
Output
HS = High sink (8 mA)
Output speed
O1 = Standard (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
configuration
Output
float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Reset state is shown in bold.
28/100
STM8AF61xx, STM8AF51xx
STM8A microcontroller family pin description
Output
I/O
X
2
2
2
2 PA1/OSCIN
I/O X
X
3
3
3
3 PA2/OSCOUT
I/O X
X
4
4
4
- VSSIO_1
S
I/O ground
5
5
5
4 VSS
S
Digital ground
6
6
6
5 VCAP
S
1.8 V regulator capacitor
7
7
7
6 VDD
S
Digital power supply
8
8
8
7 VDDIO_1
S
I/O power supply
9
9
9
- PA3/TIM2_CC3
I/O X
X
X
O1
X
X Port A3
10 10 10
- PA4/USART_RX
I/O X
X
X
O3
X
X Port A4 USART receive
11 11 11
- PA5/USART_TX
I/O X
X
X
O3
X
X Port A5 USART transmit
12 12 12
- PA6/USART_CK
I/O X
X
X
O3
X
USART
X Port A6 synchronous
clock
13
-
-
- PH0
I/O X
X
HS O3
X
X Port H0
14
-
-
- PH1
I/O X
X
HS O3
X
X Port H1
15
-
-
- PH2
I/O X
X
O1
X
X Port H2
16
-
-
- PH3
I/O X
X
O1
X
X Port H3
17 13
-
- PF7/AIN15
I/O X
X
O1
X
X Port F7
Analog input 15
18 14
-
- PF6/AIN14
I/O X
X
O1
X
X Port F6
Analog input 14
19 15
-
- PF5/AIN13
I/O X
X
O1
X
X Port F5
Analog input 13
20 16
-
8 PF4/AIN12
I/O X
X
O1
X
X Port F4
Analog input 12
21 17
-
- PF3/AIN11
I/O X
X
O1
X
X Port F3
Analog input 11
22 18
-
- VREF+
S
ADC positive reference
voltage
9 VDDA
S
Analog power supply
24 20 14 10 VSSA
S
Analog ground
25 21
-
- VREF-
S
ADC negative reference
voltage
26 22
-
- PF0/AIN10
23 19 13
I/O X
X
PP
1 NRST
OD
1
Speed
LQFP32
1
wpu
LQFP48
1
Pin name
floating
LQFP64
Main
function Default alternate
(after
function
reset)
LQFP80
High sink
Input
Type
Pin number
Ext. interrupt
Table 6.
Pinouts and pin description
Alternate
function
after
remap
[option bit]
Reset
X
O1
X
X Port A1
Resonator/crystal
in
O1
X
X Port A2
Resonator/crystal
out
O1
X
X Port F0
Timer 2 channel3
TIM3_CC1
[AFR1]
Analog input 10
29/100
Pinouts and pin description
Table 6.
STM8AF61xx, STM8AF51xx
STM8A microcontroller family pin description (continued)
Output
PP
X
X Port B7 Analog input 7
28 24 16
- PB6/AIN6
I/O X
X
X
O1
X
X Port B6 Analog input 6
29 25 17 11 PB5/AIN5
I/O X
X
X
O1
X
X Port B5 Analog input 5
I2C_SDA
[AFR6]
30 26 18 12 PB4/AIN4
I/O X
X
X
O1
X
X Port B4 Analog input 4
I2C_SCL
[AFR6]
31 27 19 13 PB3/AIN3
I/O X
X
X
O1
X
X Port B3 Analog input 3
TIM1_ETR
[AFR5]
32 28 20 14 PB2/AIN2
I/O X
X
X
O1
X
X Port B2 Analog input
TIM1_
NCC3
[AFR5]
33 29 21 15 PB1/AIN1
I/O X
X
X
O1
X
X Port B1 Analog input 1
TIM1_
NCC2
[AFR5]
34 30 22 16 PB0/AIN0
I/O X
X
X
O1
X
X Port B0 Analog input 0
TIM1_
NCC1
[AFR5]
35
-
-
- PH4/TIM1_ETR
I/O X
X
O1
X
X Port H4
Timer 1 - trigger
input
36
-
-
- PH5/ TIM1_NCC3 I/O X
X
O1
X
X Port H5
Timer 1 - inverted
channel 3
37
-
-
- PH6/TIM1_NCC2 I/O X
X
O1
X
X Port H6
Timer 1 - inverted
channel 2
38
-
-
- PH7/TIM1_NCC1 I/O X
X
O1
X
X Port H7
Timer 1 - inverted
channel 2
39 31 23
- PE7/AIN8
I/O X
X
O1
X
X Port E7
Analog input 8
40 32 24
PE6/AIN9
I/O X
X
X
O1
X
X Port E7
Analog input 9
41 33 25 17 PE5/SPI_NSS
I/O X
X
X
O1
X
X Port E5
SPI master/slave
select
42
- PC0/ADC_ETR
I/O X
X
X
O1
X
X Port C0 ADC trigger input
43 34 26 18 PC1/TIM1_CC1
I/O X
X
X
HS O3
X
X Port C1
Timer 1 - channel
1
44 35 27 19 PC2/TIM1_CC2
I/O X
X
X
HS O3
X
X Port C2
Timer 1- channel
2
45 36 28 20 PC3/TIM1_CC3
I/O X
X
X
HS O3
X
X Port C3
Timer 1 - channel
3
-
30/100
-
High sink
O1
floating
X
Pin name
Type
X
LQFP32
I/O X
LQFP48
- PB7/AIN7
LQFP64
27 23 15
LQFP80
OD
Alternate
function
after
remap
[option bit]
Speed
Main
function Default alternate
(after
function
reset)
Ext. interrupt
Input
wpu
Pin number
STM8AF61xx, STM8AF51xx
Table 6.
Pinouts and pin description
STM8A microcontroller family pin description (continued)
Output
PP
47 38 30 22 PC5/SPI_SCK
I/O X
X
X
O3
X
X Port C5 SPI clock
Speed
X Port C4
High sink
X
floating
HS O3
Pin name
Type
X
LQFP32
X
LQFP48
I/O X
LQFP64
46 37 29 21 PC4/TIM1_CC4
LQFP80
OD
Main
function Default alternate
(after
function
reset)
Ext. interrupt
Input
wpu
Pin number
Alternate
function
after
remap
[option bit]
Timer 1 - channel
4
48 39 31
- VSSIO_2
S
I/O ground
49 40 32
- VDDIO_2
S
I/O power supply
50 41 33 23 PC6/SPI_MOSI
I/O X
X
X
O3
X
X Port C6
SPI master out/
slave in
51 42 34 24 PC7/SPI_MISO
I/O X
X
X
O3
X
X Port C7
SPI master in/
slave out
52 43 35
- PG0/CAN_TX
I/O X
X
O1
X
X Port G0 CAN transmit
53 44 36
- PG1/CAN_RX
I/O X
X
O1
X
X Port G1 CAN receive
54 45
-
- PG2
I/O X
X
O1
X
X Port G2
55 46
-
- PG3
I/O X
X
O1
X
X Port G3
56 47
-
- PG4
I/O X
X
O1
X
X Port G4
57 48
-
- PI0
I/O X
X
O1
X
X Port I0
58
-
-
- PI1
I/O X
X
O1
X
X Port I1
59
-
-
- PI2
I/O X
X
O1
X
X Port I2
60
-
-
- PI3
I/O X
X
O1
X
X Port I3
61
-
-
- PI4
I/O X
X
O1
X
X Port I4
62
-
-
- PI5
I/O X
X
O1
X
X Port I5
63 49
-
- PG5
I/O X
X
O1
X
X Port G5
64 50
-
- PG6
I/O X
X
O1
X
X Port G6
65 51
-
- PG7
I/O X
X
O1
X
X Port G7
66 52
-
- PE4
I/O X
X
X
O1
X
X Port E4
67 53 37
- PE3/TIM1_BKIN
I/O X
X
X
O1
X
X Port E3
68 54 38
- PE2/I2C_SDA
I/O X
X
X
O1 T(1) X Port E2
I2C data
69 55 39
- PE1/I2C_SCL
I/O X
X
X
O1 T(1) X Port E1
I2C clock
70 56 40
- PE0/CLK_CCO
I/O X
X
X
O3
X
X Port E0
Configurable
clock output
71
-
-
- PI6
I/O X
X
O1
X
X Port I6
72
-
-
- PI7
I/O X
X
O1
X
X Port I7
Timer 1 - break
input
31/100
Pinouts and pin description
STM8A microcontroller family pin description (continued)
Alternate
function
after
remap
[option bit]
PP
Main
function Default alternate
(after
function
reset)
OD
Speed
High sink
Output
Ext. interrupt
Pin name
floating
Input
Type
LQFP32
LQFP48
LQFP64
LQFP80
Pin number
wpu
Table 6.
STM8AF61xx, STM8AF51xx
73 57 41 25 PD0/TIM3_CC2
I/O X
X
X
HS O3
X
TIM1_BKIN
Timer 3 - channel [AFR3]/
X Port D0
2
CLK_CCO
[AFR2]
74 58 42 26 PD1/SWIM
I/O X
X
X
HS O4
X
X Port D1
SWIM data
interface
75 59 43 27 PD2/TIM3_CC1
I/O X
X
X
HS O3
X
X Port D2
Timer 3 - channel TIM2_CC3
1
[AFR1]
76 60 44 28 PD3/TIM2_CC2
I/O X
X
X
HS O3
X
X Port D3
Timer 2 - channel ADC_ETR
2
[AFR0]
77 61 45 29
PD4/TIM2_CC1/B
I/O X
EEP
X
X
HS O3
X
X Port D4
BEEP
Timer 2 - channel
output
1
[AFR7]
78 62 46 30
PD5/
LINUART_TX
X
X
O1
X
X Port D5
LINUART data
transmit
Port D6
LINUART data
receive
79 63 47 31
PD6/
LINUART_RX
80 64 48 32 PD7/TLI
I/O X
I/O X
X
X
O1
X
X
Caution: This pin must be held low
during power on
I/O X
X
X
O1
X
X Port D7 Top level interrupt
TIM1_CC4
[AFR4]
1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
6.2.1
Alternate function remapping
As shown in the rightmost column of Table 6, some alternate functions can be remapped at different I/O
ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 10:
Option bytes on page 49. When the remapping option is active, the default alternate function is no longer
available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of
the STM8A microcontroller family reference manual, RM0009).
32/100
STM8AF61xx, STM8AF51xx
7
Memory map
Memory map
Figure 7.
Register and memory map
00 0000
Up to 6 Kbytes RAM
Up to 1 Kbyte stack
00 1800
Reserved
00 4000
Up to 2 Kbytes data EEPROM
00 4800
Option and engineering bytes
00 4900
Reserved
00 5000
HW registers
00 5800
Reserved
00 6000
2 Kbytes ROM
00 6800
00 7F00
CPU registers
00 8000
IT vectors
00 8080
Up to 128 Kbytes code Flash
02 7FFF
Table 7.
Stack and RAM partitioning
Stack size
Product
Kbytes
RAM size
Kbytes
RAM end
128
6
17FF
Stack start
Dec
Hex
1024
0400
1400
33/100
Interrupt table
8
STM8AF61xx, STM8AF51xx
Interrupt table
Table 8.
Priority
34/100
STM8A interrupt table
Source
block
Description
Interrupt vector Wake-up
address
from halt
Yes
Comments
-
Reset
Reset
6000h
Reset vector in ROM
-
TRAP
SW interrupt
8004h
0
TLI
External top level
interrupt
8008h
1
AWU
Auto wake up from
halt
800Ch
2
Clock
controller
Main clock controller
8010h
3
MISC
Ext interrupt E0
8014h
Yes
Port A interrupts
4
MISC
Ext interrupt E1
8018h
Yes
Port B interrupts
5
MISC
Ext interrupt E2
801Ch
Yes
Port C interrupts
6
MISC
Ext interrupt E3
8020h
Yes
Port D interrupts
7
MISC
Ext interrupt E4
8024h
Yes
Port E interrupts
8
CAN
CAN interrupt Rx
8028h
Yes
9
CAN
CAN interrupt
TX/ER/SC
802Ch
10
SPI
End of transfer
8030h
11
Timer 1
Update/overflow/
trigger/break
8034h
12
Timer 1
Capture/compare
8038h
13
Timer 2
Update/overflow/
break
803Ch
14
Timer 2
Capture/compare
8040h
15
Timer 3
Update/overflow/
break
8044h
16
Timer 3
Capture/compare
8048h
17
USART
(SCI1)
Tx complete/
ER/SPI EOT/SPI
error
804Ch
18
USART
(SCI1)
Receive data full reg.
8050h
19
I2C
I2C interrupts
8054h
20
LINUART
(SCI2)
Tx complete/error/
SPI EOT/SPI error
8058h
21
LINUART
(SCI2)
Receive data full reg.
805Ch
Yes
Yes
Trigger not available on
medium end timer
Trigger not available on
medium end timer
Yes
STM8AF61xx, STM8AF51xx
Table 8.
Priority
Interrupt table
STM8A interrupt table (continued)
Source
block
Description
Interrupt vector Wake-up
address
from halt
22
ADC
End of conversion
8060h
23
Timer 4
Update/overflow
8064h
24
Reserved(1)
Reserved
8068h
Comments
1. Also unused interrupts should be initialised with “IRET” for robust programming.
35/100
Register mapping
9
Register mapping
Table 9.
STM8A I/O port hardware register map
Register label
Register name
Reset
status
00 5000h
PA_ODR
Port A data output latch register
00h
00 5001h
PA_IDR
Port A input pin value register
00h
PA_DDR
Port A data direction register
00h
00 5003h
PA_CR1
Port A control register 1
00h
00 5004h
PA_CR2
Port A control register 2
00h
00 5005h
PB_ODR
Port B data output latch register
00h
00 5006h
PB_IDR
Port B input pin value register
00h
PB_DDR
Port B data direction register
00h
00 5008h
PB_CR1
Port B control register 1
00h
00 5009h
PB_CR2
Port B control register 2
00h
00 500Ah
PC_ODR
Port C data output latch register
00h
00 500Bh
PC_IDR
Port C input pin value register
00h
PC_DDR
Port C data direction register
00h
00 500Dh
PC_CR1
Port C control register 1
00h
00 500Eh
PC_CR2
Port C control register 2
00h
00 500Fh
PD_ODR
Port D data output latch register
00h
00 5010h
PD_IDR
Port D input pin value register
00h
PD_DDR
Port D data direction register
00h
00 5012h
PD_CR1
Port D control register 1
00h
00 5013h
PD_CR2
Port D control register 2
00h
00 5014h
PE_ODR
Port E data output latch register
00h
00 5015h
PE_IDR
Port E input pin value register
00h
PE_DDR
Port E data direction register
00h
00 5017h
PE_CR1
Port E control register 1
00h
00 5018h
PE_CR2
Port E control register 2
00h
00 5019h
PF_ODR
Port F data output latch register
00h
00 501Ah
PF_IDR
Port F input pin value register
00h
PF_DDR
Port F data direction register
00h
00 501Ch
PF_CR1
Port F control register 1
00h
00 501Dh
PF_CR2
Port F control register 2
00h
Address
00 5002h
00 5007h
00 500Ch
00 5011h
00 5016h
00 501Bh
36/100
STM8AF61xx, STM8AF51xx
Block
Port A
Port B
Port C
Port D
Port E
Port F
STM8AF61xx, STM8AF51xx
Table 9.
Register mapping
STM8A I/O port hardware register map (continued)
Register label
Register name
Reset
status
00 501Eh
PG_ODR
Port G data output latch register
00h
00 501Fh
PG_IDR
Port G input pin value register
00h
PG_DDR
Port G data direction register
00h
00 5021h
PG_CR1
Port G control register 1
00h
00 5022h
PG_CR2
Port G control register 2
00h
00 5023h
PH_ODR
Port H data output latch register
00h
00 5024h
PH_IDR
Port H input pin value register
00h
PH_DDR
Port H data direction register
00h
00 5026h
PH_CR1
Port H control register 1
00h
00 5027h
PH_CR2
Port H control register 2
00h
00 5028h
PI_ODR
Port I data output latch register
00h
00 5029h
PI_IDR
Port I input pin value register
00h
PI_DDR
Port I data direction register
00h
00 502Bh
PI_CR1
Port I control register 1
00h
00 502Ch
PI_CR2
Port I control register 2
00h
Address
00 5020h
00 5025h
00 502Ah
Block
Port G
Port H
Port I
37/100
Register mapping
Table 10.
Address
STM8AF61xx, STM8AF51xx
STM8A general hardware register map
Block
Register label
00 5050h
to
00 5059h
Register name
Reset
status
Reserved area (10 bytes)
00 505Ah
FLASH_CR1
Flash control register 1
00h
00 505Bh
FLASH_CR2
Flash control register 2
00h
FLASH_NCR2
Flash complementary control register 2
FFh
FLASH _FPR
Flash protection register
00h
00 505Eh
FLASH _NFPR
Flash complementary protection register
FFh
00 505Fh
FLASH _IAPSR
Flash in-application programming status
register
00h
00 505Ch
00 505Dh
Flash
00 5060h
to
00 5061h
00 5062h
Reserved area (2 bytes)
Flash
Flash program memory unprotection
register
FLASH _PUKR
00 5063h
00 5064h
00h
Reserved area (1 byte)
Flash
FLASH _DUKR
00 5065h
to
00 509Fh
Data EEPROM unprotection register
00h
Reserved area (59 bytes)
00 50A0h
EXTI_CR1
External interrupt control register 1
00h
EXTI_CR2
External interrupt control register 2
00h
ITC
00 50A1h
00 50A2h
to
00 50B2h
00 50B3h
Reserved area (17 bytes)
RST
RST_SR
00 50B4h
to
00 50BFh
Reset status register
xxh
Reserved area (12 bytes)
00 50C0h
CLK_ICKR
Internal clock control register
01h
CLK_ECKR
External clock control register
00h
CLK
00 50C1h
00 50C2h
38/100
Reserved area (1 byte)
STM8AF61xx, STM8AF51xx
Table 10.
Register mapping
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 50C3h
CLK_CMSR
Clock master status register
E1h
00 50C4h
CLK_SWR
Clock master switch register
E1h
00 50C5h
CLK_SWCR
Clock switch control register
xxxx
0000b
00 50C6h
CLK_CKDIVR
Clock divider register
18h
CLK_PCKENR1
Peripheral clock gating register 1
FFh
CLK_CSSR
Clock security system register
00h
00 50C9h
CLK_CCOR
Configurable clock control register
00h
00 50CAh
CLK_PCKENR2
Peripheral clock gating register 2
FFh
00 50CBh
CLK_CANCCR
CAN clock control register
00h
00 50CCh
CLK_HSITRIMR
HSI clock calibration trimming register
xxh
00 50CDh
CLK_SWIMCCR
SWIM clock control register
x0h
Address
Block
00 50C7h
00 50C8h
CLK
00 50CEh
to
00 50D0h
Reserved area (3 bytes)
00 50D1h
WWDG_CR
WWDG control register
7Fh
WWDG_WR
WWDR window register
7Fh
WWDG
00 50D2h
00 50D3h
to
00 50DFh
Reserved area (13 bytes)
00 50E0h
00 50E1h
IWDG
00 50E2h
IWDG_KR
IWDG key register
-
IWDG_PR
IWDG prescaler register
00h
IWDG_RLR
IWDG reload register
FFh
00 50E3h
to
00 50EFh
Reserved area (13 bytes)
00 50F0h
00 50F1h
AWU
00 50F2h
00 50F3h
00 50F4h
to
00 50FFh
BEEP
AWU_CSR1
AWU control/status register 1
00h
AWU_APR
AWU asynchronous prescaler buffer
register
3Fh
AWU_TBR
AWU timebase selection register
00h
BEEP_CSR
BEEP control/status register
1Fh
Reserved area (12 bytes)
39/100
Register mapping
Table 10.
STM8AF61xx, STM8AF51xx
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5200h
SPI_CR1
SPI control register 1
00h
00 5201h
SPI_CR2
SPI control register 2
00h
00 5202h
SPI_ICR
SPI interrupt control register
00h
SPI_SR
SPI status register
02h
00 5204h
SPI_DR
SPI data register
00h
00 5205h
SPI_CRCPR
SPI CRC polynomial register
07h
00 5206h
SPI_RXCRCR
SPI Rx CRC register
FFh
00 5207h
SPI_TXCRCR
SPI Tx CRC register
FFh
Address
Block
00 5203h
SPI
00 5208h
to
00 520Fh
Reserved area (8 bytes)
I2C control register 1
I2C_CR1
00 5210h
00 5211h
2C
I2C_CR2
00h
frequency register
00h
00 5212h
I2C_FREQR
00 5213h
I2C_OARL
I2C own address register low
00h
I2C_OARH
2C
00h
00 5214h
I
I
own address register high
00 5215h
Reserved
00 5216h
00 5217h
00 5218h
00 5219h
I2C
I2C_DR
I2C data register
00h
I2C_SR1
I2C status register 1
00h
I2C_SR2
2C
I
status register 2
00h
I2C_SR3
I2C
status register 3
00h
interrupt control register
00h
2C
00 521Ah
I2C_ITR
00 521Bh
I2C_CCRL
I2C clock control register low
00h
I2C_CCRH
I2C
00h
00 521Ch
00 521Dh
00 521Eh
00 521Fh
to
00 522Fh
40/100
control register 2
I
2C
00h
I
2
I C TRISE register
I2C_TRISER
I2C_PECR
clock control register high
2C
I
packet error checking register
Reserved area (17 bytes)
02h
00h
STM8AF61xx, STM8AF51xx
Table 10.
Register mapping
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5230h
USART_SR
USART status register
C0h
00 5231h
USART_DR
USART data register
xxh
00 5232h
USART_BRR1
USART baud rate register 1
00h
00 5233h
USART_BRR2
USART baud rate register 2
00h
00 5234h
USART_CR1
USART control register 1
00h
USART_CR2
USART control register 2
00h
00 5236h
USART_CR3
USART control register 3
00h
00 5237h
USART_CR4
USART control register 4
00h
00 5238h
USART_CR5
USART control register 5
00h
00 5239h
USART_GTR
USART guard time register
00h
00 523Ah
USART_PSCR
USART prescaler register
00h
Address
00 5235h
Block
USART
00 523Bh
to
00 523Fh
Reserved area (5 bytes)
00 5240h
LINUART_SR
LINUART status register
C0h
00 5241h
LINUART_DR
LINUART data register
xxh
00 5242h
LINUART_BRR1
LINUART baud rate register 1
00h
00 5243h
LINUART_BRR2
LINUART baud rate register 2
00h
00 5244h
LINUART_CR1
LINUART control register 1
00h
LINUART_CR2
LINUART control register 2
00h
00 5246h
LINUART_CR3
LINUART control register 3
00h
005247h
LINUART_CR4
LINUART control register 4
00h
00 5245h
LINUART
00 5248h
00 5249h
00 524Ah
to
00 524Fh
Reserved
LINUART_CR6
LINUART control register 6
00h
Reserved area (6 bytes)
41/100
Register mapping
Table 10.
STM8AF61xx, STM8AF51xx
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5250h
TIM1_CR1
TIM1 control register 1
00h
00 5251h
TIM1_CR2
TIM1 control register 2
00h
00 5252h
TIM1_SMCR
TIM1 slave mode control register
00h
00 5253h
TIM1_ETR
TIM1 external trigger register
00h
00 5254h
TIM1_IER
TIM1 interrupt enable register
00h
00 5255h
TIM1_SR1
TIM1 status register 1
00h
00 5256h
TIM1_SR2
TIM1 status register 2
00h
00 5257h
TIM1_EGR
TIM1 event generation register
00h
00 5258h
TIM1_CCMR1
TIM1 capture/compare mode register 1
00h
00 5259h
TIM1_CCMR2
TIM1 capture/compare mode register 2
00h
00 525Ah
TIM1_CCMR3
TIM1 capture/compare mode register 3
00h
00 525Bh
TIM1_CCMR4
TIM1 capture/compare mode register 4
00h
00 525Ch
TIM1_CCER1
TIM1 capture/compare enable register 1
00h
00 525Dh
TIM1_CCER2
TIM1 capture/compare enable register 2
00h
00 525Eh
TIM1_CNTRH
TIM1 counter high
00h
TIM1_CNTRL
TIM1 counter low
00h
00 5260h
TIM1_PSCRH
TIM1 prescaler register high
00h
00 5261h
TIM1_PSCRL
TIM1 prescaler register low
00h
00 5262h
TIM1_ARRH
TIM1 auto-reload register high
FFh
00 5263h
TIM1_ARRL
TIM1 auto-reload register low
FFh
00 5264h
TIM1_RCR
TIM1 repetition counter register
00h
00 5265h
TIM1_CCR1H
TIM1 capture/compare register 1 high
00h
00 5266h
TIM1_CCR1L
TIM1 capture/compare register 1 low
00h
00 5267h
TIM1_CCR2H
TIM1 capture/compare register 2 high
00h
00 5268h
TIM1_CCR2L
TIM1 capture/compare register 2 low
00h
00 5269h
TIM1_CCR3H
TIM1 capture/compare register 3 high
00h
00 526Ah
TIM1_CCR3L
TIM1 capture/compare register 3 low
00h
00 526Bh
TIM1_CCR4H
TIM1 capture/compare register 4 high
00h
00 526Ch
TIM1_CCR4L
TIM1 capture/compare register 4 low
00h
00 526Dh
TIM1_BKR
TIM1 break register
00h
00 526Eh
TIM1_DTR
TIM1 dead-time register
00h
00 526Fh
TIM1_OISR
TIM1 output idle state register
00h
Address
Block
00 525Fh
TIM1
00 5270h
to
00 52FFh
42/100
Reserved area (147 bytes)
STM8AF61xx, STM8AF51xx
Table 10.
Register mapping
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5300h
TIM2_CR1
TIM2 control register 1
00h
00 5301h
TIM2_IER
TIM2 interrupt enable register
00h
00 5302h
TIM2_SR1
TIM2 status register 1
00h
00 5303h
TIM2_SR2
TIM2 status register 2
00h
00 5304h
TIM2_EGR
TIM2 event generation register
00h
00 5305h
TIM2_CCMR1
TIM2 capture/compare mode register 1
00h
00 5306h
TIM2_CCMR2
TIM2 capture/compare mode register 2
00h
00 5307h
TIM2_CCMR3
TIM2 capture/compare mode register 3
00h
00 5308h
TIM2_CCER1
TIM2 capture/compare enable register 1
00h
00 5309h
TIM2_CCER2
TIM2 capture/compare enable register 2
00h
TIM2_CNTRH
TIM2 counter high
00h
00 530Bh
TIM2_CNTRL
TIM2 counter low
00h
00 530Ch
TIM2_PSCR
TIM2 prescaler register
00h
00 530Dh
TIM2_ARRH
TIM2 auto-reload register high
FFh
00 530Eh
TIM2_ARRL
TIM2 auto-reload register low
FFh
00 530Fh
TIM2_CCR1H
TIM2 capture/compare register 1 high
00h
00 5310h
TIM2_CCR1L
TIM2 capture/compare register 1 low
00h
00 5311h
TIM2_CCR2H
TIM2 capture/compare register 2 high
00h
00 5312h
TIM2_CCR2L
TIM2 capture/compare register 2 low
00h
00 5313h
TIM2_CCR3H
TIM2 capture/compare register 3 high
00h
00 5314h
TIM2_CCR3L
TIM2 capture/compare register 3 low
00h
Address
00 530Ah
00 5315h
to
00 531Fh
Block
TIM2
Reserved area (11 bytes)
43/100
Register mapping
Table 10.
STM8AF61xx, STM8AF51xx
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5320h
TIM3_CR1
TIM3 control register 1
00h
00 5321h
TIM3_IER
TIM3 interrupt enable register
00h
00 5322h
TIM3_SR1
TIM3 status register 1
00h
00 5323h
TIM3_SR2
TIM3 status register 2
00h
00 5324h
TIM3_EGR
TIM3 event generation register
00h
00 5325h
TIM3_CCMR1
TIM3 capture/compare mode register 1
00h
00 5326h
TIM3_CCMR2
TIM3 capture/compare mode register 2
00h
00 5327h
TIM3_CCER1
TIM3 capture/compare enable register 1
00h
TIM3_CNTRH
TIM3 counter high
00h
00 5329h
TIM3_CNTRL
TIM3 counter low
00h
00 532Ah
TIM3_PSCR
TIM3 prescaler register
00h
00 532Bh
TIM3_ARRH
TIM3 auto-reload register high
FFh
00 532Ch
TIM3_ARRL
TIM3 auto-reload register low
FFh
00 532Dh
TIM3_CCR1H
TIM3 capture/compare register 1 high
00h
00 532Eh
TIM3_CCR1L
TIM3 capture/compare register 1 low
00h
00 532Fh
TIM3_CCR2H
TIM3 capture/compare register 2 high
00h
00 5330h
TIM3_CCR2L
TIM3 capture/compare register 2 low
00h
Address
00 5328h
Block
TIM3
00 5331h
to
00 533Fh
00 5340h
TIM4_CR1
TIM4 control register 1
00h
00 5341h
TIM4_IER
TIM4 interrupt enable register
00h
00 5342h
TIM4_SR
TIM4 status register
00h
TIM4_EGR
TIM4 event generation register
00h
00 5344h
TIM4_CNTR
TIM4 counter
00h
00 5345h
TIM4_PSCR
TIM4 prescaler register
00h
00 5346h
TIM4_ARR
TIM4 auto-reload register
FFh
00 5343h
00 5347h
to
00 53FFh
44/100
Reserved area (15 bytes)
TIM4
Reserved area (184 bytes)
STM8AF61xx, STM8AF51xx
Table 10.
Register mapping
STM8A general hardware register map (continued)
Register label
Register name
Reset
status
00 5400h
ADC _CSR
ADC control/status register
00h
00 5401h
ADC_CR1
ADC configuration register 1
00h
00 5402h
ADC_CR2
ADC configuration register 2
00h
ADC_CR3
ADC configuration register 3
00h
00 5404h
ADC_DRH
ADC data register high
00h
00 5405h
ADC_DRL
ADC data register low
00h
00 5406h
ADC_TDRH
ADC Schmitt trigger disable register high
00h
00 5407h
ADC_TDRL
ADC Schmitt trigger disable register low
00h
Address
Block
00 5403h
ADC
00 5408h
to
00 541Fh
Reserved area (24 bytes)
00 5420h
CAN_MCR
CAN master control register
02h
00 5421h
CAN_MSR
CAN master status register
02h
00 5422h
CAN_TSR
CAN transmit status register
00h
00 5423h
CAN_TPR
CAN transmit priority register
0Ch
00 5424h
CAN_RFR
CAN receive FIFO register
00h
00 5425h
CAN_IER
CAN interrupt enable register
00h
00 5426h
CAN_DGR
CAN diagnosis register
0Ch
00 5427h
CAN_FPSR
CAN page selection register
00h
00 5428h
CAN_P0
CAN paged register 0
00h
00 5429h
CAN_P1
CAN paged register 1
00h
00 542Ah
CAN_P2
CAN paged register 2
00h
CAN_P3
CAN paged register 3
00h
00 542Ch
CAN_P4
CAN paged register 4
00h
00 542Dh
CAN_P5
CAN paged register 5
00h
00 542Eh
CAN_P6
CAN paged register 6
00h
00 542Fh
CAN_P7
CAN paged register 7
00h
00 5430h
CAN_P8
CAN paged register 8
00h
00 5431h
CAN_P9
CAN paged register 9
00h
00 5432h
CAN_PA
CAN paged register A
00h
00 5433h
CAN_PB
CAN paged register B
00h
00 5434h
CAN_PC
CAN paged register C
00h
00 5435h
CAN_PD
CAN paged register D
00h
00 5436h
CAN_PE
CAN paged register E
00h
00 5437h
CAN_PF
CAN paged register F
00h
00 542Bh
CAN
45/100
Register mapping
Table 10.
Address
STM8AF61xx, STM8AF51xx
STM8A general hardware register map (continued)
Block
Register label
00 5438h to
00 57FFh
Reset
status
Reserved area (968 bytes)
5800h
TU_KEYS_REG0
TMU key register 0 [7:0]
00h
5801h
TU_KEYS_REG1
TMU key register 1 [7:0]
00h
5802h
TU_KEYS_REG2
TMU key register 2 [7:0]
00h
5803h
TU_KEYS_REG3
TMU key register 3 [7:0]
00h
TU_KEYS_REG4
TMU key register 4 [7:0]
00h
5805h
TU_KEYS_REG5
TMU key register 5 [7:0]]
00h
5806h
TU_KEYS_REG6
TMU key register 6 [7:0]
00h
5807h
TU_KEYS_REG7
TMU key register 7 [7:0]
00h
5808h
TU_CTL_ST
TMU control and status register
00h
5804h
46/100
Register name
TMU
STM8AF61xx, STM8AF51xx
Table 11.
Register mapping
CPU/SWIM/debug module/interrupt controller registers
Register label
Register name
Reset
status
00 7F00h
A
Accumulator
00h
00 7F01h
PCE
Program counter extended
00h
00 7F02h
PCH
Program counter high
60h
00 7F03h
PCL
Program counter low
00h
00 7F04h
XH
X index register high
00h
XL
X index register low
00h
00 7F06h
YH
Y index register high
00h
00 7F07h
YL
Y index register low
00h
00 7F08h
SPH
Stack pointer high
17h
00 7F09h
SPL
Stack pointer low
FFh
00 7F0Ah
CCR
Condition code register
28h
Address
Block
00 7F05h
CPU
00 7F0Bh to
00 7F5Fh
00 7F60h
Reserved area (85 bytes)
CFG_GCR
Global configuration register
00h
00 7F70h
ITC_SPR1
Interrupt software priority register 1
FFh
00 7F71h
ITC_SPR2
Interrupt software priority register 2
FFh
00 7F72h
ITC_SPR3
Interrupt software priority register 3
FFh
ITC_SPR4
Interrupt software priority register 4
FFh
00 7F74h
ITC_SPR5
Interrupt software priority register 5
FFh
00 7F75h
ITC_SPR6
Interrupt software priority register 6
FFh
00 7F76h
ITC_SPR7
Interrupt software priority register 7
FFh
00 7F73h
CFG
ITC
00 7F77h
to
00 7F79h
00 7F80h
00 7F81h
to
00 7F8Fh
Reserved area (3 bytes)
SWIM
SWIM_CSR
SWIM control status register
00h
Reserved area (15 bytes)
47/100
Register mapping
Table 11.
CPU/SWIM/debug module/interrupt controller registers (continued)
Register label
Register name
Reset
status
00 7F90h
DM_BK1RE
DM breakpoint 1 register extended byte
FFh
00 7F91h
DM_BK1RH
DM breakpoint 1 register high byte
FFh
00 7F92h
DM_BK1RL
DM breakpoint 1 register low byte
FFh
00 7F93h
DM_BK2RE
DM breakpoint 2 register extended byte
FFh
00 7F94h
DM_BK2RH
DM breakpoint 2 register high byte
FFh
DM_BK2RL
DM breakpoint 2 register low byte
FFh
00 7F96h
DM_CR1
Debug module control register 1
00h
00 7F97h
DM_CR2
Debug module control register 2
00h
00 7F98h
DM_CSR1
Debug module control/status register 1
10h
00 7F99h
DM_CSR2
Debug module control/status register 2
00h
00 7F9Ah
DM_ENFCTR
DM enable function register
FFh
Address
00 7F95h
00 7F9Bh
to
00 7F9Fh
48/100
STM8AF61xx, STM8AF51xx
Block
DM
Reserved area (5 bytes)
STM8AF61xx, STM8AF51xx
10
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory protection of the
device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection)
byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one
(NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in
Table 12: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP and UBC
options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and
debug modulel user manual (UM0470) for information on SWIM programming procedures.
Table 12.
Addr.
Option bytes
Option
name
Option
byte no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
Read-out
4800h protection OPT0
(ROP)
ROP[7:0]
00h
4801h
UBC[7:0]
00h
NUBC[7:0]
FFh
User
OPT1
boot code
4802h (UBC)
NOPT1
4803h Alternate
function
4804h remappin
g (AFR)
OPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
NOPT2
NAFR
7
NAFR
NAFR5
6
4805h
OPT3
NAFR4
NAFR3
NAFR2
NAFR1 NAFR0
FFh
Reserved
LSI
_EN
IWDG
_HW
WWDG WWDG
_HW
_HALT
00h
4806h
NOPT3
Reserved
NLSI
_EN
NIWDG NWWD NWWG
_HW
G_HW _HALT
FFh
4807h
OPT4
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
00h
4808h
NOPT4
Reserved
NEXT
CLK
NCKAW
USEL
NPR
SC1
NPR
SC0
FFh
4809h HSE
clock
480Ah startup
OPT5
NOPT5
480Bh
OPT6
Watchdog
option
Clock
option
AFR1
AFR0
00h
HSECNT[7:0]
00h
NHSECNT[7:0]
FFh
TMU[0:3]
00h
NTMU[0:3]
FFh
TMU
480Ch
NOPT6
480Dh
OPT7
Reserved
WAIT
STATE
00h
NOPT7
Reserved
NWAIT
STATE
FFh
Flash wait
states
480Eh
480Fh
Reserved
49/100
Option bytes
Table 12.
Addr.
STM8AF61xx, STM8AF51xx
Option bytes (continued)
Option
name
Option
byte no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
4810h
OPT8
TMU_KEY 0 [7:0]
00h
4811h
OPT9
TMU_KEY 1 [7:0]
00h
4812h
OPT10
TMU_KEY 2 [7:0]
00h
4813h
OPT11
TMU_KEY 3 [7:0]
00h
OPT12
TMU_KEY 4 [7:0]
00h
4815h
OPT13
TMU_KEY 5 [7:0]
00h
4816h
OPT14
TMU_KEY 6 [7:0]
00h
4817h
OPT15
TMU_KEY 7 [7:0]
00h
4818h
OPT16
TMU MAX_ATT [7:0]
00h
4814h
TMU
4819h
to
487D
487E
487F
50/100
Reserved
Bootloader
OPT17
NOPT17
BL_EN [7:0]
00h
NBL_EN [7:0]
00h
STM8AF61xx, STM8AF51xx
Table 13.
Option bytes
Option byte description
Option byte no.
Description
OPT0
ROP[7:0]: Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the STM8A microcontroller family reference manual
(RM0009) section on Flash/EEPROM memory readout protection for
details.
OPT1
UBC[7:0]: User boot code area
00h: No UBC, no write-protection
01h: Page 0 to 1 defined as UBC, memory write-protected
02h: Page 0 to 3 defined as UBC, memory write-protected
03h to FFh: Pages 4 to 255 defined as UBC, memory write-protected
Note: Refer to the STM8A microcontroller family reference manual
(RM0009) section on Flash/EEPROM write protection for more details.
OPT2
AFR7: Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CC1
1: Port D4 alternate function = BEEP
AFR6: Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL.
AFR5: Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate
function = TIM1_NCC1.
AFR4: Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Port D7 alternate function = TIM1_CC4
AFR3: Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CC2
1: Port D0 alternate function = TIM1_BKIN
AFR2: Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CC2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1: Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CC3, port D2 alternate function
TIM3_CC1.
1: Port A3 alternate function = TIM3_CC1, port D2 alternate function
TIM2_CC3.
AFR0: Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CC2
1: Port D3 alternate function = ADC_ETR
51/100
Option bytes
STM8AF61xx, STM8AF51xx
Table 13.
Option byte description (continued)
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0]: AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
52/100
OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles.
OPT6
TMU[3:0]: Enable temporary memory unprotection
0101: Read-out protection can be temporary disabled using a key
sequence.
Any other value: Permanent ROP
OPT7
WAIT STATE: Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
0: No wait state
1: One wait state
OPT8
TMU_KEY 0 [7:0]: Temporary unprotection key 0
Temporary unprotection key: Must be different from 00h or FFh
OPT9
TMU_KEY 1 [7:0]: Temporary unprotection key 1
Temporary unprotection key: Must be different from 00h or FFh
OPT10
TMU_KEY 2 [7:0]: Temporary unprotection key 2
Temporary unprotection key: Must be different from 00h or FFh
OPT11
TMU_KEY 3 [7:0]: Temporary unprotection key 3
Temporary unprotection key: Must be different from 00h or FFh
STM8AF61xx, STM8AF51xx
Table 13.
Option bytes
Option byte description (continued)
Option byte no.
Description
OPT12
TMU_KEY 4 [7:0]: Temporary unprotection key 4
Temporary unprotection key: Must be different from 00h or FFh
OPT13
TMU_KEY 5 [7:0]: Temporary unprotection key 5
Temporary unprotection key: Must be different from 00h or FFh
OPT14
TMU_KEY 6 [7:0]: Temporary unprotection key 6
Temporary unprotection key: Must be different from 00h or FFh
OPT15
TMU_KEY 7 [7:0]: Temporary unprotection key 7
Temporary unprotection key: Must be different from 00h or FFh
OPT16
TMU_MAXATT [7:0]: TMU access failure counter
Every unsuccessful trial to enter the temporary unprotection procedure
increments the counter. More than eight unsuccessful trials trigger the
global erase of the code and data memory.
OPT17
BL_EN [7:0]: Bootloader enable
If this optionbyte is set to 55h (complementary value AAh) the bootloader
program is activated also in case of a programmed code memory
(for more details, see the bootloader user manual, UM0500).
53/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
11
Electrical characteristics
11.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
11.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
11.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.
11.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
11.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Figure 8.
Pin loading conditions
STM8A pin
50 pF
54/100
STM8AF61xx, STM8AF51xx
11.1.5
Electrical characteristics
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 9.
Pin input voltage
STM8A pin
VIN
11.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 14.
Symbol
VDDx - VSS
VIN
Voltage characteristics
Ratings
Min
Max
-0.3
6.5
Input voltage on true open drain pins (PE1, PE2)(2)
VSS - 0.3
6.5
Input voltage on any other pin(2)
VSS - 0.3
VDD + 0.3
Supply voltage (including VDDA and VDDIO)(1)
|VDDx - VSS| Variations between different power pins
50
|VSSx - VSS| Variations between all the different ground pins
50
VESD
Electrostatic discharge voltage
Unit
V
mV
see Absolute maximum
ratings (electrical
sensitivity) on page 86
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
55/100
Electrical characteristics
Table 15.
STM8AF61xx, STM8AF51xx
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power lines (source)(1)(2)
60
IVSS
Total current out of VSS ground lines (sink)(1)(2)
60
Output current sunk by any I/O and control pin
20
Output current source by any I/Os and control pin
- 20
Injected current on NRST pin
± 10
Injected current on OSCIN pin
± 10
Injected current on any other pin
± 10
Total injected current (sum of all I/O and control pins)
± 20
IIO
IINJ(PIN)(3)
ΣIINJ(PIN)(4)
Unit
mA
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. The total limit applies to the sum of operation and injected currents.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current allowed and the corresponding VIN maximum must always be
respected.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the sum of the absolute
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 16.
56/100
Thermal characteristics
Symbol
Ratings
Value
TSTG
Storage temperature range
-65 to +150
TJ
Maximum junction temperature
150
Unit
°C
STM8AF61xx, STM8AF51xx
11.3
Electrical characteristics
Operating conditions
Table 17.
General operating conditions
Symbol
Parameter
fCPU
Internal CPU clock frequency
Conditions
Min
Max
TA ≤105 °C
0
24
TA > 105 °C
0
16
3.0
5.5
V
Suffix A
-40
85
°C
Suffix B
-40
105
°C
Suffix C
-40
125
°C
Suffix D
-40
145
°C
A suffix version
-40
90
°C
B suffix version
-40
110
°C
C suffix version
-40
130
°C
D suffix version
-40
150
°C
MHz
VDD/VDD_IO Standard operating voltage
TA
TJ
Unit
Ambient temperature
Junction temperature range
Figure 10. fCPUmax versus VDD
fCPU [MHz]
24
Functionality
not guaranteed
in this area
Functionality guaranteed
@ TA -40 to 105 ¬×
16
Functionality
guaranteed
@ TA -40 to 125 ¬×
12
8
4
0
3.0
4.0
5.0
5.5
Supply voltage [V]
57/100
Electrical characteristics
Table 18.
Symbol
tVDD
tTEMP
STM8AF61xx, STM8AF51xx
Operating conditions at power-up/power-down
Parameter
Conditions
Min
Typ
Max
VDD rise time rate
20(1)
∞
VDD fall time rate(3)
20(2)
∞
Unit
µs/V
Reset release
delay
VDD rising
TBD(2)
3
ms
Reset generation
delay(3)
VDD falling
TBD(2)
3
µs
VIT+
Power-on reset
threshold
2.65
2.8
2.95
V
VIT-
Brown-out reset
threshold
2.58
2.73
2.88
V
VHYS(BOR)
Brown-out reset
hysteresis
70(1)
mV
1. Guaranteed by design, not tested in production
2. TBD = To be determined
3. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum operating voltage (VDD min) when the tTEMP delay has elapsed.
11.3.1
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 54 and Figure 9 on
page 55.
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Note on the run-current typical and worst-case values
58/100
●
Typical device currents values are representative of an application set-up without any
I/O activity at 25 °C. The worst case values correspond to the actual test-limits and
include both internal and external device I/O current.
●
During the execution of an actual application program, the number of read access
cycles to the code memory depends on its structure. A code doing arithmetical
calculations reads the memory less frequently than programs with jump, loop or data
manipulation instructions. The fast-reading access in a Flash memory needs much
more power compared to a RAM. Consequently, the run-current for EEPROM
execution depends strongly on the actual application code structure. The
measurements in the tables below were made using a short, representative code with
move, jump and arithmetic operations. The worst case, an infinite loop of ‘while’
instructions takes approximately 25 % more power. For RAM execution, such power to
program structure relations has not been observed.
STM8AF61xx, STM8AF51xx
Table 19.
Symbol
IDD(RUN)
IDD(RUN)
IDD(RUN)
Electrical characteristics
Total current consumption in run, wait and slow mode at VDD = 5.0 V
Parameter
Supply
current in
run mode
Supply
current in
run mode
Supply
current in
run mode
Conditions
Typ
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
4.4
HSE external clock
fCPU = fMASTER = 24 MHz
3.8
HSE Crystal oscillator
All peripherals off, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from RAM
fCPU = fMASTER = 16 MHz
mA
2.7
2.55
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.2
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
11.4
HSE external clock
fCPU = fMASTER = 24 MHz
10.8
6.0(1)
9.0
mA
8.35
HSI internal RC
fCPU = fMASTER = 16 MHz
8.2
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.9
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
6.9
HSE external clock
fCPU = fMASTER = 24 MHz
6.3
HSE Crystal oscillator
All peripherals on, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from RAM
fCPU = fMASTER = 16 MHz
Unit
3.3
HSI internal RC
fCPU = fMASTER = 16 MHz
HSE Crystal oscillator
All peripherals off, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from EEPROM
fCPU = fMASTER = 16 MHz
Max
15.0(1)
4.3
mA
3.7
HSI internal RC
fCPU = fMASTER = 16 MHz
3.5
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.2
8.0(1)
59/100
Electrical characteristics
Table 19.
Symbol
IDD(RUN)
IDD(WFI)
STM8AF61xx, STM8AF51xx
Total current consumption in run, wait and slow mode at VDD = 5.0 V
Parameter
Supply
current in
run mode
Supply
current in
wait mode
Supply
IDD(SLOW) current in
slow mode
Conditions
Typ
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
13.9
HSE external clock
fCPU = fMASTER = 24 MHz
13.3
HSE Crystal oscillator
All peripherals on, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from EEPROM
fCPU = fMASTER = 16 MHz
CPU not clocked,
all peripherals off
60/100
9.35
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
2.1
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
2.4
HSE external clock
fCPU = fMASTER = 24 MHz
1.8
HSE Crystal oscillator
fCPU = fMASTER = 16 MHz
2.0
mA
HSE external clock
fCPU = fMASTER = 16 MHz
1.38
HSI internal RC
fCPU = fMASTER = 16 MHz
1.21
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.05
HSE external clock 16 MHz/128
fCPU = fMASTER = 0.125 MHz
1.15
fCPU scaled down,
all peripherals off, HSI internal RC 16 MHz/128
fCPU = fMASTER = 0.125 MHz
code executed
from EEPROM
LSI internal RC 128 kHz
fCPU = fMASTER = 0.128 MHz
1. Prodution test limits
mA
9.2
HSE external clock 16 MHz/128
fCPU = fMASTER = 0.125 MHz
Unit
10.0
HSI internal RC
fCPU = fMASTER = 16 MHz
fCPU scaled down,
all peripherals off, HSI internal RC 16 MHz/128
fCPU = fMASTER = 0.125 MHz
code executed
from RAM
LSI internal RC 128 kHz
fCPU = fMASTER = 0.128 MHz
Max
4.0(1)
4.0(1)
1.04
0.5
mA
1.21
1.09
0.56
STM8AF61xx, STM8AF51xx
Table 20.
Electrical characteristics
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 5.0 V
Symbol
Parameter
IDD(H)
Supply current in halt mode
IDD(FAH)
Supply current in fast active halt
mode
Conditions
IDD(SAH)
Supply current in slow active halt
mode
tWU(FAH)
Wake-up time from fast active halt
mode to run mode
tWU(SAH)
Wake-up time from slow active
halt mode to run mode
Typ
Max
Flash powered down
6.5
10(1)
Flash in stand-by mode
64
Crystal osc 16 MHz/128
1050
HSE osc 16 MHz/128
490
LSI RC 128 kHz
150
200(1)
LSI RC 128 kHz
11
30(1)
Unit
µA
2(2)
µs
(2)
100
1. Maximum values at 55 °C, tested in production according to the actual product temperature ranges.
2. Data based on characterization results, not tested in production.
Table 21.
Symbol
IDD(RUN)
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter
Supply
current in
run mode
Conditions
Typ
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
4
HSE external clock
fCPU = fMASTER = 24 MHz
3.8
HSE Crystal oscillator
All peripherals off, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from RAM
fCPU = fMASTER = 16 MHz
Max
Unit
2.9
mA
2.7
HSI internal RC
fCPU = fMASTER = 16 MHz
2.55
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.2
61/100
Electrical characteristics
Table 21.
Symbol
IDD(RUN)
IDD(RUN)
IDD(RUN)
62/100
STM8AF61xx, STM8AF51xx
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter
Supply
current in
run mode
Supply
current in
run mode
Supply
current in
run mode
Conditions
Typ
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
11.0
HSE external clock
fCPU = fMASTER = 24 MHz
10.8
HSE Crystal oscillator
All peripherals off, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from EEPROM
fCPU = fMASTER = 16 MHz
mA
8.35
8.2
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.6
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
6.5
HSE external clock
fCPU = fMASTER = 24 MHz
6.3
3.9
mA
3.7
HSI internal RC
fCPU = fMASTER = 16 MHz
3.55
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.4
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
13.5
HSE external clock
fCPU = fMASTER = 24 MHz
13.3
HSE Crystal oscillator
All peripherals on, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from EEPROM
fCPU = fMASTER = 16 MHz
Unit
8.6
HSI internal RC
fCPU = fMASTER = 16 MHz
HSE Crystal oscillator
All peripherals on, fCPU = fMASTER = 16 MHz
code executed
HSE external clock
from RAM
fCPU = fMASTER = 16 MHz
Max
9.6
mA
9.35
HSI internal RC
fCPU = fMASTER = 16 MHz
9.2
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.8
STM8AF61xx, STM8AF51xx
Table 21.
Symbol
IDD(WFI)
Electrical characteristics
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter
Supply
current in
wait mode
Supply
IDD(SLOW) current in
slow mode
CPU not clocked,
all peripherals off
Conditions
Typ
HSE Crystal oscillator
fCPU = fMASTER = 24 MHz
2.0
HSE external clock
fCPU = fMASTER = 24 MHz
1.8
HSE Crystal oscillator
fCPU = fMASTER = 16 MHz
1.6
HSE external clock
fCPU = fMASTER = 16 MHz
1.38
HSI internal RC
fCPU = fMASTER = 16 MHz
1.21
HSI internal RC 16 MHz/8
fCPU = fMASTER = 2 MHz
1.05
HSE external clock 16 MHz/128
fCPU = fMASTER = 0.125 MHz
1.15
fCPU scaled down,
all peripherals off, HSI internal RC 16 MHz/128
fCPU = fMASTER = 0.125 MHz
code executed
from RAM
LSI internal RC 128 kHz
fCPU = fMASTER = 0.128MHz
HSE external clock 16 MHz/128
fCPU = fMASTER = 0.125 MHz
fCPU scaled down,
all peripherals off, HSI internal RC 16 MHz/128
fCPU = fMASTER = 0.125 MHz
code executed
from EEPROM
LSI internal RC 128 kHz
fCPU = fMASTER = 0.128 MHz
Max
Unit
mA
1.04
0.5
mA
1.21
1.09
0.56
63/100
Electrical characteristics
Table 22.
Symbol
STM8AF61xx, STM8AF51xx
Total current consumption and timing in halt, fast active halt and slow
active halt modes at VDD = 3.3 V
Parameter
IDD(H)
Supply current in halt mode
IDD(FAH)
Supply current in fast active halt
mode
IDD(SAH)
Supply current in slow active halt
mode
tWU(FAH)
Wake-up time from fast active halt
mode to run mode
tWU(SAH)
Wake-up time from slow active
halt mode to run mode
Conditions
Typ
Flash powered down
4.7
Flash in stand-by mode
62
Crystal osc 16 MHz/128
600
HSE osc 16 MHz/128
490
LSI RC 128 kHz
140
LSI RC 128 kHz
9
Max
Unit
µA
2(1)
µs
1. Data based on characterization results, not tested in production
64/100
(1)
100
STM8AF61xx, STM8AF51xx
Electrical characteristics
On-chip peripherals
Table 23.
Typical peripheral current consumption VDD = 5.0 V(1)
Symbol
Parameter
Typ.
Typ.
Typ.
fmaster =
fmaster =
fmaster =
2 MHz
16 MHz
24 MHz
IDD(TIM1)
TIM1 supply current(2)
0.03
0.23
0.34
IDD(TIM2)
TIM2 supply current (2)
0.02
0.12
0.19
IDD(TIM3)
TIM3 supply current(2)
0.01
0.1
0.16
IDD(TIM4)
TIM4 supply current(2)
0.004
0.03
0.05
USART supply current(2)
0.03
0.09
0.15
LINUART supply current(2)
0.03
0.11
0.18
IDD(SPI)
SPI supply current(2)
0.01
0.04
0.07
IDD(I2C)
I2C supply current(2)
0.02
0.06
0.91
IDD(CAN)
CAN supply current(3)
0.06
0.22
0.34
IDD(AWU)
AWU supply current(2)
0.003
0.02
0.05
All digital peripherals on
0.22
1
2.4
ADC supply current when
converting(4)
0.93
0.95
0.96
Data EEPROM programming
current
2.5
2.9
3.1
IDD(USART)
IDD(LINUART)
IDD(TOT_DIG)
IDD(ADC)
IDD(EE_PROG)
Unit
mA
1. Typical values - not tested in production. Since the peripherals are powered by an internally regulated,
constant digital supply voltage, the values are similar in the full supply voltage range.
2. Data based on a differential IDD measurement between no peripheral clocked and a single active
peripheral. This measurement does not include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a
permanent CAN data transmit sequence in loopback mode at 1 MHz. This measurement does not include
the pad toggling consumption.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
65/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Current consumption curves
Figure 11 to Figure 16 show typical current consumption measured with code executing in RAM.
Figure 11. Typ. IDD(RUN)HSE vs. VDD
@fCPU = 16 MHz, periph = on
Figure 12. Typ. IDD(RUN)HSE vs. fCPU
@ VDD = 5.0 V, periph = on
10
9
25°C
8
85°C
7
125°C
25°C
9
IDD(RUN)HSE [mA]
IDD(RUN)HSE [mA]
10
6
5
4
3
2
1
8
85°C
7
125°C
6
5
4
3
2
1
0
0
2.5
3
3.5
4
4.5
5
5.5
0
6
5
10
VDD [V]
25
30
3
2
25°C
85°C
125°C
1
0
4.5
5.5
Figure 14. Typ. IDD(WFI)HSE vs. VDD
@ fCPU = 16 MHz, periph = on
IDD(WFI)HSE [mA]
IDD(RUN)HSI [mA]
4
3.5
20
fcpu [MHz]
Figure 13. Typ. IDD(RUN)HSI vs. VDD
@ fCPU = 16 MHz, periph = off
2.5
15
6
5
4
3
2
25°C
85°C
125°C
1
0
2.5
6.5
3.5
4.5
5.5
6.5
VDD [V]
VDD [V]
Figure 15. Typ. IDD(WFI)HSE vs. fCPU
@ VDD = 5.0 V, periph = on
Figure 16. Typ. IDD(WFI)HSI vs. VDD
@ fCPU = 16 MHz, periph = off
2.5
IDD(WFI)HSI [mA]
IDD(WFI)HSE [mA]
6
5
4
3
25°C
2
85°C
1
1.5
1
25°C
85°C
0.5
125°C
125°C
0
0
2.5
0
5
10
15
fcpu [MHz]
66/100
2
20
25
3
3.5
4
4.5
30
VDD [V]
5
5.5
6
STM8AF61xx, STM8AF51xx
11.3.2
Electrical characteristics
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 24.
HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
fHSE_ext
User external clock source
frequency
VHSEdHL
Comparator hysteresis
0.1 x VDD
VHSEH
OSCIN input pin high level
voltage
0.7 x VDD
VHSEL
OSCIN input pin low level
voltage
Max
TA < 105 °C
0(1)
24
TA > 105 °C
(1)
16
Unit
MHz
0
V
VDD
V
ILEAK_HSE
OSCIN input leakage
current
VSS < VIN < VDD
VSS
0.3 x VDD
-1
+1
µA
1. In case of CSS, the external clock must have a frequency above 500 kHz.
Figure 17. HSE external clock source
VHSEH
VHSEL
fHSE
External clock
source
OSCIN
STM8A
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
67/100
Electrical characteristics
Table 25.
STM8AF61xx, STM8AF51xx
HSE oscillator characteristics
Symbol
Parameter
Conditions
RF
Feedback resistor
C(1)
Recommended load capacitance(2)
IDD(HSE)
gm
Min
Typ
Max
Unit
220
kΩ
20
pF
C = 20 pF
6 (startup)
2 (stabilized)
C = 10 pF
6 (startup)
1.5 (stabilized)
HSE oscillator power consumption
mA
Oscillator transconductance
5
mA/V
VDD is
stabilized
tSU(HSE)(3) Startup time
1
ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3.
tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
fHSE to core
Rm
Lm
RF
CO
CL1
OSCIN
Cm
gm
Resonator
Resonator
OSCOUT
CL2
HSE oscillator critical gm formula
f
2
g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C )
2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1 = CL2 = C: Grounded external capacitance
gm >> gmcrit
68/100
Consumption
control
STM8A
STM8AF61xx, STM8AF51xx
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 26.
HSI oscillator characteristics
Symbol
fHSI
Parameter
Conditions
Typ
Max
16
HSI oscillator user
trimming accuracy
ACCHS
HSI oscillator accuracy
(factory calibrated)
tsu(HSI)
Min
Frequency
-1(1)
1(1)
VDD = 5.0 V, TA = 25°C
-1(1)
1(1)
VDD = 5.0 V,
25 °C ≤TA ≤85 °C
Unit
MHz
Trimmed by the
application for any VDD
and TA conditions
±2
%
VDD = 5.0 V,
25 °C ≤TA ≤125 °C
-3(1)
3(1)
VDD = 3.0 V ≤VDD ≤ 5.5 V,
-40 °C ≤TA ≤ 125 °C
-5(1)
5(1)
HSI oscillator wake-up
time including calibration
2(2)
µs
1. Tested in production
2. Guaranteed by design, not tested in production
Figure 19. Typical HSI frequency vs VDD @ four temperatures
3%
-40°C
HSI frequency variation [%]
11.3.3
Electrical characteristics
2%
25°C
85°C
1%
125°C
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
69/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 27.
LSI oscillator characteristics
Symbol
fLSI
tsu(LSI)
Parameter
Conditions
Frequency
Min
Typ
Max
Unit
112
128
144
kHz
7(1)
µs
LSI oscillator wake-up time
1. Data based on characterization results, not tested in production.
Figure 20. Typical LSI frequency vs VDD @ room temperature
LSI frequency variation [%]
3%
2%
1%
25°C
0%
-1%
-2%
-3%
2.5
70/100
3
3.5
4
VDD [V]
4.5
5
5.5
6
STM8AF61xx, STM8AF51xx
11.3.4
Electrical characteristics
Memory characteristics
RAM and hardware registers
Table 28.
RAM and hardware registers
Symbol
Parameter
Conditions
Min
VRM
Data retention mode(1)
Halt mode (or reset)
1.8
Typ
Max
Unit
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production. refer to Table 18 on page 58
for the value of VIT-max
Flash program memory/data EEPROM memory
General conditions: TA = -40 to 125 °C.
Table 29.
Symbol
VDD
tprog
terase
Flash program memory/data EEPROM memory
Parameter
Operating voltage
(all modes, execution/write/erase)
Conditions
fCPU ≤24 MHz
3.0
Max
Unit
5.5
V
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
6
6.6
ms
Fast programming time for 1 block
(128 bytes)
3
3.3
ms
Erase time for 1 block (128 bytes)
3
3.3
ms
TA = 25 °C
1k
TA = 125 °C
100
TA = 25 °C
300 k
TA = 125 °C
100 k
TA = 145 °C
80 k
TA = 25 °C
40
TA = 55 °C
20
TA = 85 °C
10
Full temperature
range
1000
TA = 25 °C
40
TA = 55 °C
20
TA = 85 °C
10
Program memory endurance
erase/write cycles(2)
NRW
Data memory endurance erase/write
cycles(2)
Program memory after cycling
tRET
Data memory retention after cycling at
the endurance limits (T, n)
tRETI
Min(1) Typ
Intrinsic data retention
cycles
years
hours
years
1. Guaranteed by characterization, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
71/100
Electrical characteristics
11.3.5
STM8AF61xx, STM8AF51xx
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 30.
Symbol
I/O static characteristics
Parameter
VIL
Input low level
voltage
VIH
Input high level
voltage
Vhys
Hysteresis(1)
Conditions
VDD = 5.0 V
Min
Typ
Max
Unit
-0.3 V
0.3 x VDD
V
0.7 x VDD
VDD + 0.3 V
V
0.1 x
VDD
mV
I = 3 mA
Standard I/0, VDD = 5 V
VDD - 0.5 V
I = 1.5 mA
Standard I/0, VDD = 3 V
VDD - 0.4 V
I = 8mA
High sink and true open
drain I/0, VDD = 5 V
0.5
I = 3 mA
Standard I/0, VDD = 5 V
0.6
I = 1.5 mA
Standard I/0, VDD = 3 V
0.4
Rpu
Pull-up resistor
VDD = 5 V, VIN = VSS
tR, tF
Rise and fall time
(10% - 90%)
VOH
VOL
65
kΩ
Fast I/Os
Load = 50 pF
20(2)
ns
Standard and high sink I/Os
Load = 50 pF
125(2)
ns
Input leakage
current,
analog and digital
VSS ≤VIN ≤VDD
±1(2)
µA
Ilkg ana
Analog input
leakage current
VSS ≤ VIN ≤ VDD
-40 °C < TA < 125 °C
±250(2)
nA
Ilkg(inj)
Leakage current in
adjacent I/O(2)
Injection current ±4 mA
±1(2)
µA
Ilkg
35
50
V
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data based on characterization results, not tested in production.
72/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 21. Typical VIL and VIH vs VDD @ four temperatures
6
-40°C
25°C
5
85°C
VIL / V IH [V]
4
125°C
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 22. Typical pull-up resistance RPU vs VDD @ four temperatures
60
Pull-Up resistance [k ohm]
55
50
45
-40°C
40
25°C
85°C
35
125°C
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 23. Typical pull-up current Ipu vs VDD @ four temperatures
140
Pull-Up current [µA]
120
100
80
-40°C
60
25°C
40
85°C
125°C
20
0
0
1
2
3
4
5
6
VDD [V]
Note: The pull-up is a pure resistor (slope goes through 0).
73/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Typical output level curves
Figure 24 to Figure 33 show typical output level curves measured with output on a single pin.
Figure 24. Typ. VOL @ VDD = 3.3 V (standard
ports)
Figure 25. Typ. VOL @ VDD = 5.0 V (standard
ports)
-40°C
1.5
-40°C
1.5
25°C
25°C
85°C
1.25
85°C
1.25
125°C
125°C
1
VOL [V]
VOL [V]
1
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOL [mA]
Figure 26. Typ. VOL @ VDD = 3.3 V (true open
drain ports)
25°C
1.75
85°C
125°C
1.5
125°C
1.25
VOL [V]
VOL [V]
85°C
1.5
1.25
1
0.75
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
10
12
14
0
5
10
IOL [mA]
25°C
85°C
85°C
1.25
125°C
125°C
1
1
VOL [V]
VOL [V]
25
-40°C
1.5
25°C
1.25
20
Figure 29. Typ. VOL @ VDD = 5.0 V (high sink
ports)
-40°C
1.5
15
IOL [mA]
Figure 28. Typ. VOL @ VDD = 3.3 V (high sink
ports)
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
IOL [mA]
74/100
12
-40°C
2
25°C
1.75
10
Figure 27. Typ. VOL @ VDD = 5.0 V (true open
drain ports)
-40°C
2
8
IOL [mA]
10
12
14
0
5
10
15
IOL [mA]
20
25
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 30. Typ. VDD - VOH @ VDD = 3.3 V
(standard ports)
Figure 31. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports)
-40°C
2
1.75
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
-40°C
2
25°C
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOH [mA]
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high
sink ports)
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
12
-40°C
2
25°C
1.75
10
Figure 33. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports)
-40°C
2
8
IOH [mA]
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
IOH [mA]
10
12
14
0
5
10
15
20
25
IOH [mA]
75/100
Electrical characteristics
11.3.6
STM8AF61xx, STM8AF51xx
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 31.
NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL(NRST)
NRST input low level voltage(1)
VSS
TBD(2)
VIH(NRST)
NRST input high level voltage(1)
TBD(2)
VDD
VOL(NRST)
NRST output low level voltage(1)
RPU(NRST)
NRST pull-up resistor(3)
IOL=TBD(2) mA
30
40
60
kΩ
VF(NRST)
NRST input filtered pulse(4)
TBD(2)
ns
VNF(NRST)
NRST input not filtered pulse(4)
TBD(2)
µs
2. TBD = To be determined.
3. The RPU pull-up equivalent resistor is based on a resistive transistor
Data guaranteed by design, not tested in production.
Figure 34. Typical NRST VIL and VIH vs VDD @ four temperatures
-40°C
6
25°C
85°C
5
125°C
VIL / V IH [V]
4
3
2
1
0
2.5
3
3.5
4
4.5
VDD [V]
76/100
V
TBD(2)
1. Data based on characterization results, not tested in production.
4.
Unit
5
5.5
6
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 35. Typical NRST pull-up resistance RPU vs VDD @ four temperatures
-40°C
60
NRST Pull-Up resistance [k ohm]
25°C
55
85°C
125°C
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 36. Typical NRST pull-up current Ipu vs VDD @ four temperatures
140
NRST Pull-Up current [µA]
120
100
80
60
-40°C
25°C
40
85°C
20
125°C
0
0
1
2
3
VDD [V]
4
5
6
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 30. Otherwise the reset is not taken into account internally.
Figure 37. Recommended reset pin protection
STM8A
VDD
RPU
NRST
External
reset
circuit
Filter
Internal reset
0.01µ
77/100
Electrical characteristics
11.3.7
STM8AF61xx, STM8AF51xx
TIM 1, 2, 3, and 4 timer characteristics
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
Table 32.
TIM 1, 2, 3 characteristics
Symbol
tw(ICAP)in
tres(TIM)
fEXT
ResTIM
tCOUNTER
tMAX_COUNT
Parameter
Input capture pulse time(1)
(1)
Timer resolution time
Timer external clock frequency
Timer resolution
(1)
Maximum possible count(1)
Min
Typ
Max
Unit
2
TMASTER
1
TMASTER
(1)
16-bit counter clock period when
internal clock is selected(1)
1. Not tested in production
78/100
Conditions
24
MHz
16
bit
1
TMASTER
65 536 TMASTER
STM8AF61xx, STM8AF51xx
Electrical characteristics
SPI serial peripheral interface
11.3.8
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 33.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(NSS)(1)
(1)
th(NSS)
tw(SCKH)(1)
tw(SCKL)(1)
tsu(MI)(1)
tsu(SI)(1)
th(MI)(1)
th(SI)(1)
ta(SO)(1)(2)
SPI characteristics
Parameter
Conditions
Min
Max
Master mode
0
10
Slave mode
0
10
SPI clock frequency
MHz
SPI clock rise and fall time Capacitive load: C = 30 pF
25
NSS setup time
Slave mode
4*TMASTER
NSS hold time
Slave mode
70
SCK high and low time
Master mode,
fMASTER = 16 MHz, fSCK= 8 MHz
110
Master mode
5
Slave mode
2
Master mode,
fMASTER = 16 MHz, fSCK = 8 MHz
7
Slave mode,
fMASTER = 16 MHz, fSCK = 8 MHz
3
140
Data input setup time
Data input hold time
Data output access time
Slave mode,
fMASTER = 16 MHz, fSCK = 8 MHz
ns
400
Slave mode
tdis(SO)(1)(3)
4*tMASTER
Data output disable time
Slave mode
tv(SO)(1)
Data output valid time
Slave mode (after enable edge),
fMASTER = 16 MHz, fSCK = 8 MHz
100
tv(MO)(1)
Data output valid time
Master mode (after enable edge),
fMASTER = 16 MHz, fSCK = 8 MHz
3
th(SO)(1)
th(MO)(1)
Unit
Slave mode (after enable edge)
25
100
Data output hold time
Master mode (after enable edge)
6
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
79/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Figure 38. SPI timing diagram - slave mode and CPHA = 0
NSS input
tSU(NSS)
SCK Input
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS)
SCK Input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
80/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 40. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
81/100
Electrical characteristics
11.3.9
STM8AF61xx, STM8AF51xx
I2C interface characteristics
Table 34.
I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2)
Max(2)
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(4)
tr(SDA)
tr(SCL)
SDA and SCL rise time
(VDD 3 ... 5.5 V)
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
(VDD 3 ... 5.5 V)
300
300
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
µs
STOP to START condition time
(bus free)
4.7
1.3
µs
tw(STO:STA)
Cb
µs
900(3)
µs
Capacitive load for each bus line
1. fMASTER, must be at least 8 MHz to achieve max fast
400
I 2C
400
speed (400 kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
82/100
ns
pF
STM8AF61xx, STM8AF51xx
11.3.10
Electrical characteristics
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 35.
Symbol
ADC characteristics
Parameter
fADC
ADC clock frequency
VDDA
Analog supply
VREF+
VREF-
Conditions
Min
Typ
Max
2
Unit
MHz
3
5.5
V
Positive reference voltage
2.75
VDDA
V
Negative reference voltage
VSSA
0.5
V
VSSA
VDDA
V
VREF-
VREF+
V
VAIN
Conversion voltage range(1)
CADC
Internal sample and hold
capacitor
tS(1)
Sampling time
(3 x 1/fADC)
tSTAB
Wake-up time from standby
tCONV
Total conversion time including
sampling time
(14 x 1/fADC)
Devices with
external VREF+/
VREF- pins
fADC = 2 MHz
fADC = 2 MHz
3
pF
1.5
µs
7
µs
7
µs
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
83/100
Electrical characteristics
Table 36.
Symbol
STM8AF61xx, STM8AF51xx
ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V
Parameter
Conditions
Typ
Max
|ET|
Total unadjusted error(1)
1.5
TBD(1)
|EO|
Offset error(1)
1.1
TBD(1)
|EG|
Gain error(1)
-0.2/0.6
TBD(1)
|ED|
Differential linearity error(1)
0.9
TBD(1)
|EL|
Integral linearity error(1)
1
TBD(1)
Typ
Max
fADC = 2 MHz
Unit
LSB
1. TBD = To be determined
Table 37.
Symbol
ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V
Parameter
Conditions
|ET|
Total unadjusted error(1)
1.4
3
|EO|
Offset error(1)
0.8
2
|EG|
Gain error(1)
0.1
1
|ED|
Differential linearity error(1)
0.9
2
|EL|
Integral linearity error(1)
0.7
2
fADC = 2 MHz
Unit
LSB
1. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 11.3.5 does not affect the ADC accuracy.
Figure 41. ADC accuracy characteristics
EG
1023
1022
1021
1LSB
IDEAL
–V
V
DDA
SSA
= ----------------------------------------1024
(2)
ET
7
(3)
(1)
6
5
4
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
1021102210231024
VDDA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: Deviation between the first actual transition and the first ideal one.
EG = Gain error: Deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.
84/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 42. Typical application with ADC
VDD
VT
0.6V
RAIN
AINx
VAIN
CAIN
11.3.11
STM8A
10-bit A/D
conversion
VT
0.6V
IL
¬±1¬
CADC
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
85/100
Electrical characteristics
Table 38.
STM8AF61xx, STM8AF51xx
EMS data
Symbol
Parameter
Conditions
Level/class
VFESD
VDD = 3.3 V, TA= 25 °C,
Voltage limits to be applied on any I/O pin to
fMASTER = 16 MHz (HSI clock),
induce a functional disturbance
Conforms to IEC 1000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD= 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-4
4A
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 39.
EMI data
Conditions
Symbol
Parameter
General conditions
SEMI
Peak level
SAE EMI level
VDD = 5 V,
TA = 25 °C,
LQFP80 package
conforming to SAE J
1752/3
Monitored
frequency band
Max fCPU(1)
Unit
8
MHz
16
MHz
24
MHz
0.1 MHz to 30 MHz
15
17
22
30 MHz to 130 MHz
18
22
16
130 MHz to 1 GHz
-1
3
5
2
2.5
2.5
dBµV
-
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
86/100
STM8AF61xx, STM8AF51xx
Table 40.
Electrical characteristics
ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge voltage
(Human body model)
TA = 25°C, conforming to
JESD22-A114
3A
4000
VESD(CDM)
Electrostatic discharge voltage
(Charge device model)
TA= 25°C, conforming to
JESD22-C101
3
500
VESD(MM)
Electrostatic discharge voltage
(Machine model)
TA= 25°C, conforming to
JESD22-A115
B
200
V
1. Data based on characterization results, not tested in production
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
●
A supply overvoltage (applied to each power supply pin) and
●
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 41.
Symbol
Electrical sensitivities
Parameter
Static latch-up class
LU
Conditions
Class(1)
TA = 25 °C
A
TA = 85 °C
A
TA = 125 °C
A
TA = 145 °C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
87/100
Electrical characteristics
11.4
STM8AF61xx, STM8AF51xx
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 17: General operating conditions on page 57.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
–
TAmax is the maximum ambient temperature in ° C
–
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
–
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
–
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum
chip internal power.
–
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level
in the application.
Table 42.
Thermal characteristics(1)
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
38
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
46
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
57
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
59
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
11.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
88/100
STM8AF61xx, STM8AF51xx
11.4.2
Electrical characteristics
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 47: STM8A order codes on page 95).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 82 °C (measured according to JESD51-2),
IDDmax = 8 mA, VDD = 5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V= 400 mW
PIOmax = 20 x 8 mA x 0.4 V = 64 mW
This gives: PINTmax = 400 mW and PIOmax 64 mW:
PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
Using the values obtained in Table 42: Thermal characteristics on page 88 TJmax is
calculated as follows:
–
For LQFP64 46°C/W
TJmax = 82° C + (46° C/W x 464 mW) = 82°C + 21°C = 103° C
This is within the range of the suffix B version parts (-40 < TJ < 105° C).
Parts must be ordered at least with the temperature range suffix B.
89/100
Package characteristics
12
STM8AF61xx, STM8AF51xx
Package characteristics
To meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.
90/100
STM8AF61xx, STM8AF51xx
12.1
Package characteristics
Package mechanical data
Figure 43. 80-pin low profile quad flat package (14 x 14)
A
A2
D
D1
A1
b
e
E1 E
c
L1
L
Table 43.
θ
80-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.22
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.32
0.38
0.0087
0.0126
0.0150
0.20
0.0035
0.0079
D
16.00
0.6299
D1
14.00
0.5512
E
16.00
0.6299
E1
14.00
0.5512
e
0.65
0.0256
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
1. Values in inches are converted from mm and rounded to 4 decimal digits
91/100
Package characteristics
STM8AF61xx, STM8AF51xx
Figure 44. 64-pin low profile quad flat package (10 x 10)
A
A2
A1
D
D1
Seating plane
(0.1 x 0.004 mm)
b
e
E1 E
c
M x 45°
Pin 1 identification
L1
L
θ
1. Available only for STM8A products with up to 64 Kbytes Flash
Table 44.
64-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
0.0079
D
12.00
0.4724
D1
10.00
0.3937
E
12.00
0.4724
E1
10.00
0.3937
e
0.50
0.0197
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
1. Values in inches are converted from mm and rounded to 4 decimal digits
92/100
Typ
0.0394
STM8AF61xx, STM8AF51xx
Package characteristics
Figure 45. 48-pin low profile quad flat package (7 x 7)
A
D
A2
D1
A1
b
e
E1
E
c
L1
L
Table 45.
θ
48-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
0.0079
D
9.00
0.3543
D1
7.00
0.2756
E
9.00
0.3543
E1
7.00
0.2756
e
0.50
0.0197
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
1. Values in inches are converted from mm and rounded to 4 decimal digits
93/100
Package characteristics
STM8AF61xx, STM8AF51xx
Figure 46. 32-pin low profile quad flat package (7 x 7)
D
A
A2
D1
A1
e
b
E1 E
c
L1
L
Table 46.
θ
32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.30
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.37
0.45
0.0118
0.0146
0.0177
0.20
0.0035
0.0079
D
9.00
0.3543
D1
7.00
0.2756
E
9.00
0.3543
E1
7.00
0.2756
e
0.80
0.0315
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
1. Values in inches are converted from mm and rounded to 4 decimal digits
94/100
Typ
0.0394
STM8AF61xx, STM8AF51xx
13
Ordering information
Ordering information
Figure 47. STM8A order codes
STM8A
F
51
A
A
T
D
xxx(1)
Y
Product family
Temperature range
STM8A....8-bit microcontroller
Memory size
Program memory type
F....Flash + EEPROM
P....FASTROM no EEPROM
H....Flash no EEPROM
Q....FASTROM + EEPROM
Device family
5x - CAN/LIN
6x - LIN only
Pin count
2....8 Kbyte
3....20 pins
4....16 Kbyte
6....32 pins
7....44 pins
8....48 pins
9....64 pins
A....80 pins
B....100 pins
C....128 pins
6....32 Kbyte
7....48 Kbyte
8....64 Kbyte
9....96 Kbyte
A....128 Kbyte
B....256 Kbyte
A....-40 °C to +85 °C
B....-40 °C to +105 °C
C....-40 °C to +125 °C
D....-40 °C to +145 °C
Package type
T.....LQFP
U....QFN
Packaging
Y.... Tray
U.... Tube
R.... Tape and reel
X.... Tape and reel x90°
1. Customer specific FASTROM code
95/100
STM8 development tools
14
STM8AF61xx, STM8AF51xx
STM8 development tools
Development tools for the STM8A microcontrollers include the
●
STice emulation system offering tracing and code profiling
●
STVD high-level language debugger including assembler and visual development
environment - seamless integration of third party C compilers
●
STVP Flash programming software
In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
14.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
96/100
●
Program and data trace recording up to 128 K records
●
Advanced breakpoints with up to 4 levels of conditions
●
Data breakpoints
●
Real-time read/write of all device ressources during emulation
●
Occurrence and time profiling and code coverage analysis (new features)
●
In-circuit debugging/programming via SWIM protocol
●
8-bit probe analyzer
●
1 input and 2 output triggers
●
USB 2.0 high speed interface to host PC
●
Power supply follower managing application voltages between 1.62 to 5.5 V
●
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8
STM8AF61xx, STM8AF51xx
14.2
STM8 development tools
Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the Cosmic C compiler
for STM8, which is available in a free version that outputs up to 16 Kbytes of code.
14.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST visual develop – Full-featured integrated development environment from ST, featuring
●
Seamless integration of C and ASM toolsets
●
Full-featured debugger
●
Project management
●
Syntax highlighting editor
●
Integrated programming interface
●
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8A microcontroller’s Flash memory. STVP also offers project
mode for saving programming configurations and automating programming sequences.
14.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
14.3
●
C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code.
For more information, see www.cosmic-software.com, www.raisonance.com
●
STM8 assembler linker – Free assembly toolchain included in the STM8 toolset,
which allows you to assemble and link your application source code.
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8A Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8A.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
97/100
Revision history
15
STM8AF61xx, STM8AF51xx
Revision history
Table 47.
Document revision history
Date
Revision
31-Jan-2008
Rev 1
Initial release
Rev 2
Added ‘H’ products to the datasheet (Flash no EEPROM).
Features on page 1: Updated Memories, Reset and supply
management, Communication interfaces and I/Os; reduced wakeup
pins by 1.
Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166,
STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and
STM8AF5166.
Section 1, Section 5, Section 6.2.1, Table 13, and Section 10:
Updated reference documentation: RM0009, PM0047, and UM0470.
Section 2: Added information about peak performance.
Section 3: Removed STM8A common features table.
Table 2: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T,
and STM8AF5166T.
Table 3: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T,
and STM8AF6146T.
Section 5: Made minor content changes and improved readability
and layout.
Section 5.4.3: Major modification, TMU included.
Section 5.6.2: User triming updated.
Section 5.6.3: LSI as CPU clock added.
Section 5.6.4 , Section 5.6.5: Maximum frequency conditional 32
Kbyte/128 Kbyte.
Section 5.8: Scan for 128 Kbyte removed.
Section 5.9, Section 5.9.3: SPI 10 Mb/s.
Figure 3, Figure 4, and Figure 5: Amended footnote 1.
Table 5: HS output changed from 20 mA to 8 mA.
Section 7: Corrected Figure 7: Register and memory map; removed
address list; added Table 7.
Section 11.3.1 Note on typical/WC values added.
Table 10: Replaced the source blocks ‘simple USART’, ‘very low-end
timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and
‘reserved’ respectively, added TMU registers.
Table 12: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL)
Table 13: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4
PRSC [1:0], and OPT6, added OPT7 to 16 (TMU).
Table 15: Amended footnotes.
Table 17: Added parameter ‘voltage and current operating
conditions’.
Table 18: Amended footnotes.
Table 19: Replaced.
Table 20: Amended maximum data and footnotes.
Table 21: Replaced.
Table 22: Added and amended IDD(RUN) data; amended IDD(WFI)
data; amended footnotes.
Table 23: Filled in, amended maximum data and footnotes.
Figure 11 to Figure 16: info on peripheral activity added.
Table 24: Modified fHSE_ext data and added VHSEdhl data.
22-Aug-2008
98/100
Changes
STM8AF61xx, STM8AF51xx
Table 47.
Revision history
Document revision history (continued)
Date
22-Aug-2008
Revision
Changes
Rev 2
cont’d
Table 26: Removed ACCHSI parameters and replaced with ACCHS
parameters; amended data and footnotes.
Table 28: Amended data.
Table 29: Updated names and data of NRW and tRET parameters.
Table 30: Added VOH and VOL parameters; Updated Ilkg ana
parameter.
Removed: Output driving current (standard ports), Output driving
current (true open drain ports), and Output driving current (high sink
ports).
Table 35: Updated fADC, tS, and tCONV data.
Table 36: Removed the 4-MHz condition from all parameters.
Table 37: Removed the 4-MHz condition from all parameters;
updated footnote 1 and removed footnote 2.
Table 41: Added data for TA = 145 °C.
Figure 47: Updated memory size, pin count and package type
information.
99/100
STM8AF61xx, STM8AF51xx
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100/100