HT32F1653/HT32F1654 Series Datasheet

32-bit ARM® Cortex™-M3 Microcontroller, up to 64KB Flash and
16KB SRAM with 1 MSPS ADC, USART, UART, SPI, I2C, I2S, MCTM,
GPTM, BFTM, PDMA, SCI, CRC, EBI and USB2.0 FS
HT32F1653/HT32F1654 Series
Datasheet
Revision: V1.00
Date: ����������������
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 8
Clock Control Unit – CKCU..................................................................................................... 8
Power Management – PWRCU.............................................................................................. 8
External Interrupt/Event Controller – EXTI............................................................................. 9
Analog to Digital Converter – ADC......................................................................................... 9
Analog Comparator – CMP..................................................................................................... 9
I/O Ports................................................................................................................................ 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Motor Control Timer – MCTM............................................................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer – WDT........................................................................................................ 12
Real Time Clock – RTC........................................................................................................ 12
Inter-integrated Circuit – I2C................................................................................................. 13
Serial Peripheral Interface – SPI.......................................................................................... 13
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 14
Universal Asynchronous Receiver Transmitter – UART....................................................... 15
Smart Card Interface – SCI.................................................................................................. 15
Inter-IC Sound – I2S.............................................................................................................. 16
Cyclic Redundancy Check – CRC........................................................................................ 16
Peripheral Direct Memory Access – PDMA.......................................................................... 17
External Bus Interface – EBI................................................................................................. 17
Universal Serial Bus Device Controller – USB..................................................................... 18
Debug Support...................................................................................................................... 18
Package and Operation Temperature................................................................................... 18
3 Overview................................................................................................................. 19
Device Information................................................................................................................ 19
Block Diagram...................................................................................................................... 20
Memory Map......................................................................................................................... 21
Clock Structure..................................................................................................................... 22
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Table of Contents
On-chip Memory..................................................................................................................... 7
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
4 Pin Assignment...................................................................................................... 23
5 Electrical Characteristics...................................................................................... 29
Absolute Maximum Ratings.................................................................................................. 29
Recommended DC Operating Conditions............................................................................ 29
On-Chip LDO Voltage Regulator Characteristics.................................................................. 29
Reset and Supply Monitor Characteristics............................................................................ 31
External Clock Characteristics.............................................................................................. 31
Internal Clock Characteristics............................................................................................... 32
PLL Characteristics............................................................................................................... 33
Memory Characteristics........................................................................................................ 33
I/O Port Characteristics......................................................................................................... 34
ADC Characteristics............................................................................................................. 35
Comparator Characteristics.................................................................................................. 37
GPTM/MCTM Characteristics............................................................................................... 37
I2C Characteristics................................................................................................................ 38
SPI Characteristics............................................................................................................... 39
I2S Characteristics................................................................................................................ 40
USB Characteristics.............................................................................................................. 42
6 Package Information............................................................................................. 43
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 44
64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 45
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Table of Contents
Power Consumption............................................................................................................. 30
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
List of Tables
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List of Tables
Table 1 HT32F1654/1653 Series Features and Peripheral List................................................................ 19
Table 2 HT32F1654/1653 Series Pin Assignment for LQFP 64 / 48 Package.......................................... 25
Table 3 HT32F1654/1653 Pin Description................................................................................................ 27
Table 4 Absolute Maximum Ratings.......................................................................................................... 29
Table 5 Recommended DC Operating Conditions.................................................................................... 29
Table 6 LDO Characteristics..................................................................................................................... 29
Table 7 Power Consumption Characteristics............................................................................................ 30
Table 8 LVD/BOD Characteristics............................................................................................................. 31
Table 9 High Speed External Clock (HSE) Characteristics....................................................................... 31
Table 10 Low Speed External Clock (LSE) Characteristics...................................................................... 32
Table 11 High Speed Internal Clock (HSI) Characteristics....................................................................... 32
Table 12 Low Speed Internal Clock (LSI) Characteristics......................................................................... 33
Table 13 PLL Characteristics.................................................................................................................... 33
Table 14 Flash Memory Characteristics.................................................................................................... 33
Table 15 I/O Port Characteristics.............................................................................................................. 34
Table 16 ADC Characteristics................................................................................................................... 35
Table 17 Comparator Characteristics....................................................................................................... 37
Table 18 GPTM/MCTM Characteristics.................................................................................................... 37
Table 19 I2C Characteristics...................................................................................................................... 38
Table 20 SPI Characteristics..................................................................................................................... 39
Table 21 I2S Characteristics...................................................................................................................... 40
Table 22 USB DC Electrical Characteristics............................................................................................. 42
Table 23 USB AC Electrical Characteristics.............................................................................................. 42
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
List of Figures
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List of Figures
Figure 1 HT32F1654/1653 Block Diagram............................................................................................... 20
Figure 2 HT32F1654/1653 Memory Map.................................................................................................. 21
Figure 3 HT32F1654/1653 Clock Structure.............................................................................................. 22
Figure 4 HT32F1654/1653 LQFP-48 Pin Assignment.............................................................................. 23
Figure 5 HT32F1654/1653 LQFP-64 Pin Assignment.............................................................................. 24
Figure 6 ADC Sampling Network Model................................................................................................... 36
Figure 7 I2C Timing Diagrams................................................................................................................... 38
Figure 8 SPI Timing Diagrams - SPI Master Mode................................................................................... 39
Figure 9 SPI Timing Diagrams - SPI Slave Mode with CPHA=1.............................................................. 40
Figure 10 Timing of I2S Master Mode....................................................................................................... 41
Figure 11 Timing of I2S Slave Mode.......................................................................................................... 41
Figure 12 USB Signal Rise Time and Fall Time and Cross-Point Voltage (VCRS) Definition.................. 42
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
1
General Description
The Holtek HT32F1654/1653 devices are high performance, low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M3 processor core. The Cortex™-M3 is a nextgeneration processor core which is tightly coupled with a Nested Vectored Interrupt Controller
(NVIC), SysTick timer and which includes advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control, fingerprint
recognition and so on.
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General Description
The devices operate at a frequency of up to 72MHz with a Flash accelerator to obtain maximum
efficiency. They provide up to 64KB of embedded Flash memory for code/data storage and 16KB
of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, PDMA, GPTM, MCTM, SCI, EBI, CRC16/32, USB2.0 FS, SW-DP (Serial Wire Debug Port), etc., are also implemented in the devices.
Several power saving modes provide the flexibility for maximum optimisation between wakeup
latency and power consumption, an especially important consideration in low power applications.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
2
Features
Core
■■ 32-bit ARM® Cortex™-M3 processor core
■■ Up to 72 MHz operating frequency
Features
■■ 1.25 DMIPS/MHz - Dhrystone 2.1
■■ Single-cycle multiplication and hardware division
■■ Integrated Nested Vectored Interrupt Controller - NVIC
■■ 24-bit SysTick timer
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
special features such as a Thumb-2 instruction set, hardware divider, low latency interrupt response
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets.
On-chip Memory
■■ Up to 64 KB on-chip Flash memory for instruction/data and option storage
■■ 16 KB on-chip SRAM
■■ Supports multiple boot modes
The ARM® Cortex™-M3 processor is structured using Harvard architecture which implements a
separate bus structure to fetch instructions and load/store data. The instruction code and data are
both located in the same memory address space but in different address ranges. The maximum
address range of the Cortex™-M3 is 4 GB due to its 32-bit bus address width. Additionally, a predefined memory map is provided by the Cortex™-M3 processor to reduce the software complexity
of repeated implementation for different device vendors. However, some regions are used by the
ARM® Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference
Manual for more information. Figure 2 shows the memory map of the HT32F1654/53 series of
devices, including Code, SRAM, peripheral, and other pre-defined regions.
Flash Memory Controller – FMC
■■ Flash accelerator for maximum efficiency
■■ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
■■ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Reset Control Unit – RSTCU
■■ Supply supervisor:
●● Power-on Reset - POR
●● Brown-out Detector - BOD
●● Programmable Low Voltage Detector - LVD
Clock Control Unit – CKCU
■■ External 4 to 16 MHz crystal oscillator
■■ External 32,768 Hz crystal oscillator
■■ Internal 8MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C
operating temperature
■■ Internal 32 kHz RC oscillator
■■ Integrated system clock PLL
■■ Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider and
gating circuitry. The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock
(CK_SYS) which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock
(RTC) use either the LSI or LSE as their clock source. The maximum operating frequency of the
system core clock (CK_AHB) can be up to 72 MHz.
Power Management – PWRCU
■■ Single 3.3 V power supply: 2.7 V to 3.6 V
■■ Integrated 1.8 V LDO regulator for core and peripheral power supply
■■ VBAT battery power supply for RTC and backup registers
■■ Three power domains: 3.3 V, 1.8 V and Backup
■■ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
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Features
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
External Interrupt/Event Controller – EXTI
■■ Up to 16 EXTI lines with configurable trigger source and type
■■ All GPIO pins can be selected as EXTI trigger source
■■ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
■■ Individual interrupt enable, wakeup enable and status bits for each EXTI line
■■ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate a
wake-up event or interrupt requests independently. Each EXTI line can also be masked independently.
Analog to Digital Converter – ADC
■■ 12-bit SAR ADC engine
■■ Up to 1 Msps conversion rate - 1 μs at 56 MHz, 1.17 μs at 72 MHz
■■ Up to 12 external analog input channels
■■ Supply voltage range: 2.7 V ~ 3.6 V
■■ Conversion range: VREF+ ~ VREFA 12-bit multi-channel ADC is integrated in the device. There are up to 12 multiplexed channels,
which include external channels on which the external analog signals can be measured, and 2
internal channels. If the input voltage is required to remain within a specific threshold window,
an Analog Watchdog function will monitor and detect these signals. An interrupt will then be
generated to inform the device that the input voltage is not within the preset threshold levels. There
are three conversion modes to convert an analog signal to digital data. The ADC can be operated in
one shot, continuous and discontinuous conversion modes.
Analog Comparator – CMP
■■ Dual rail-to-rail comparators
■■ Each comparator has configurable negative inputs used for flexible voltage selection
■■ Dedicated I/O pin or internal voltage reference provided by an internal 6-bit scaler
■■ Programmable hysteresis
■■ Programming speed and consumption
■■ Comparator outputs can be routed to I/O pins, to timers or to ADC trigger inputs
■■ 6-bit scaler can be configured to dedicated I/O pins for a voltage reference
■■ Comparators have interrupt generation capability with wakeup function from within the Sleep or
Deep Sleep modes through the EXTI controller
■■ Supply voltage range: 2.7 V ~ 3.6 V
Two general purpose comparators – CMP - are implemented within the devices. These can be
configured either as standalone comparators or combined with the different kinds of peripheral
functions. Each comparator is capable of generating an interrupt to the NVIC and waking up the
MCU from the Deep Sleep mode through EXTI wakeup event management unit.
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Features
■■ Software interrupt trigger mode for each EXTI line
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
I/O Ports
■■ Up to 51 GPIOs
■■ Port A, B, C, D are mapped as 16 external interrupts - EXTI
■■ Almost all I/O pins are 5 V-tolerant except for pins shared with analog inputs
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit, EXTI.
PWM Generation and Capture Timers – GPTM
■■ Two 16-bit up, down, up/down auto-reload counters
■■ 16-bit programmable prescaler allowing counter clock frequency division ratio between 1 and
65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Encoder interface controller with two inputs using a quadrature decoder
The General Purpose Timers consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.
They can be used for a variety of purposes including general time measurement, input signal pulse
width measurement and output waveform generation such as that for single pulse generation or
for PWM output generation. The GPTM includes an Encoder Interface using a decoder with two
inputs.
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Features
There are up to 51 General Purpose I/O pins, GPIO, named from PA0~PA15 to PD0~PD2 for the
implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximize flexibility and to meet the requirements of a wide
range of applications.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Motor Control Timer – MCTM
■■ Two 16-bit up, down, up/down auto-reload counters
■■ 16-bit programmable prescaler allowing counter clock frequency division ratio between 1 and
65536
■■ Input Capture function
■■ PWM waveform generation with edge aligned and centre-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Complementary Outputs with programmable dead-time insertion
■■ Encoder interface controller with two inputs using a quadrature decoder
■■ Includes a 3-phase motor control and hall sensor interface
■■ Brake input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter; four 16-bit CCRs (Capture/
Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter
and several control/status registers. It can be used for a variety of purposes including measuring
the pulse widths of input signals or generating output waveforms such as compare match outputs,
PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM supports an
Encoder interface controller to an incremental encoder with two inputs. The MCTM is capable of
offering full functional support for motor control, hall sensor interfacing and brake input.
Basic Function Timer – BFTM
■■ Two 32-bit compare/match count-up counters - no I/O control features
■■ One shot mode - counting stops after a match condition
■■ Repetitive mode - restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
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Features
■■ Compare Match Output
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Watchdog Timer – WDT
■■ 12-bit down counter with 3-bit prescaler
■■ Interrupt or reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
Real Time Clock – RTC
■■ 32-bit up-counter with a programmable prescaler
■■ Alarm function
■■ Interrupt and Wake-up event
The Real Time Clock, RTC for short, includes an APB interface, a 32-bit count-up counter, a
control register, a prescaler, a compare register and a status register. Most of the RTC circuits are
located in the Backup Domain except for the APB interface. The APB interface is located in the
VDD18 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from
the power control unit when the V DD18 power domain is powered off, that is when the device enters
the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume
signal from the Power-Down mode.
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Features
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to
software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value
register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry
and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or
a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts
down and reaches a zero value. If the software does not reload the counter value before a Watchdog
Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In
addition, an interrupt or reset is also generated if the software reloads the counter when the counter
value is greater than or equal to the WDT delta value. This means the counter must be reloaded
within a limited timing window using a specific method. The Watchdog Timer counter can be
stopped while the processor is in the debug mode. There is a register write protect function which
can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Inter-integrated Circuit – I2C
■■ Supports both master and slave modes with a frequency of up to 1 MHz
■■ Provide an arbitration function and clock synchronization
■■ Supports 7-bit and 10-bit addressing modes and general call addressing
■■ Supports slave multi-addressing mode with maskable address
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I2C module also has
an arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
Serial Peripheral Interface – SPI
■■ Supports both master and slave mode
■■ Frequency of up to fPCLK/2 MHz for master mode and fPCLK/3 MHz for slave mode
■■ FIFO Depth: 8 levels
■■ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
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Features
The I2C Module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two line serial interface used for connection to external hardware. These
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides three data transfer rates: 1. 100 kHz in the Standard mode, 2. 400 kHz in the Fast mode
and 3. 1 MHz in the Fast mode plus mode. The SCL period generation register is used to setup
different kinds of duty cycle implementations for the SCL pulse.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Universal Synchronous Asynchronous Receiver Transmitter – USART
■■ Supports both asynchronous and clocked synchronous serial communication modes
■■ Asynchronous operating baud rate up to fPCLK/16 MHz and synchronous operating rate up to fPCLK/8 MHz
■■ Full duplex communication
Features
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
■■ Auto hardware flow control mode - RTS, CTS
■■ IrDA SIR encoder and decoder
■■ RS485 mode with output enable control
■■ FIFO Depth: 16 x 9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a 16-byte transmitter FIFO, (TX_FIFO) and
a 16-byte receiver FIFO (RX_FIFO). The software can detect a USART error status by reading the
Line Status Register, LSR. The status includes the type and the condition of transfer operations as
well as several error conditions resulting from Parity, Overrun, Framing and Break events.
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32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Universal Asynchronous Receiver Transmitter – UART
■■ Asynchronous serial communication operating baud-rate up to fPCLK/16 MHz
■■ Full duplex communication
Features
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
■■ FIFO Depth: 16 x 9 bits for both receiver and transmitter
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports four types of interrupt including Line Status Interrupt, Transmitter FIFO Empty
Interrupt, Receiver Threshold Level Reaching Interrupt and Time Out Interrupt. The UART
module includes a 16-byte transmitter FIFO, (TX_FIFO) and a 16-byte receiver FIFO (RX_
FIFO). The software can detect a UART error status by reading the Line Status Register, LSR. The
status includes the type and the condition of transfer operations as well as several error conditions
resulting from Parity, Overrun, Framing and Break events.
Smart Card Interface – SCI
■■ Supports ISO 7816-3 standard
■■ Character mode
■■ Single transmit buffer and single receive buffer
■■ 11-bit ETU (elementary time unit) counter
■■ 9-bit guard time counter
■■ 24-bit general purpose waiting time counter
■■ Parity generation and checking
■■ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
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32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Inter-IC Sound – I2S
■■ Master or slave mode
■■ Mono and stereo
■■ I2S-justified, Left-justified, and Right-justified mode
■■ 8/16/24/32-bit sample size with 32-bit channel extended
■■ 8-bit Fractional Clock Divider with rate control
The I 2S is a synchronous communication interface that can be used as a master or slave to
exchange data with other audio peripherals, such as ADCs or DACs. The I2S supports a variety of
data formats. In addition to the stereo I2S-justified, Left-justified and Right-justified modes, there
are mono PCM modes with 8/16/24/32-bit sample size. When the I2S operates in the master mode,
then when using the fractional divider, it can provide an accurate sampling frequency output and
support the rate control function and fine-tuning of the output frequency to avoid system problems
caused by the cumulative frequency error between different devices.
Cyclic Redundancy Check – CRC
■■ Support CRC16 polynomial: 0x8005,
X16+X15+X2+1
■■ Support CCITT CRC16 polynomial: 0x1021,
X16+X12+X5+1
■■ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
■■ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
■■ Supports byte, half-word & word data size
■■ Programmable CRC initial seed value
■■ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32bit data
■■ Supports PDMA to complete a CRC computation of a block of memory
The CRC calculation unit is an error detection technique test algorithm which is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data
as input and generates a 16- or 32-bit output remainder. Ordinarily, a data stream is suffixed by a
CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, that means data stream contains a data error.
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Features
■■ 8 x 32-bit Tx & Rx FIFO with PDMA supported
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Peripheral Direct Memory Access – PDMA
■■ 8 channels with trigger source grouping
■■ 8-/16-/32-bit width data transfer
■■ Supports Address increment, decrement or fixed mode
■■ 4-level programmable channel priority
■■ Supports trigger source: ADC, SPI, USART, UART, I2C, I2S, EBI, GPTM, MCTM, SCI and
software request
The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals
and the system memory on the AHB bus. Each PDMA channel has a source address, destination
address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid
interrupt service routine execution. It improves system performance as the software does not need
to join each data movement operation.
External Bus Interface – EBI
■■ Programmable interface for various memory types
■■ Translate the AHB transactions into the appropriate external device protocol
■■ Memory bank regions and independent chip select control for each memory bank
■■ Programmable timings to support a wide range of devices
■■ Includes page read mode
■■ Automatic translation when the AHB transaction width and external memory interface width is
different
■■ Write buffer to decrease the stalling of the AHB write burst transaction
■■ Multiplexed address and data line configurations
■■ Up to 21 address lines
■■ Up to 16-bit data bus width
The external bus interface is able to access external parallel interface devices such as SRAM,
Flash and LCD modules. The interface is memory mapped into the internal address map of the
CPU. The data and address lines are multiplexed in order to reduce the number of pins required to
connect to the external devices. The read/write timing of the bus can be adjusted to meet the timing
specification of the external devices. Note the interface only supports asynchronous 8 or 16-bit bus
interface.
Rev. 1.00
17 of 46
January 28, 2015
Features
■■ Auto reload mode
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Universal Serial Bus Device Controller – USB
■■ Complies with USB 2.0 full-speed (12Mbps) specification
■■ On-chip USB full-speed transceiver
■■ 1 control endpoint (EP0) for control transfer
■■ 3 single-buffered endpoints for bulk and interrupt transfer
■■ 1,024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM
is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding
registers, which provides maximum flexibility for various applications. The integrated USB fullspeed transceiver helps to minimize the overall system complexity and cost. The USB functional
block also contains the resume and suspend feature to meet the requirements of low-power
consumption.
Debug Support
■■ Serial Wire Debug Port - SW-DP
■■ 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal
patches
■■ 4 comparators for hardware watchpoints
■■ 1-bit asynchronous trace (TRACESWO)
Package and Operation Temperature
■■ 48/64-pin LQFP package
■■ Operation temperature range: -40°C to +85°C
Rev. 1.00
18 of 46
January 28, 2015
Features
■■ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
3
Overview
Device Information
Table 1 HT32F1654/1653 Series Features and Peripheral List
63
32
Option Bytes Flash
1
1
SRAM (KB)
16
8
Timers
Communication
Rev. 1.00
HT32F1654
MCTM
2
GPTM
2
BFTM
2
RTC
1
WDT
1
USB
1
SPI
2
USART
2
UART
2
IC
2
I2S
1
SCI
1
2
EBI
1
CRC-16/32
1
EXTI
16
12-bit ADC
Number of channels
1
Comparator
2
GPIO
Up to 51
CPU frequency
Up to 72 MHz
Operating voltage
2.7 V ~ 3.6 V
Operating temperature
-40℃ ~ +85℃
Packages
48/64-pin LQFP
HT32F1653
Overview
Peripherals
Main Flash (KB)
12 Channels
19 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Block Diagram
TRACESWO
BOOT0
BOOT1
SWCLK SWDIO
AF
Powered by VDD18
SW-DP
DCode
CortexTM-M3
Processor
Flash Memory
Interface
fMax: 72 MHz
CKCU/RSTCU
Control Registers
CRC
-16/32
USB
Control/Data
Registers
PDMA
CAP.
BOD
LVD
USB
Device
Powered by VDD33
AF
AF
I2S
SPI1
AFIO
I2C 0 ~ 1
BFTM 0 ~ 1
...
AF
Analog
CMP
RTCOUT
VBAT
VBAK
PWRCU
VDD33
VSS33
OPA/CMP
PORB
LSI
32 kHz
LSE
WAKEUP
32,768 Hz
nRST
Backup Domain
Powered by VDD18
AF
VBAK 3.3 V
BREG
Powered by VDDA
CLK, DIO,
DET
PWRSW
ADC
VDDA
VSSA
CH3 ~ CH0
ETI
AF
AF
RTC
12-bit
SAR ADC
SDA
SCL
AF
SCI
TX, RX
MOSI, MISO
SCK, SEL
Power control
APB1
AF
MCTM1
GPTM 0 ~ 1
APB0
MCTM0
TX, RX
RTS/TXE
CTS/SCK
AF
UART1
DP
DM
AF
AF
SPI0
AD0~AD15
A0~A24
CS0~CS3
OE, WR
ALE, RDY
BL0~BL1
AF
USART1
ADC_IN11
CN0, CP0
COUT0
CN1, CP1
COUT1
CLDO
1.8 V
UART0
AF
ADC_IN0
LDO
WDT
EXTI
CH0 ~CH2
CH0N ~ CH2N
CH3, ETI, BRK
VSS33
AF
DMA request
AHB to APB
Bridge
XTALIN
XTALOUT
VDD33
HSI
8 MHz
USART0
MCLK, BCLK
WS, SDO, SDI
CH0 ~CH2
CH0N ~ CH2N
CH3, ETI, BRK
SRAM
External Bus
Interafce
8 Channels
4 ~ 16 MHz
Clock and reset control
Bus Matrix
System
Interrupt request
SRAM
Controller
HSE
AF
GPIO
A~D
Control
Registers
AF
MOSI, MISO
SCK, SEL
FMC
AHB
Peripherals
PDMA
AF
TX, RX
PLL
AF
TX, RX
RTS/TXE
CTS/SCK
1.8 V
fMax: 144 MHz
Control
Registers
NVIC
POR
Flash
Memory
AF
XTAL32KIN
XTAL32KOUT
Power supply:
Bus:
Control signal:
Alternate function:
AF
Figure 1 HT32F1654/1653 Block Diagram
Rev. 1.00
20 of 46
January 28, 2015
Overview
ICode
TPIU
PA ~ PD15:0]
AF
AF
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Memory Map
0xFFFF_FFFF
Reserved
0x400F_FFFF
0xE010_0000
0x7000_0000
Private peripheral bus
Reserved
EBI Selection Bank
0x6000_0000
0x4400_0000
Peripheral
0x4200_0000
0x4010_0000
0x4008_0000
0x4000_0000
0x2220_0000
64 MBytes
x4
Reserved
APB/AHB bit band alias
32 Mbytes
Reserved
AHB peripherals
512 Kbytes
APB peripherals
512 Kbytes
Reserved
SRAM bit band alias
SRAM
2 Mbytes
0x2200_0000
Reserved
0x2000_4000
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_2000
0x1F00_0000
Up to
16 KB on-chip SRAM
Up to
16 Kbytes
Reserved
Option byte alias
1 Kbytes
Reserved
Boot loader
8 Kbytes
Code
Reserved
0x0001_0000
Up to
64 KB on-chip Flash
Up to
64 Kbytes
0x0000_0000
0x4007_8000
0x4007_7000
0x4007_6000
0x4007_0000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_F000
0x4004_E000
0x4004_A000
0x4004_9000
0x4004_8000
0x4004_5000
0x4004_4000
0x4004_3000
0x4004_1000
0x4004_0000
0x4002_D000
0x4002_C000
0x4002_6000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_F000
0x4001_E000
0x4001_D000
0x4001_C000
0x4001_B000
0x4001_A000
0x4001_9000
0x4001_8000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_1000
0x4000_0000
Reserved
GPIOA~D
USB
EBI
PDMA
CRC-16/32
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM1
BFTM0
Reserved
GPTM1
GPTM0
Reserved
RTC/PWRCU
Reserved
WDT
Reserved
USB
Reserved
I2C1
I2C0
Reserved
SPI1
SCI
UART1
USART1
MCTM1
MCTM0
I2S
EXTI
Reserved
AFIO
AHB
APB1
APB0
Reserved
OPA/CMP
Reserved
ADC
Reserved
SPI0
UART0
USART0
Figure 2 HT32F1654/1653 Memory Map
Rev. 1.00
21 of 46
January 28, 2015
Overview
0xE000_0000
0x400B_0000
0x400A_8000
0x4009_8000
0x4009_0000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Clock Structure
Prescaler
÷1 ~ 32
CK_LSE
HSI Auto
Trimming
Controller
Divider
÷2
CK_REF
CKREFPRE
CKREFEN
USB Frame Pulse
fCK_USB,max = 48MHz
Prescaler
÷1, 2, 3
1
HSIEN
PLLEN
f CK_PLL,max = 144MHz
SW[1:0]
0x
CK_HSI
11
CK_HSE
CK_SYS
CK_LSE
LSEEN(Note1)
32 kHz
LSI RC
GPIOEEN
AHB
Prescaler
÷ 1,2,4,8
FCLK
( free running clock)
10
HCLKC
( to CortexTM-M3)
CM3EN
(control by HW)
CK_AHB
Clock
Monitor
32.768 kHz
LSE OSC
CK_GPIO
( to GPIO port)
GPIOAEN
fCK_SYS,max = 144MHz
4-16 MHz
HSE XTAL
HSEEN
STCLK
(to SysTick)
÷8
CK_PLL
PLL
0
Overview
PLLSRC
8 MHz
HSI RC
CK_USB
USBEN
DMAEN
HCLKD
( to PDMA)
EBIEN
CK_EBI
( to EBI)
CRCEN
CK_CRC
( to CRC)
WDTSRC
1
0
CK_LSI
CK_WDT
WDTEN
RTCSRC(Note1)
LSIEN(Note1)
HCLKF
( to Flash)
CM3EN
1
0
CK_RTC
FMCEN
HCLKS
( to SRAM)
(Note1)
RTCEN
CM3EN
SRAMEN
CKOUTSRC[2:0]
CKOUT
HCLKBM
( to Bus Matrix)
000
CK_REF
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
CM3EN
BMEN
HCLKAPB0
( to APB0 Bridge)
CM3EN
APB0EN
HCLKAPB1
( to APB1 Bridge)
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
Note 1: Those control bits are located at RTC Control Register
(RTC_CTRL)
CM3EN
APB1EN
PCLK
Peripherals
Clock
Prescaler
÷ 1,2,4,8
00
PCLK/2
01
PCLK/4
10
PCLK/8
11
PCLK ( OPAx, AFIO,
ADC, SPIx, USARTx,
UARTx, I2Cx, I2S,
GPTMx, MCTMx,
BFTMx, EXTI, RTC,
SCI, WDT)
SPIEN
SCIEN
ADC
Prescaler
÷ 2,4,6,8,16...
CK_ADC IP
ADCEN
Figure 3 HT32F1654/1653 Clock Structure
Rev. 1.00
22 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
4
Pin Assignment
Holtek HT32F1654/1653
48 LQFP-A
�
33V
PA�
6
33V
PA6
7
33V
PA7
�
33V
1�
USB
39
3�
37
AP
AP
33V
33V
33V
33V
33V
33V
�VT
�VT
�VT
�VT
P33
3.3 V Digital Powe� Pad
AP
3.3 V Analog Powe� Pad
P1�
1.� V Powe� Pad
33V
3.3 V I/O Pad
�VT
� V Tole�ance I/O Pad
�VT
High C���ent O�tp�t
� V Tole�ance I/O Pad
USB
USB PHY Pad
�VT
�VT
1�
19
�0
�1
��
�3
�4
P33
13
14
1�
16
17
AF1
P33
36
VSS33_3
P33
3�
VDD33_3
�VT
34
PB1
�VT
33
PB0
�VT
3�
PA1�
�VT
31
PA14
�VT
30
SWDIO
PA13
�VT
�9
SWCLK
PA1�
�VT
�� TRACESWO
�VT
�7
�VT
�6
�VT
��
PA11
PA10
PA9_
BOOT1
PA�_
BOOT0
PC14
PC13
AF1
33V
P33
AF0
(Defa�lt)
AF0
(Defa�lt)
33V
P1�
XTAL3�K
OUT
XTAL3�KI
N
BAK
�VT
VBAT
BAK
33V
nRST
BAK
33V
VSS33_�
BAK
P33
BAK
�VT
VDD33_�
Back�p Domain Pad
CLDO
BAK
PD�
USB
40
PD1
11
41
PB1�
P33
4�
XTALOUT
10
USBDM
/PB1�
USBDP
/PB13
43
PB14
VSS33_1
44
XTALIN
P33
4�
PC1�
9
46
RTCOUT
VDD33_1
47
Figure 4 HT32F1654/1653 LQFP-48 Pin Assignment
Rev. 1.00
23 of 46
January 28, 2015
Pin Assignment
PA4
4�
AF0
(Defa�lt)
33V
PB�
4
PB3
PA3
PB4
33V
PB�
3
PB6
PA�
PB7
33V
PB�
�
PB9
PA1
PB10
33V
PB11
1
VDDA
PA0
VSSA
AF0
(Defa�lt)
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Holtek HT32F1653/1654
64 LQFP-A
PB11
PB10
PB9
PB�
PB7
PB6
VSS33_4
VDD33_4
PC�
PC7
PB�
PB4
PB3
PB�
63
6�
61
60
�9
��
�7
�6
��
�4
�3
��
�1
�0
49
AP
AP
AF0
(Defa�lt)
AF1
33V 33V 33V 33V 33V 33V P33 P33 �VT �VT �VT �VT �VT �VT
PA0
1
33V
�VT
4�
PC6
PA1
�
33V
�VT
47
PC�
PA�
3
33V
�VT
46
PC4
PA3
4
33V
�VT
4�
PB1
PA4
�
33V
�VT
44
PB0
PA�
6
33V
P33
43
VSS33_3
PA6
7
33V
P33
4�
VDD33_3
PA7
�
33V
�VT
41
PA1�
VDD33_1
9
P33
�VT
40
PA14
VSS33_1
10
P33
�VT
39
SWDIO
PA13
PC9
11
33V
�VT
3�
SWCLK
PA1�
PC10
1�
33V
�VT
37
TRACESWO
PA11
PC11
13
33V
�VT
36
PA10
PC1�
14
33V
�VT
3�
1�
USB
�VT
34
16
USB
�VT
33
USBDM
/PB1�
USBDP
/PB13
P33
3.3 V Digital Powe� Pad
AP
3.3 V Analog Powe� Pad
P1� 1.� V Powe� Pad
33V 3.3 V I/O Pad
�VT � V Tole�ance I/O Pad
�VT
High C���ent O�tp�t
� V Tole�ance I/O Pad
USB USB PHY Pad
BAK Back�p Domain Pad
PA9_
BOOT1
PA�_
BOOT0
PC3
BAK BAK BAK BAK BAK
P1� P33 P33 �VT P33 33V 33V �VT �VT 33V 33V �VT �VT �VT �VT �VT
VBAT
XTAL3�KIN
XTAL3�KOUT
RTCOUT
PC13
PC14
PC1�
�9
30
31
3�
AF1
nRST
��
AF0
(Defa�lt)
VSS33_�
�7
PC�
VDD33_�
�6
PC1
CLDO
��
PC0
�4
PD�
�3
PD1
��
PB1�
�1
XTALOUT
�0
PB14
19
XTALIN
1�
PD0
17
Figure 5 HT32F1654/1653 LQFP-64 Pin Assignment
Rev. 1.00
24 of 46
January 28, 2015
Pin Assignment
VDDA
64
AF0
(Defa�lt)
VSSA
AF0
(Defa�lt)
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Table 2 HT32F1654/1653 Series Pin Assignment for LQFP 64 / 48 Package
Alternate function number
Package
LQFP LQFP
-64
-48
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
System
Default
GPIO
ADC
CMP
MCTM
/GPTM
SPI
USART
/UART
I2C
SCI
EBI
I2S
1
PA0
ADC_
IN0
GT1_
CH0
USR0_
RTS
I2C1_
SCL
SCI_
CLK
I2S
_WS
2
2
PA1
ADC_
IN1
GT1_
CH1
USR0_
CTS
I2C1_
SDA
SCI_
DIO
I2S
_BCLK
3
3
PA2
ADC_
IN2
GT1_
CH2
USR0_
TX
I2S
_SDO
4
4
PA3
ADC_
IN3
GT1_
CH3
USR0_
RX
I2S
_SDI
5
5
PA4
ADC_
IN4
GT0_
CH0
SPI0_
SCK
USR1_
TX
I2C0_
SCL
6
6
PA5
ADC_
IN5
GT0_
CH1
SPI0_
MOSI
USR1_
RX
I2C0_
SDA
7
7
PA6
ADC_
IN6
GT0_
CH2
SPI0_
MISO
USR1_
RTS
8
8
PA7
ADC_
IN7
GT0_
CH3
SPI0_
SEL
USR1_
CTS
9
9
VDD33_1
10
10
VSS33_1
PC9
ADC_
IN8
GT0_
CH0
SPI1_
SEL
UR0_
TX
I2C1_
SCL
EBI
_A19
12
PC10
ADC_
IN9
GT0_
CH1
SPI1_
SCK
UR0_
RX
I2C1_
SDA
EBI
_A20
13
PC11
ADC_
IN10
GT0_
CH2
SPI1_
MOSI
EBI
_A0
14
PC12
ADC_
IN11
GT0_
CH3
SPI1_
MISO
EBI
_A1
11
PB12
15
11
USBDM
16
12
USBDP
16
12
PB13
17
13
CLDO
18
14
VDD33_2
19
15
VSS33_2
20
16
nRST
21
17
VBAT
22
18
XTAL32KIN
PC13
23
19
XTAL32KOUT
PC14
24
20
RTCOUT
PC15
_WAKEUP
25
PD0
MT1_
CH2
I2C0_
SCL
MT1_
CH2N
I2C0_
SDA
MT1_
ETI
I2C0_
SDA
EBI_
A18
I2S_
SDI
I2S_
MCLK
26
21
XTALIN
PB14
27
22
XTALOUT
PB15
28
23
PD1
MT1_
CH0
SPI0_
SEL
I2C1_
SCL
EBI_
A16
29
24
PD2
MT1_
CH0N
SPI0_
SCK
I2C1_
SDA
EBI_
A17
30
PC0
GT1_
CH0
SPI1_
SEL
EBI_
AD13
I2S_
WS
31
PC1
GT1_
CH1
SPI1_
SCK
EBI_
AD14
I2S_
BCLK
32
PC2
GT1_
CH2
SPI1_
MOSI
UR1_
TX
I2C0_
SCL
EBI_
AD15
I2S_
SDO
33
PC3
GT1_
CH3
SPI1_
MISO
UR1_
RX
I2C0_
SDA
EBI_
CS3
I2S_
SDI
Rev. 1.00
25 of 46
N/A
N/A
N/A
AF15
System
Other
I2S
_MCLK
11
15
N/A
Pin Assignment
1
AF11 AF12 AF13 AF14
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Alternate function number
Package
AF0
AF1
AF2
AF3
AF4
AF5
GT0_
ETI
25
PA8_BOOT0
35
26
PA9_BOOT1
36
27
PA10
37
28
TRACESWO
PA11
38
29
SWCLK
PA12
39
30
SWDIO
PA13
40
31
41
32
AF6
AF7
AF8
AF9
USR0_
TX
I2S_
MCLK
SPI0_
MOSI
MT1_
CH1
USR0_
RX
EBI_
A1
I2S_
WS
EBI_
A0
I2S_
MCLK
SPI0_
MISO
PA14
MT0_
CH0
SPI1_
SEL
USR1_
TX
SCI_
CLK
EBI_
AD0
PA15
MT0_
CH0N
SPI1_
SCK
USR1_
RX
SCI_
DIO
EBI_
AD1
42
VDD33_3
VSS33_3
44
33
PB0
MT0_
CH1
SPI1_
MOSI
USR0_
TX
I2C0_
SCL
EBI_
AD2
45
34
PB1
MT0_
CH1N
SPI1_
MISO
USR0_
RX
I2C0_
SDA
EBI_
AD3
46
PC4
MT1_
CH2
USR1_
RTS
SCI_
CLK
EBI_
AD10
47
PC5
MT1_
CH2N
USR1_
CTS
SCI_
DIO
EBI_
AD11
48
PC6
MT1_
CH3
SCI_
DET
EBI_
AD12
35
VDD33_3
36
VSS33_3
49
37
PB2
MT0_
CH2
SPI0_
SEL
UR0_
TX
EBI_
AD4
50
38
PB3
MT0_
CH2N
SPI0_
SCK
UR0_
RX
EBI_
AD5
51
39
PB4
MT0_
BRK
SPI0_
MOSI
UR1_
TX
EBI_
AD6
52
40
PB5
MT1_
BRK
SPI0_
MISO
UR1_
RX
EBI_
AD7
53
PC7
MT0_
CH3
I2C0_
SCL
EBI_
AD8
54
PC8
MT0_
ETI
I2C0_
SDA
EBI_
AD9
55
VDD33_4
56
VSS33_4
57
41
PB6
CN0
MT1_
CH0
SPI1_
SEL
58
42
PB7
CP0
MT1_
CH0N
SPI1_
SCK
59
43
PB8
COUT0
GT1_
ETI
SPI1_
MOSI
UR1_
RX
EBI_
WE
60
44
PB9
CN1
MT1_
CH2
SPI1_
MISO
UR0_
TX
EBI_
ALE
I2S_
BCLK
61
45
PB10
CP1
MT1_
CH2N
I2C1_
SCL
EBI_
CS1
I2S_
SDO
62
46
PB11
COUT1
MT1_
CH3
I2C1_
SDA
EBI_
CS2
I2S_
SDI
63
47
VDDA
64
48
VSSA
Rev. 1.00
AF11 AF12 AF13 AF14
AF15
CKOUT
SCI_
DET
MT1_
CH1N
43
AF10
UR1_
TX
EBI_
OE
TRACESWO
Pin Assignment
34
I2S_
MCLK
EBI_
CS0
UR0_
RX
26 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Table 3 HT32F1654/1653 Pin Description
Pin number
(Note1)
(Note2)
Output
Driving
AI/O
33V
4/8mA
PA0
AI/O
33V
4/8mA
PA1
AI/O
33V
4/8mA
PA2
33V
4/8mA
PA3
AI/O
33V
4/8mA
PA4
AI/O
33V
4/8mA
PA5
Pin Name
2
2
PA1
3
3
PA2
4
4
PA3
AI/O
5
5
PA4
6
6
PA5
Default function (AF0)
Pin Assignment
LQFP
48
1
PA0
Description
IO
Structure
Type
LQFP
64
1
7
7
PA6
AI/O
33V
4/8mA
PA6
8
8
PA7
AI/O
33V
4/8mA
PA7
9
9
VDD33_1
P
—
—
3.3 V voltage for digital I/O
10
10
Ground reference for digital I/O
VSS33_1
P
—
—
11
PC9
AI/O
33V
4/8mA
PC9
12
PC10
AI/O
33V
4/8mA
PC10
13
PC11
AI/O
33V
4/8mA
PC11
14
PC12
AI/O
33V
4/8mA
PC12
PB12
15
11
PB12
I/O
5VT
8mA
15
11
USBDM
AI/O
—
—
USB Differential data bus conforming to the
Universal Serial Bus standard.
16
12
USBDP
AI/O
—
—
USB Differential data bus conforming to the
Universal Serial Bus standard.
16
12
PB13
I/O
5VT
8mA
PB13
17
13
CLDO
P
—
—
Core power LDO 1.8 V output
It is recommended to connect a 4.7uF capacitor
as close as possible between this pin and
VSS33_2.
18
14
VDD33_2
P
—
—
3.3 V voltage for digital I/O
19
15
VSS33_2
P
—
—
Ground reference for digital I/O
I
(BK)
5VT_PU
—
External reset pin and external wakeup pin in
the Power-Down mode
Battery power input for the backup domain
20
16
nRST
21
17
VBAT
P
—
—
33V
1mA
XTAL32KIN
22
18
PC13Note 4
AI/O
(BK)
23
19
PC14 Note 4
AI/O
(BK)
33V
1mA
XTAL32KOUT
24
20
PC15 Note 4
I/O
(BK)
5VT
1mA
RTCOUT
PD0
I/O
5VT
8mA
PD0
26
21
PB14
AI/O
33V
4/8mA
XTALIN
27
22
PB15
AI/O
33V
4/8mA
XTALOUT
28
23
PD1
I/O
5VT
8mA
PD1
29
24
PD2
I/O
5VT
8mA
PD2
30
PC0
I/O
5VT
12mA
PC0
31
PC1
I/O
5VT
12mA
PC1
32
PC2
I/O
5VT
12mA
PC2
33
PC3
I/O
5VT
12mA
PC3
25
Rev. 1.00
27 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Pin number
Description
(Note1)
IO
Structure
(Note2)
Output
Driving
I/O
5VT_PU
12mA
PA8_BOOT0
PA9
I/O
5VT_PU
12mA
PA9_BOOT1
PA10
I/O
5VT
8mA
PA10
LQFP
64
LQFP
48
Pin Name
34
25
PA8
35
26
36
27
Type
Default function (AF0)
28
PA11
I/O
5VT
8mA
TRACESWO
29
PA12
I/O
5VT_PU
8mA
SWCLK
39
30
PA13
I/O
5VT_PU
8mA
SWDIO
40
31
PA14
I/O
5VT
12mA
PA14
41
32
PA15
I/O
5VT
12mA
PA15
42
VDD33_3
P
—
—
3.3 V voltage for digital I/O
43
VSS33_3
P
—
—
Ground reference for digital I/O
PB0
I/O
5VT
12mA
PB0
44
33
45
34
PB1
I/O
5VT
12mA
PB1
46
PC4
I/O
5VT
8mA
PC4
47
PC5
I/O
5VT
8mA
PC5
PC6
48
PC6
I/O
5VT
8mA
35
VDD33_3
P
—
—
3.3 V voltage for digital I/O
Ground reference for digital I/O
36
VSS33_3
P
—
—
49
37
PB2
I/O
5VT
12mA
PB2
50
38
PB3
I/O
5VT
12mA
PB3
51
39
PB4
I/O
5VT
12mA
PB4
52
40
PB5
I/O
5VT
12mA
PB5
53
PC7
I/O
5VT
8mA
PC7
54
PC8
I/O
5VT
8mA
PC8
55
VDD33_4
P
—
—
3.3 V voltage for digital I/O
Ground reference for digital I/O
56
VSS33_4
P
—
—
57
41
PB6
AI/O
33V
4/8mA
PB6
58
42
PB7
AI/O
33V
4/8mA
PB7
59
43
PB8
AI/O
33V
4/8mA
PB8
60
44
PB9
AI/O
33V
4/8mA
PB9
61
45
PB10
AI/O
33V
4/8mA
PB10
62
46
PB11
AI/O
33V
4/8mA
PB11
63
47
VDDA
P
—
—
3.3 V analog voltage for ADC and Comparator
64
48
VSSA
P
—
—
Ground reference for the ADC and Comparator
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, BK = Back-up domain
2. 5VT = 5 V tolerant; 33V = 3.3 V tolerant.
3. The GPIOs are in an AF0 state after a VDD18 power on reset (POR) except for the RTCOUT pin in the
Backup Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or by the
Backup Domain software reset (BAK_RST bit in BAK_CR register).
4. The backup domain of the I/O pins have a source current capability limitation of <1 mA @ VBAT = 3.3V and
sink current typical is 4 mA @ VBAT = 3.3V.
Rev. 1.00
28 of 46
January 28, 2015
Pin Assignment
37
38
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
5
Electrical Characteristics
Absolute Maximum Ratings
Table 4 Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD33
External main supply voltage
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VLDOIN
External LDO supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5 V-tolerant I/O
VSS - 0.3
VSS + 5.5
V
Input voltage on other I/O
VIN
VSS - 0.3
VDD33 + 0.3
V
TA
Ambient operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
PD
Total power dissipation
—
500
mW
VESD
Electrostatic discharge voltage - human body mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 5 Recommended DC Operating Conditions
Symbol
VDD33
Parameter
I/O operating voltage
VDDA
VBAT
VLDOIN
TA = 25°C, unless otherwise specified.
Conditions
Min
2.7
Typ
3.3
Max
3.6
Unit
V
Analog operating voltage
2.7
3.3
3.6
V
Battery supply operating voltage
2.7
3.3
3.6
V
LDO operating voltage
2.7
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 6 LDO Characteristics
Symbol
VLDOOUT
Rev. 1.00
Parameter
Internal regulator output
voltage
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max Unit
VDD33 = 3.3 V Regulator input
1.71
1.8
1.89
V
VDD33 = 2.7 V Regulator input
—
—
200
mA
2.2
—
10
μF
ILDOOUT
Output current
CLDO
The capacitor value is depenExternal filter capacitor value
dent on the core power curfor internal core power supply
rent consumption
29 of 46
January 28, 2015
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Power Consumption
Table 7 Power Consumption Characteristics
Symbol
Parameter
Conditions
VDD33 = VBAT = 3.3 V, HSE = 8MHz,
PLL = 144 MHz, fHCLK = 72 MHz,
fPCLK = 72 MHz, All peripherals enabled
Typ Max Unit
—
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz,
PLL = 144 MHz, fHCLK = 72 MHz,
fPCLK = 72 MHz, All peripherals disabled
—
33
—
mA
VDD = VBAT = 3.3 V, HSE = 8MHz,
PLL = 144 MHz, fHCLK = 0 MHz,
fPCLK = 72 MHz, All peripherals enabled
—
55
—
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz,
PLL = 144 MHz, fHCLK = 0 MHz,
fPCLK = 72 MHz, All peripherals disabled
—
10
—
mA
VDD33 = VBAT = 3.3 V, All clock off
Supply current
(HSE/PLL/fHCLK), LDO in low power mode,
(Deep-Sleep1 mode)
LSI on, RTC on
—
63
—
μA
VDD33 = VBAT = 3.3 V, All clock off
Supply current
(HSE/PLL/fHCLK), LDO off (DMOS on),
(Deep-Sleep2 mode)
LSI on, RTC on
—
22
—
μA
—
-
—
μA
—
-
—
μA
—
-
—
μA
—
5
—
μA
—
4
—
μA
—
3.9
—
μA
VDD33 = VBAT = 3.3 V, LDO off,
LSE on, LSI off, RTC on
VDD33 = VBAT = 3.3 V, LDO off,
LSE on, LSI off, RTC off
Supply current
(Power-Down mode) VDD33 = VBAT = 3.3 V, LDO off,
LSE off, LSI on, RTC on
VDD33 = VBAT = 3.3 V, LDO off,
LSE off, LSI on, RTC off
VDD33 not present, VBAT = 3.3 V,
Battery supply
LDO off, LSE off, LSI on, RTC on
current (Power-Down
VDD33 not present, VBAT = 3.3 V,
mode)
LDO off, LSE off, LSI on, RTC off
Note: 1. HSE means high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means low speed external oscillator. LSI means 32.768KHz low speed internal
oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
Rev. 1.00
30 of 46
January 28, 2015
Electrical Characteristics
76
Supply current
(Sleep mode)
IBAT
Min
—
Supply current
(Run mode)
IDD
TA = 25°C, unless otherwise specified.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Reset and Supply Monitor Characteristics
Table 8 LVD/BOD Characteristics
Symbol
VBOD
TA = 25°C, unless otherwise specified.
Parameter
LVDS
Typ
Max
Unit
—
2.6
—
V
—
2.7
—
V
—
2.8
—
V
Voltage of Low Voltage Detector
(Note1)
= ‘010’
—
2.9
—
V
LVDS (Note1) = ‘011’
—
3.0
—
V
LVDS (Note1) = ‘100’
—
3.1
—
V
LVDS (Note1) = ‘101’
—
3.2
—
V
= ‘110’
—
3.4
—
V
LVDS (Note1) = ‘111’
—
3.5
—
V
—
1.36
—
V
Power On Reset Voltage
(Note1)
(Note1)
—
Note: LVDS field is in PWRCU LVDCSR register
External Clock Characteristics
Table 9 High Speed External Clock (HSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Rev. 1.00
Parameter
Conditions
Min
Typ
Max
Unit
VDD33 = 3.3 V
4
—
16
MHz
fHSE
High Speed External oscillator
frequency (HSE)
CHSE
Recommended load capacitance
on XTALIN and XTALOUT pins
—
—
TBD
—
pF
RFHSE
Recommended external
feedback resistor between
XTALIN and XTALOUT pins
—
—
1.0
—
MΩ
DHSE
HSE oscillator Duty cycle
—
40
—
60
%
IDDHSE
HSE oscillator current
consumption
VDD33 = 3.3 V, TA = 25°C
—
0.96
—
mA
ISTBHSE
HSE oscillator standby current
VDD33 = 3.3 V, TA = 25°C
—
—
0.1
μA
tSUHSE
HSE oscillator startup time
VDD33 = 3.3 V, TA = 25°C
—
—
4
ms
31 of 46
January 28, 2015
Electrical Characteristics
= ‘000’
LVDS
VPOR
Min
—
LVDS (Note1) = ‘001’
LVDS
VLVD
Conditions
Brown Out Detector Voltage
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Table 10 Low Speed External Clock (LSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
fLSE
Parameter
Low Speed External oscillator
frequency (LSE)
Conditions
VDD33 = VBAT = 3.3 V
Min
Typ
Max Unit
—
32.768
—
kHz
Recommended load capacitance on
XTAL32KIN and XTAL32KOUT pins
—
—
TBD
—
pF
RFLSE
Recommended external feedback
resistor between XTAL32KIN and
XTAL32KOUT pins
—
—
10
—
MΩ
DLSE
LSE oscillator Duty cycle
40
—
60
%
—
1.7
—
μA
IDDLSE
LSE Oscillator Operating current
VDD33 = VBAT = 3.3 V,
LSESM = 0
(Normal startup mode)
ISTBLSE
LSE Oscillator Standby current
VDD33 = VBAT = 3.3 V,
LSESM = 1
(Fast startup mode)
—
3
8
μA
tSULSE
LSE Oscillator Startup time
VDD33 = VBAT = 3.3 V,
LSESM = 1
(Fast startup mode)
—
200
—
ms
Note: The following PCB layout guidelines are recommended to increase the stability of the crystal circuit for the HSE/LSE clock:
■■ The crystal oscillator should be located as close as possible to the MCU to minimise trace length
thus reducing parasitic capacitance.
■■ Use a ground plane as a shield under the crystal circuit to reduce the effects of noise
interference..
■■ Route high frequency signals away from crystal oscillator area to prevent crosstalk.
Internal Clock Characteristics
Table 11 High Speed Internal Clock (HSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
fHSI
Parameter
High Speed Internal Oscillator
Frequency (HSI)
Conditions
VDD33 = 3.3 V,
TA = -40°C ~ +85°C
Min
Typ
Max
Unit
—
8
—
MHz
—
+5
%
ACCHSI
Factory-trimmed,
HSI Oscillator Frequency accuracy VDD33 = 3.3 V,
TA = -40°C ~ +85°C
-5
DHSI
HSI Oscillator Duty cycle
VDD33 = 3.3 V, fHSI = 8 MHz
35
—
65
%
IDDHSI
HSI Oscillator current
VDD33 = 3.3 V, fHSI = 8 MHz
—
0.92
—
mA
tSUHSI
HSI Oscillator Startup time
VDD33 = 3.3 V, fHSI = 8 MHz,
HSIRCBL = 0 (HSI Ready
Counter Bits Length 7 Bits )
—
17
—
μs
Note: HSIRCBL field is in PWRCU HSIRCR register
Rev. 1.00
32 of 46
January 28, 2015
Electrical Characteristics
CLSE
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Table 12 Low Speed Internal Clock (LSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Conditions
VDD33 = VBAT = 3.3 V,
TA = -40°C ~ +85°C
IDDLSI
LSI Oscillator Operating current
tSULSI
LSI Oscillator startup time
fLSI
Min
Typ
Max
Unit
25
32
43
kHz
VDD33 = VBAT = 3.3 V,
TA = 25°C
—
1.0
2
μA
VDD33 = VBAT = 3.3 V,
TA = 25°C
—
35
—
ms
PLL Characteristics
Table 13 PLL Characteristics
Symbol
TA = 25°C, unless otherwise specified.
fPLLIN
Parameter
PLL input clock
Conditions
—
Min
4
Typ
—
Max
16
Unit
MHz
fCK_PLL
PLL output clock
—
8
—
144
MHz
tLOCK
PLL lock time
—
—
TBD
—
ms
Memory Characteristics
Table 14 Flash Memory Characteristics
Symbol
Parameter
Conditions
Number of guaranteed program/
erase cycles before failure.
TA = -40°C ~ +85°C
(Endurance)
Min
Typ
Max
Unit
20
—
—
K
cycles
TRET
Data retention time
TA = 25°C
100
—
—
Years
tPROG
Word programming time
TA = -40°C ~ +85°C
20
—
40
μs
tERASE
Page erase time
TA = -40°C ~ +85°C
20
—
40
ms
tMERASE
Mass erase time
TA = -40°C ~ +85°C
20
—
40
ms
NENDU
Rev. 1.00
TA = 25°C, unless otherwise specified.
33 of 46
January 28, 2015
Electrical Characteristics
Parameter
Low Speed Internal Oscillator
Frequency (LSI)
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
I/O Port Characteristics
Table 15 I/O Port Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Min
Typ
Max
Unit
VI = 0 V,
5 V-tolerant IO On-chip pull-up
resister disabled.
Reset pin
—
—
3
IIL
IIH
VIL
VIH
VHYS
IOL
IOH
VOL
Rev. 1.00
Low level input current
μA
—
—
3
μA
—
—
3
μA
3.3 V IO
—
—
3
μA
High level input current
—
—
3
μA
—
—
3
μA
3.3 V IO
-0.3
—
0.8
V
Low level input voltage
5 V-tolerant IO
-0.3
—
0.8
V
Reset pin
-0.3
—
0.8
V
3.3 V IO
2
—
3.6
V
High level input voltage
5 V-tolerant IO
2
—
5.5
V
Reset pin
2
—
5.5
V
Schmitt trigger input
voltage hysteresis
Low level output current
(GPIO Sink current)
High level output current
(GPIO Source current)
Low level output voltage
VI = VDD33,
5 V-tolerant IO On-chip pull-down
resister disabled.
Reset pin
3.3 V IO
—
400
—
mV
5 V-tolerant IO
—
400
—
mV
Reset pin
—
400
—
mV
3.3 V IO 4 mA drive, VOL = 0.4 V
4
—
—
mA
3.3 V IO 8 mA drive, VOL = 0.4 V
8
—
—
mA
5 V-tolerant IO 8 mA drive,
VOL = 0.4 V
8
—
—
mA
5 V-tolerant IO 12 mA drive,
VOL = 0.4 V
12
—
—
mA
Backup Domain IO drive
@ VBAT = 3.3 V,
VOL = 0.4 V, PC13, PC14, PC15.
—
4
—
mA
3.3 V I/O 4 mA drive,
VOH = VDD33 - 0.4 V
4
—
—
mA
3.3 V I/O 8 mA drive,
VOH = VDD33 - 0.4 V
8
—
—
mA
5 V-tolerant I/O 8 mA drive,
VOH = VDD33 - 0.4 V
8
—
—
mA
5 V-tolerant I/O 12 mA drive,
VOH = VDD33 - 0.4 V
12
—
—
mA
Backup Domain IO drive
@ VBAT = 3.3 V, VOL = VDD33 - 0.4V,
PC13, PC14, PC15.
—
—
1
mA
3.3 V 4 mA drive IO, IOL = 4 mA
—
—
0.4
V
3.3 V 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
5 V-tolerant 8 mA drive IO,
IOL = 8 mA
—
—
0.4
V
5 V-tolerant 12 mA drive IO,
IOL = 12 mA
—
—
0.4
V
34 of 46
January 28, 2015
Electrical Characteristics
Conditions
3.3 V IO
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Symbol
VOH
Parameter
High level output voltage
Internal pull-up resistor
RPD
Internal pull-down resistor
Min
Typ
Max
Unit
3.3 V 4 mA drive IO, IOH = 4 mA
VDD33 0.4 V
—
—
V
3.3 V 8 mA drive IO, IOH = 8 mA
VDD33 0.4 V
—
—
V
5 V-tolerant 8 mA drive IO,
IOH = 8 mA
VDD33 0.4 V
—
—
V
5 V-tolerant 12 mA drive IO,
IOH = 12 mA
VDD33 0.4 V
—
—
V
3.3 V I/O
34
—
74
kΩ
5 V-tolerant I/O
38
—
89
kΩ
3.3 V I/O
29
—
86
kΩ
5 V-tolerant I/O
35
—
107
kΩ
ADC Characteristics
Table 16 ADC Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operating voltage
VDDA
Conditions
—
Min
2.7
—
0
—
—
Typ Max
3.3 3.6
VADCIN
A/D Converter input voltage range
VREF+
A/D Converter Reference voltage
IADC
Current consumption
VDDA = 3.3 V
—
1
TBD
mA
IADC_DN
Power down current consumption
VDDA = 3.3 V
—
1
10
μA
fADC
A/D Converter clock
—
0.7
—
14
MHz
fS
Sampling rate
—
0.05
—
1
MHz
fADCCONV
A/D Converter conversion time
—
—
14
—
1/fADC
Cycles
RI
Input sampling switch resistance
—
—
—
1
kΩ
—
—
5
pF
No pin/pad capacitance
included
—
VREF+
Unit
V
VDDA VDDA
V
V
CI
Input sampling capacitance
tSU
Startup up time
—
—
—
1
μs
N
Resolution
—
—
12
—
bits
INL
Integral Non-linearity error
fS = 1 MHz, VDDA = 3.3 V
—
±2
±5
LSB
DNL
Differential Non-linearity error
fS = 1 MHz, VDDA = 3.3 V
—
—
±1
LSB
EO
Offset error
—
—
—
±10
LSB
EG
Gain error
—
—
—
±10
LSB
Note: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input
stage where CI is the storage capacitor, RI is the resistance of the sampling switch and RS
is the output impedance of the signal source VS. Normally the sampling phase duration
is approximately, 1.5/fADC. The capacitance, CI, must be charged within this time frame
and it must be ensured that the voltage at its terminals becomes sufficiently close to VS for
accuracy. To guarantee this, RS may not have an arbitrarily large value.
Rev. 1.00
35 of 46
January 28, 2015
Electrical Characteristics
RPU
Conditions
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
SAR ADC
sample
RS
RI
Figure 6 ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and VREF) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
RS <
1.5
− RI
f ADC C I ln(2 N + 2 )
where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, Rs may be larger than the value indicated by the equation
above.
Rev. 1.00
36 of 46
January 28, 2015
Electrical Characteristics
CI
VS
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
Comparator Characteristics
Table 17 Comparator Characteristics
Symbol
Parameter
Operating voltage
VDDA
TA = -40°C ~ 85°C, unless otherwise specified.
Conditions
Comparator mode
Min
2.7
Typ Max Unit
3.3 3.6
V
Input Common Mode
Voltage Range
CP or CN
VSSA
—
VDDA
V
VIOS
Input offset voltage(Note)
TA = 25°C
-5
—
5
mV
No hysteresis
(CMPnHM [1:0] = 00)
—
0
—
mV
Low hysteresis
(CMPnHM [1:0] = 01)
—
30
—
mV
Middle hysteresis
(CMPnHM [1:0] = 10)
—
70
—
mV
High hysteresis
(CMPnHM [1:0] = 11)
—
100
—
mV
—
50
100
ns
—
2
5
us
Vhys
Input Hysteresis
tRT
High Speed mode
Response time
Input Overdrive = ±100mV
Low Speed mode
ICMP
Current Consumption
VDDA = 3.3 V
tCMPST
ICMP_DN
High Speed mode
—
100
uA
Low Speed mode
—
10
uA
Comparator Startup Time
Comparator enabled to output
valid.
—
—
50
us
Power Down Supply
Current
CMPEN = 0
CVREFEN = 0
CVREFOE=0
—
—
0.1
uA
Comparator Voltage Reference (CVR)
VCVR
Output Range
—
VSSA
—
VDDA
V
NBits
CVR Scaler Resolution
—
—
6
—
bits
tCVRST
Setting Time
CVR scaler setting time from
CVREF = “000000” to “111111”
—
—
100
us
ICVR
Current Consumption
VDDA = 3.3 V
CVREFEN=1, CMPREFOE=0
—
10
—
uA
CVREFEN=1, CVREFOE=1
—
20
40
uA
Note: Guaranteed by design, not tested in production.
GPTM/MCTM Characteristics
Table 18 GPTM/MCTM Characteristics
Symbol
Rev. 1.00
fTM
Parameter
Timer clock source for GPTM and MCTM
tRES
Timer resolution time
—
1
—
—
fEXT
External single frequency on channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer resolution
—
—
—
16
bits
37 of 46
Conditions
—
Min
—
Typ Max Unit
—
72 MHz
fTM
January 28, 2015
Electrical Characteristics
VIN
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
I2C Characteristics
Table 19 I2C Characteristics
Symbol
Standard
mode
Parameter
fSCL
SCL clock frequency
Min
—
Fast mode
Fast mode
plus
Max
100
Min
—
Max
400
Min
—
Max
1000
Unit
kHz
SCL clock high time
4.5
—
1.125
—
0.45
—
μs
SCL clock low time
4.5
—
1.125
—
0.45
—
μs
tFALL
SCL and SDA fall time
—
1.3
—
0.34
—
0.135
μs
tRISE
SCL and SDA rise time
tSU(SDA)
SDA data setup time
—
1.3
—
0.34
—
0.135
μs
500
—
125
—
50
—
ns
ns
tH(SDA)
SDA data hold time
0
—
0
—
0
—
tSU(STA)
START condition setup time
500
—
125
—
50
—
ns
tH(STA)
START condition hold time
0
—
0
—
0
—
ns
tSU(STO)
STOP condition setup time
500
—
125
—
50
—
ns
Note: 1. Guaranteed by design, not tested in production.
2. To achieve 100kHz standard mode, the peripheral clock frequency must be higher than
2MHz.
3. To achieve 400kHz fast mode, the peripheral clock frequency must be higher than 8MHz.
4. To achieve 1MHz fast mode plus, the peripheral clock frequency must be higher than
20MHz.
5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01
and COMB_FILTER_En is disabled.
tFALL
tRISE
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 7 I2C Timing Diagrams
Rev. 1.00
38 of 46
January 28, 2015
Electrical Characteristics
tSCL(H)
tSCL(L)
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
SPI Characteristics
Table 20 SPI Characteristics
Symbol
Parameter
SCK clock frequency
fSCK
Conditions
—
Min
—
Typ
—
Max
fPCLK/2
Unit
MHz
tSCK(H)
SCK clock high time
—
fPCLK/8
—
—
ns
tSCK(L)
SCK clock low time
—
fPCLK/8
—
—
ns
tV(MO)
Data output valid time
—
—
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
ns
SPI Slave mode
tSU(SEL)
SEL enable setup time
—
4 tPCLK
—
—
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI)
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI)
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI)
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI)
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 8 SPI Timing Diagrams - SPI Master Mode
Rev. 1.00
39 of 46
January 28, 2015
Electrical Characteristics
SPI Master mode
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
SEL
tSU(SEL)
tH(SEL)
tSCK
tSCK(H)
Electrical Characteristics
SCK
(CPOL=0)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MOSI
tH(SI)
LSB/MSB IN
MSB/LSB IN
tA(SO)
tV(SO)
tDIS(SO)
tH(SO)
LSB/MSB OUT
MSB/LSB OUT
MISO
Figure 9 SPI Timing Diagrams - SPI Slave Mode with CPHA=1
I2S Characteristics
Table 21 I2S Characteristics
Symbol
I2S Master mode
Parameter
Conditions
Min
Typ
Max
Unit
tWSD(MO)
WS output to BCLK delay
—
—
TBD
—
ns
tDOD(MO)
Data output to BCLK delay
—
—
TBD
—
ns
tDIS(MI)
Data input setup time
—
—
TBD
—
ns
tDIH(MI)
Data input hold time
—
—
TBD
—
ns
I2S Slave mode
Rev. 1.00
tBCH(SI)
BCLK high pulse width
—
—
TBD
—
ns
tBCL(SI)
BCLK low pulse width
—
—
TBD
—
ns
tWSS(SI)
WS input setup time
—
—
TBD
—
ns
tDOD(SO)
Data output to BCLK delay
—
—
TBD
—
ns
tDIS(SI)
Data input setup time
—
—
TBD
—
ns
tDIH(SI)
Data input hold time
—
—
TBD
—
ns
40 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
BCLK
tWSD(MO)
WS
Electrical Characteristics
tDOD(MO)
SDO
tDIS(MI)
tDIH(MI)
SDI
Figure 10 Timing of I2S Master Mode
tBCH(SI)
tBCL(SI)
BCLK
tWSS(SI)
WS
tDOD(SO)
SDO
tDIS(SI)
tDIH(SI)
SDI
Figure 11 Timing of I2S Slave Mode
Rev. 1.00
41 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
USB Characteristics
The USB interface is USB-IF certified - Full Speed.
Table 22 USB DC Electrical Characteristics
Symbol
Parameter
USB operating voltage
VDD33
Conditions
—
USBDP-USBDM
Min
3.0
Typ
—
Max
3.6
Unit
V
Differential input sensitivity
0.2
—
—
V
Common mode voltage range
—
0.8
—
2.5
V
VSE
Single-ended receiver threshold
—
0.8
—
2.0
V
VOL
Pad output low voltage
0
—
0.3
V
VOH
Pad output high voltage
2.8
—
3.6
V
VCRS
Differential output signal crosspoint voltage
1.3
—
2.0
V
ZDRV
Driver output resistance
—
—
10
—
Ω
CIN
Transceiver pad capacitance
—
—
—
20
pF
RL of 1.5 kΩ to VDD33
Note: 1. Guaranteed by design, not tested in production.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP pin should
be pulled up with a 1.5 kΩ external resistor to a 3.0-to-3.6 V voltage supply.
3. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which will experience degradation in the 2.7-to-3.0 V VDD33 voltage range.
4. RL is the load connected to the USB driver USBDP.
Rise Time
Fall Time
Tr
Tf
90%
90%
VCRS
10%
10%
Figure 12 USB Signal Rise Time and Fall Time and Cross-Point Voltage (VCRS) Definition
Table 23 USB AC Electrical Characteristics
Symbol
Parameter
Rise time
Tr
Rev. 1.00
Conditions
CL = 50 pF
Min
4
Typ
-
Max
20
Unit
ns
Tf
Fall time
CL = 50 pF
4
-
20
ns
Tr/f
Rise time / fall time matching
Tr/f = Tr / Tf
90
-
110
%
42 of 46
January 28, 2015
Electrical Characteristics
VDI
VCM
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
6
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the package information.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
43 of 46
January 28, 2015
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
48-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.0197 BSC
—
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
A
—
9.0 BSC
Max.
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.5 BSC
—
F
0.17
0.22
0.27
G
1.35
1.4
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
44 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654
64-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Nom.
Max.
A
—
0.354 BSC
—
B
—
0.276 BSC
—
C
—
0.354 BSC
—
D
—
0.276 BSC
—
E
—
0.016 BSC
—
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
―
7°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
—
9.0 BSC
—
B
—
7.0 BSC
—
C
—
9.0 BSC
—
D
—
7.0 BSC
—
E
—
0.4 BSC
—
0.23
F
0.13
0.18
G
1.35
1.4
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
―
7°
45 of 46
January 28, 2015
32-bit ARM® Cortex™-M3 MCU
HT32F1653/HT32F1654

Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
46 of 46
January 28, 2015