STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6 8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators Features ■ ■ Operating conditions – Operating power supply range 1.8 V to 3.6 V (down to 1.65 V at power down) – Temperature range: - 40 °C to 85 or 125 °C Low power features – 5 low power modes: Wait , Low power run (5.1 µA), Low power wait (3 µA), Active-halt with full RTC (1.3 µA), Halt (350 nA) – Dynamic consumption: 195 µA/MHz+440µA – Ultralow leakage per I/0: 50 nA – Fast wakeup from Halt: 4.7 µs ■ Advanced STM8 core – Harvard architecture and 3-stage pipeline – Max freq. 16 MHz, 16 CISC MIPS peak – Up to 40 external interrupt sources ■ Reset and supply management – Low power, ultrasafe BOR reset with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ■ Clock management – 1 to 16 MHz crystal oscillator – 32 kHz crystal oscillator – Internal 16 MHz factory-trimmed RC – Internal 38 kHz low consumption RC – Clock security system ■ Low power RTC – BCD calendar with alarm interrupt – Auto-wakeup from Halt w/ periodic interrupt ■ LCD: up to 4x28 segments w/ step-up converter ■ Memories – Up to 32 KB of Flash program memory and 1 Kbyte of data EEPROM with ECC, RWW – Flexible write and read protection modes – Up to 2 Kbytes of RAM ■ ■ LQFP48 UFQFPN48 UFQFPN32 CSP LQFP32 UFQFPN28 WLCSP28 ■ 12-bit ADC up to 1 Msps/25 channels – T. sensor and internal reference voltage ■ 2 Ultralow power comparators – 1 with fixed threshold and 1 rail to rail – Wakeup capability ■ Timers – Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder – One 16-bit advanced control timer with 3 channels, supporting motor control – One 8-bit timer with 7-bit prescaler – 2 watchdogs: 1 Window, 1 Independent – Beeper timer with 1, 2 or 4 kHz frequencies ■ Communication interfaces – Synchronous serial interface (SPI) – Fast I2C 400 kHz SMBus and PMBus – USART (ISO 7816 interface and IrDA) ■ Up to 41 I/Os, all mappable on interrupt vectors ■ Up to 16 capacitive sensing channels with free firmware ■ Development support – Fast on-chip programming and non intrusive debugging with SWIM – Bootloader using USART ■ 96-bit unique ID Table 1. Device summary Reference Part number DMA – 4 channels; supported peripherals: ADC, DAC, SPI, I2C, USART, timers – 1 channel for memory-to-memory STM8L151xx (without LCD) STM8L151C6, STM8L151C4, STM8L151K6, STM8L151K4, STM8L151G6, STM8L151G4 12-bit DAC with output buffer STM8L152xx (with LCD) STM8L152C6, STM8L152C4, STM8L152K6, STM8L152K4 July 2010 Doc ID 15962 Rev 5 1/122 www.st.com 1 Contents STM8L151xx, STM8L152xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 20 3.13 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 3.15 2/122 3.2.1 3.13.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 3.16 4 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 Contents System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 64 9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.3.8 LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Doc ID 15962 Rev 5 3/122 Contents STM8L151xx, STM8L152xx 9.4 10 9.3.9 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.12 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8L15x low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Legend/abbreviation for table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 73 Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 77 Total current consumption and timing in Halt mode at VDD = 2 V . . . . . . . . . . . . . . . . . . . 77 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 88 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Doc ID 15962 Rev 5 5/122 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/122 STM8L151xx, STM8L152xx Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 104 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 UFQFPN28 – 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 WLCSP28 – 28-pin wafer level chip scale package, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 LQFP32 – 32-pin low profile quad flat package, package mechanical data . . . . . . . . . . . 116 UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP48 – 48-pin low profile quad flat package (7x7), package mechanical data . . . . . . 118 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM8L15xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STM8L15x clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM8L151Gx UFQFPN 28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM8L151Gx WLCSP28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STM8L151Kx 32-pin package pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM8L152Kx 32-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM8L151Cx 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STM8L152Cx 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical VIL and VIH vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical pull-up resistance RPU vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical pull-up current Ipu vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typ. VOL @ VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typ. VOL @ VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typ. VDD - VOH @ VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typ. VDD - VOH @ VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 106 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 106 UFQFPN28 – 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) 111 Recommended footprint (dimensions in mm)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 WLCSP28 – 28-pin wafer level chip scale package, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . 115 UFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 LQFP32 – 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Doc ID 15962 Rev 5 7/122 List of figures Figure 48. Figure 49. Figure 50. Figure 51. 8/8 STM8L151xx, STM8L152xx UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Recommended footprint (dimensions in mm)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 LQFP48 – 48-pin low profile quad flat package outline (7x7) . . . . . . . . . . . . . . . . . . . . . . 118 STM8L15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 1 Introduction Introduction This document describes the STM8L15xxx family features, pinout, mechanical data and ordering information. The STM8L15xxx devices are referred to as medium-density devices in the STM8L15xxx reference manual (RM0031) and in the STM8L Flash programming manual (PM0054) For more details on the whole STMicroelectronics ultralow power family please refer to Section 2.2: Ultralow power continuum on page 12. For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). The STM8L15xxx devices provide the following benefits: ● ● ● ● Integrated system – Up to 32 Kbytes of medium-density embedded Flash program memory – 1 Kbyte of data EEPROM – Internal high speed and low-power low speed RC. – Embedded reset Ultralow power consumption – 195 µA/MHZ + 440 µA (dynamic consumption) – 0.9 µA with LSI in Active-halt mode – Clock gated system and optimized power management – Capability to execute from RAM for Low power wait mode and Low power run mode Advanced features – Up to 16 MIPS at 16 MHz CPU clock frequency – Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access. Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. – Wide choice of development tools All devices offer 12-bit ADC, DAC, two comparators, Real-time clock three 16-bit timers, one 8-bit timer as well as standard communication interface such as SPI, I2C and USART. A 4x28-segment LCD is available on the STM8L152xx line. Table 2: STM8L15x low power device features and peripheral counts and Section 3 on page 13 give an overview of the complete range of peripherals proposed in this family. The STM8L15xxx microcontroller family is suitable for a wide range of applications: ● Medical and handheld equipment ● Application control and user interface ● PC peripherals, gaming, GPS and sport equipment ● Alarm systems, wired and wireless sensors Figure 1 on page 13 shows the general block diagram of the device family. Doc ID 15962 Rev 5 9/122 Description 2 STM8L151xx, STM8L152xx Description The STM8L15xxx devices are members of the STM8L Ultralow power 8-bit family. The STM8L15xxx family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85 °C and -40 to +125 °C temperature ranges. The STM8L15xxx Ultralow power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming. All STM8L15xxx microcontrollers feature embedded data EEPROM and low power lowvoltage single-supply program Flash memory. They incorporate an extensive range of enhanced I/Os and peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. Six different packages are proposed from 28 to 48 pins. Depending on the device chosen, different sets of peripherals are included. . All STM8L Ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout. 10/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Description 2.1 Device overview Table 2. STM8L15x low power device features and peripheral counts Features Flash (Kbytes) STM8L151Gx 16 32 STM8L15xKx 16 32 Data EEPROM (Kbytes) RAM-Kbytes Timers 16 32 1 2 LCD STM8L15xCx 2 No 4x17 2 (1) 4x28 (1) Basic 1 (8-bit) 1 (8-bit) 1 (8-bit) General purpose 2 (16-bit) 2 (16-bit) 2 (16-bit) Advanced control 1 (16-bit) 1 (16-bit) 1 (16-bit) 1 1 1 1 1 1 SPI Communication I2C interfaces USART 1 1 (3) 30 (2)(3) or 29 1 (1)(3) 41(3) GPIOs 26 12-bit synchronized ADC (number of channels) 1 (18) 1 (22 (2) or 21 (1)) 1 (25) 12-Bit DAC (number of channels) 1 (1) 1 (1) 1 (1) 2 2 2 Comparators COMP1/COMP2 Others RTC, window watchdog, independent watchdog, 16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator CPU frequency Operating voltage 16 MHz 1.8 V to 3.6 V (down to 1.65 V at power down) Operating temperature Packages -40 to +85 °C / -40 to +125 °C UFQFPN28 (4x4; 0.6 mm thickness) WLCSP28 UFQFPN32 (5x5; 0.6 mm thickness) LQFP32(7x7) UFQFPN48 (4x4; 0.6 mm thickness) LQFP48 1. STM8L152xx versions only 2. STM8L151xx versions only 3. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1). Doc ID 15962 Rev 5 11/122 Description 2.2 STM8L151xx, STM8L152xx Ultralow power continuum The Ultralow power STM8L151xx and STM8L152xx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers UtraLowPower strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 µm ultralow leakage process. Note: 1 The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices. 2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family. Please refer to STM32L15x documentation for more information on these devices. Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs. Shared peripherals STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another: ● Analog peripherals: ADC1, DAC, and comparators COMP1/COMP2 ● Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L151xx/152xx and STM32L15xx devices use a common architecture: ● Same power supply range from 1.8 to 3.6 V, down to 1.65 V at power down ● Architecture optimized to reach ultralow consumption both in low power modes and Run mode ● Fast startup strategy from low power modes ● Flexible system clock ● Ultrasafe reset: same reset strategy for both STM8L15xxx and STM32L15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST UtraLowPower continuum also lies in feature compatibility: 12/122 ● More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm ● Memory density ranging from 4 to 128 Kbytes Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Functional overview 3 Functional overview Figure 1. STM8L15xxx device block diagram OSC_IN, OSC_OUT 16 MHz internal RC OSC32_IN, OSC32_OUT @VDD 1-16 MHz oscillator 32 kHz oscillator Clock controller and CSS 38 kHz internal RC VDD18 Clocks to core and peripherals Interrupt controller Debug module (SWIM) BOR 16-bit Timer 2 2 channels 16-bit Timer 3 3 channels 16-bit Timer 1 8-bit Timer 4 Infrared interface DMA1 (4 channels) VREFINT out COMP1_INP COMP2_INP COMP2_INM DAC_OUT VREF+ VLCD = 2.5 V to 3.6 V 32 Kbytes Program memory 1 Kbyte Data EEPROM 2 Kbytes RAM PB[7:0] Port C PC[7:0] Port D PD[7:0] Port E PE[7:0] 12-bit ADC1 Port F PF0 Temp sensor Beeper BEEP RTC ALARM, CALIB SPI1 VREF+ VREF- PVD_IN Port B I²C1 ADC1_INx NRST PA[7:0] MOSI, MISO, SCK, NSS VDDA VSSA PVD VDD1 =1.65 V to 3.6 V VSS1 Port A SCL, SDA, SMB RX, TX, CK RESET POR/PDR 2 channels IR_TIM VOLT. REG. STM8 Core Address, control and data buses SWIM Power USART1 @VDDA/VSSA Internal reference voltage IWDG (38 kHz clock) COMP 1 WWDG COMP 2 12-bitDAC DAC 12-bit LCD driver 4x28 SEGx, COMx LCD booster 1. Legend: ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access DAC: Digital-to-analog converter I²C: Inter-integrated circuit multimaster interface IWDG: Independent watchdog LCD: Liquid crystal display POR/PDR: Power on reset / power down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog Doc ID 15962 Rev 5 13/122 Functional overview 3.1 STM8L151xx, STM8L152xx Low power modes The STM8L15xxx supports five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 20. ● Low power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM are stopped and the voltage regulator is configured in Ultralow power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power run mode consumption: refer to Table 21. ● Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode consumption: refer to Table 22. ● Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Active-halt consumption: refer to Table 23 and Table 24. ● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs. Halt consumption: refer to Table 25. 3.2 Central processing unit STM8 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. Architecture and registers 14/122 ● Harvard architecture ● 3-stage pipeline ● 32-bit wide program memory bus - single cycle fetching most instructions ● X and Y 16-bit index registers - enabling indexed addressing modes with or without Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Functional overview offset and read-modify-write type data manipulations ● 8-bit accumulator ● 24-bit program counter - 16 Mbyte linear memory space ● 16-bit stack pointer - access to a 64 Kbyte level stack ● 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing ● 20 addressing modes ● Indexed indirect addressing mode for lookup tables located anywhere in the address space ● Stack pointer relative addressing mode for local variables and parameter passing Instruction set 3.2.2 ● 80 instructions with 2-byte average instruction size ● Standard data movement and logic/arithmetic functions ● 8-bit by 8-bit multiplication ● 16-bit by 8-bit and 16-bit by 16-bit division ● Bit manipulation ● Data transfer between stack and accumulator (push/pop) with direct stack access ● Data transfer using the X and Y registers or direct memory-to-memory transfers Interrupt controller The STM8L15xxx features a nested vectored interrupt controller: ● Nested interrupts with 3 software priority levels ● 32 interrupt vectors with hardware priority ● Up to 40 external interrupt sources on 11 vectors ● Trap and reset interrupts Doc ID 15962 Rev 5 15/122 Functional overview STM8L151xx, STM8L152xx 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: 3.3.2 ● VSS1 ; VDD1 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1. ● VSSA ; VDDA = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for analog peripherals (minimum voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must be connected to VDD1 and VSS1, respectively. ● VSS2 ; VDD2 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supplies for I/Os. VDD2 and VSS2 must be connected to VDD1 and VSS1, respectively. ● VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided externally through VREF+ and VREF- pin. ● VREF+ (for DAC): external voltage reference for DAC must be provided externally through VREF+. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD min value at power down is 1.65 V). Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The STM8L15xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: 16/122 ● Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes. ● Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes. Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Functional overview When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.4 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features ● Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler ● Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. ● Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ● System clock sources: 4 different clock sources can be used to drive the system clock: – 1-16 MHz High speed external crystal (HSE) – 16 MHz High speed internal RC oscillator (HSI) – 32.768 Low speed external crystal (LSE) – 38 kHz Low speed internal RC (LSI) ● RTC and LCD clock sources: the above four sources can be chosen to clock the RTC and the LCD, whatever the system clock. ● Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ● Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI. ● Configurable main clock output (CCO): This outputs an external clock for use by the application. Doc ID 15962 Rev 5 17/122 Functional overview Figure 2. STM8L151xx, STM8L152xx STM8L15x clock tree diagram #33 /3#?). /3#?/54 (3% (3%/3# -(Z 393#,+ TOCOREAND (3) (3)2# -(Z 393#,+ 0RESCALER ,3) ,3% ,3% #,+"%%03%,;= ,3) ,3)2# K (Z 24#3%,;= /3#?). /3#?/54 24# PRESCALER ,3%/3# K(Z 24##,+ MEMORY 0#,+ TOPERIPHERALS 0ERIPHERAL #LOCKENABLEBITS "%%0#,+ TO"%%0 )7$'#,+ TO)7$' 24##,+ TO24# ,#$PERIPHERAL CLOCKENABLEBIT 24##,+ TO,#$ (ALT ##/ CONFIGURABLE CLOCKOUTPUT ##/ PRESCALER (3) ,3) (3% ,3% 393#,+ ,#$#,+ TO,#$ ,#$PERIPHERAL CLOCKENABLEBIT AIG 1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L15x reference manual (RM0031). 2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L15x reference manual (RM0031). 3.5 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. 18/122 ● Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours ● Periodic alarms based on the calendar can also be generated from every second to every year Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 3.6 Functional overview LCD (Liquid crystal display) The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels. ● Internal step-up converter to guarantee contrast control whatever VDD. ● Static 1/2, 1/3, 1/4 duty supported. ● Static 1/2, 1/3 bias supported. ● Phase inversion to reduce power consumption and EMI. ● Up to 4 pixels which can programmed to blink. ● The LCD controller can operate in Halt mode. Note: Unnecessary segments and common pins can be used as general I/O pins. 3.7 Memories The STM8L15xxx devices have the following main features: ● Up to 2 Kbytes of RAM ● The non-volatile memory is divided into three arrays: – Up to 32 Kbytes of medium-density embedded Flash program memory – 1 Kbyte of Data EEPROM – Option bytes. The EEPROM embeds the error correction code (ECC) feature. It supports the read-whilewrite (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix. The option byte protects part of the Flash program memory from write and readout piracy. 3.8 DMA A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, DAC, I2C1, SPI1, USART1, the 4 Timers. 3.9 Note: Analog-to-digital converter ● 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel), temperature sensor and internal reference voltage ● Conversion time down to 1 µs with fSYSCLK= 16 MHz ● Programmable resolution ● Programmable sampling time ● Single and continuous mode of conversion ● Scan capability: automatic conversion performed on a selected group of analog inputs ● Analog watchdog ● Triggered by timer ADC1 can be served by DMA1. Doc ID 15962 Rev 5 19/122 Functional overview 3.10 STM8L151xx, STM8L152xx Digital-to-analog converter (DAC) ● 12-bit DAC with output buffer ● Synchronized update capability using TIM4 ● DMA capability ● External triggers for conversion ● Input reference voltage VREF+ for better resolution Note: DAC can be served by DMA1. 3.11 Ultralow power comparators The STM8L15x embeds two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal or external (coming from an I/O). ● One comparator with fixed threshold (COMP1). ● One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one of the following: – DAC output – External I/O – Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4) The two comparators can be used together to offer a window function. They can wake up from Halt mode. 3.12 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1, COMP2, DAC and the internal reference voltage VREFINT. Finally, it provides a set of registers for efficiently managing a set of dedicated I/Os supporting up to 16 capacitive sensing channels using the ProxSenseTM technology. 3.13 Timers STM8L15xxx devices contain one advanced control timer (TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 3 compares the features of the advanced control, general-purpose and basic timers. 20/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 3. Timer Timer feature comparison Counter Counter resolution type Prescaler factor 16-bit 3.13.1 Capture/compare channels Complementary outputs 3+1 3 up/down Any power of 2 from 1 to 128 TIM3 TIM4 DMA1 request generation Any integer from 1 to 65536 TIM1 TIM2 Functional overview Yes 2 None 8-bit up Any power of 2 from 1 to 32768 0 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. 3.13.2 3.13.3 ● 16-bit up, down and up/down autoreload counter with 16-bit prescaler ● 3 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output ● 1 additional capture/compare channel which is not connected to an external I/O ● Synchronization module to control the timer with external signals ● Break input to force timer outputs into a defined state ● 3 complementary outputs with adjustable dead time ● Encoder mode ● Interrupt capability on various events (capture, compare, overflow, break, trigger) 16-bit general purpose timers ● 16-bit autoreload (AR) up/down-counter ● 7-bit prescaler adjustable to fixed power of 2 ratios (1…128) ● 2 individually configurable capture/compare channels ● PWM mode ● Interrupt capability on various events (capture, compare, overflow, break, trigger) ● Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow or for DAC trigger generation. Doc ID 15962 Rev 5 21/122 Functional overview 3.14 STM8L151xx, STM8L152xx Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 3.14.1 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.14.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 3.15 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 3.16 Communication interfaces 3.16.1 SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices. ● Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave ● Full duplex synchronous transfers ● Simplex synchronous transfers on 2 lines with a possible bidirectional data line ● Master or slave operation - selectable by hardware or software ● Hardware CRC calculation ● Slave/master selection input pin Note: SPI1 can be served by the DMA1 Controller. 3.16.2 I²C The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing. 22/122 ● Master, slave and multi-master capability ● Standard mode up to 100 kHz and fast speed modes up to 400 kHz. ● 7-bit and 10-bit addressing modes. ● SMBus 2.0 and PMBus support ● Hardware CRC calculation Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Functional overview Note: I2C1 can be served by the DMA1 Controller. 3.16.3 USART The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. ● 1 Mbit/s full duplex SCI ● SPI1 emulation ● High precision baud rate generator ● Smartcard emulation ● IrDA SIR encoder decoder ● Single wire half duplex mode Note: USART1 can be served by the DMA1 Controller. 3.17 Infrared (IR) interface The STM8L15x devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.18 Development support Development tools Development tools for the STM8 microcontrollers include: ● The STice emulation system offering tracing and code profiling ● The STVD high-level language debugger including C compiler, assembler and integrated development environment ● The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers. Bootloader A bootloader is available to reprogram the Flash memory using the USART1 interface. Doc ID 15962 Rev 5 23/122 Pin description Pin description PC3 PC2 PC1 27 PC5 PC6 28 PC4 PA0 STM8L151Gx UFQFPN 28 package pinout 26 25 24 23 22 NRST/PA1 1 21 PC0 PA2 2 20 PD4 PA3 3 19 PB7 PA4 4 18 PB6 PA5 5 17 PB5 6 16 PB4 15 PB3 8 9 10 11 12 13 14 PD3 PB0 PB1 PB2 7 PD2 VSS1/VSSA/VREFVDD1/VDDA/VREF+ PD1 Figure 3. PD0 4 STM8L151xx, STM8L152xx AI Figure 4. STM8L151Gx WLCSP28 package pinout ! 0! 0# 0# 0# " 0! 0# 0# 0# # 0! 0! 0# 0$ $ 0! 0! 0" 0" % 0$ 0" 0" 0" & 62%& 0$ 0" 0" ' 62%& 0$ 0$ 0" AI 24/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx STM8L151Kx 32-pin package pinout (without LCD) 0! 0# 0# 0# 0# 0# 0# 0# Figure 5. Pin description .2340! 0! 0! 0! 0! 0! 633 6$$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0" 0" 0" 0" AI 1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package. STM8L152Kx 32-pin package pinout (with LCD) 0! 0# 0# 0# 0# 0# 0# 0# Figure 6. .2340! 0! 0! 0! 0! 0! 633 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6,#$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$ AI 1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package. STM8L151Cx 48-pin pinout (without LCD) PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSS2 VDD2 PC1 PC0 Figure 7. 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Res. (1) PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS1/VSSA/VREFVDD1 VDDA VREF+ 1. Reserved. Must be tied to VDD. Doc ID 15962 Rev 5 25/122 Pin description STM8L152Cx 48-pin pinout (with LCD) PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSS2 VDD2 PC1 PC0 Figure 8. STM8L151xx, STM8L152xx 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VLCD PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS1/VSSA/VREFVDD1 VDDA VREF+ 26/122 Doc ID 15962 Rev 5 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 STM8L151xx, STM8L152xx Table 4. Pin description Legend/abbreviation for table 5 Type I= input, O = output, S = power supply Input CM = CMOS Output HS = high sink/source (20 mA) Level Port and control Input configuration Output Reset state T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). STM8L15x pin description 3 C4 5 - 6 X Reset PA1 I/O X X X HS X PA3/OSC_OUT/[USART1 I/O _RX](3)/[SPI1_MOSI](3) X X X HS X HSE oscillator output / X Port A3 [USART1 receive]/ [SPI1 master out/slave in]/ HS X Timer 2 - break input / LCD COM 0 / ADC1 X Port A4 input 2 / Comparator 1 positive input HS X Timer 2 - break input / [Timer 2 - trigger] / LCD_COM 0 / ADC1 X Port A4 input 2 / Comparator 1 positive input HS X Timer 3 - break input / LCD_COM 1 / ADC1 X Port A5 input 1/ Comparator 1 positive input PA4/TIM2_BKIN/ - LCD_COM0(2)/ADC1_IN2/ I/O COMP1_INP - 4 PA4/TIM2_BKIN/ [TIM2_TRIG](3)/ 4 D3 LCD_COM0(2)/ ADC1_IN2/COMP1_INP - HS X Default alternate function HSE oscillator input / [USART1 transmit] / X Port A2 [SPI1 master in- slave out] / - - Main function (after reset) 3 PP 4 X OD 2 I/O Output Ext. interrupt 3 PA2/OSC_IN/ 2 B4 [USART1_TX](3)/ [SPI1_MISO] (3) floating 1 C3 NRST/PA1(1) I/O level UFQFPN28 1 Pin name Type UFQFPN32 2 WLCSP28 UFQFPN48 and LQFP48 Input High sink/source Pin number wpu Table 5. float = floating, wpu = weak pull-up I/O PA5/TIM3_BKIN/ - LCD_COM1(2)/ADC1_IN1/ I/O COMP1_INP X X X X X X X X X Doc ID 15962 Rev 5 27/122 Pin description STM8L15x pin description (continued) 8 - - - PA7/LCD_SEG0(2)(4) X X I/O FT PB0(5)/TIM2_CH1/ 24 13 12 E3 LCD_SEG10(2)/ I/O ADC1_IN18/COMP1_INP PB1/TIM3_CH1/ 25 14 13 G1 LCD_SEG11(2)/ I/O ADC1_IN17/COMP1_INP PB2/ TIM2_CH2/ 26 15 14 F2 LCD_SEG12(2)/ I/O ADC1_IN16/COMP1_INP 27 - - 16 28/122 - PB3/TIM2_TRIG/ I/O - LCD_SEG13(2)/ ADC1_IN15/COMP1_INP - PB3/[TIM2_TRIG](3)/ TIM1_CH2N/LCD_SEG13 I/O - (2) /ADC1_IN15/ COMP1_INP X X X X X X X Default alternate function HS X Timer 3 - break input / [Timer 3 - trigger] / LCD_COM 1 / X Port A5 ADC1 input 1 / Comparator 1 positive input X HS X [ADC1 - trigger] / LCD_COM2 / X Port A6 ADC1 input 0 / Comparator 1 positive input X HS X X Port A7 LCD segment 0 HS X Timer 2 - channel 1 / LCD segment 10 / X Port B0 ADC1_IN18 / Comparator 1 positive input HS X Timer 3 - channel 1 / LCD segment 11 / X Port B1 ADC1_IN17 / Comparator 1 positive input HS X Timer 2 - channel 2 / LCD segment 12 / X Port B2 ADC1_IN16/ Comparator 1 positive input HS X Timer 2 - trigger / LCD segment 13 /ADC1_IN15 X Port B3 / Comparator 1 positive input HS X [Timer 2 - trigger] / Timer 1 inverted channel 2 / LCD segment 13 / X Port B3 ADC1_IN15 / Comparator 1 positive input X X(5) X(5) X X Main function (after reset) X PP X X OD - X wpu 6 floating 7 PA6/[ADC1_TRIG](3)/ - LCD_COM2(2)/ADC1_IN0/ I/O COMP1_INP - Pin name Output High sink/source I/O level 5 PA5/TIM3_BKIN/ [TIM3_TRIG](3)/ 5 D4 I/O LCD_COM1(2)/ADC1_IN1/ COMP1_INP WLCSP28 UFQFPN28 Type Input UFQFPN32 UFQFPN48 and LQFP48 Pin number Ext. interrupt Table 5. STM8L151xx, STM8L152xx X X X X Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx STM8L15x pin description (continued) - 28 - 29 - - PB3/[TIM2_TRIG](3)/ TIM1_CH1N/ 15 E2 LCD_SEG13(2)/ I/O ADC1_IN15/RTC_ALARM /COMP1_INP - PB4(5)/[SPI1_NSS](3)/ I/O - LCD_SEG14(2)/ ADC1_IN14/COMP1_INP - PB4(5)/[SPI1_NSS](3)/ LCD_SEG14(2)/ 17 16 D2 ADC1_IN14/ COMP1_INP/DAC_OUT - - I/O PB5/[SPI1_SCK](3)/ I/O - LCD_SEG15(2)/ ADC1_IN13/COMP1_INP PB5/[SPI1_SCK](3)/ LCD_SEG15(2)/ 18 17 D1 ADC1_IN13/DAC_OUT/ COMP1_INP I/O X X X X(5) X(5) X X(5) X(5) X X X X X X X - - - PB6/[SPI1_MOSI] I/O - LCD_SEG16(2)/ ADC1_IN12/COMP1_INP PB6/[SPI1_MOSI](3)/ LCD_SEG16(2)/ 19 18 F1 I/O ADC1_IN12/COMP1_INP/ DAC_OUT X X X X X X Doc ID 15962 Rev 5 Main function (after reset) Default alternate function HS X [Timer 2 - trigger] / Timer 1 inverted channel 1/ LCD segment 13 / X Port B3 ADC1_IN15 / RTC alarm/ Comparator 1 positive input HS X [SPI1 master/slave select] / LCD segment X Port B4 14 / ADC1_IN14 / Comparator 1 positive input HS X [SPI1 master/slave select] / LCD segment 14 / ADC1_IN14 / X Port B4 DAC output / Comparator 1 positive input HS X [SPI1 clock] / LCD segment 15 / X Port B5 ADC1_IN13 / Comparator 1 positive input HS X [SPI1 clock] / LCD segment 15 / ADC1_IN13 / DAC X Port B5 output/ Comparator 1 positive input HS X [SPI1 master out/slave in]/ LCD segment 16 / X Port B6 ADC1_IN12 / Comparator 1 positive input HS X [SPI1 master out]/ slave in / LCD segment X Port B6 16 / ADC1_IN12 / DAC output / Comparator 1 positive input (3)/ 30 PP OD High sink/source Output Ext. interrupt floating I/O level Pin name Type Input WLCSP28 UFQFPN28 UFQFPN32 UFQFPN48 and LQFP48 Pin number wpu Table 5. Pin description 29/122 Pin description STM8L15x pin description (continued) Main function (after reset) PP OD High sink/source Output Ext. interrupt floating Pin name I/O level Type Input WLCSP28 UFQFPN28 UFQFPN32 UFQFPN48 and LQFP48 Pin number wpu Table 5. STM8L151xx, STM8L152xx Default alternate function [SPI1 master in- slave out] / LCD segment 17 / X Port B7 ADC1_IN11 / Comparator 1 positive input PB7/[SPI1_MISO](3)/ 31 20 19 E1 LCD_SEG17(2)/ I/O ADC1_IN11/COMP1_INP X 37 25 21 B1 PC0(4)/I2C1_SDA I/O FT X X T(6) Port C0 I2C1 data 38 26 22 A1 PC1(4)/I2C1_SCL I/O FT X X T(6) Port C1 I2C1 clock PC2/[USART1_RX](3)/ 41 27 23 B2 LCD_SEG22/ADC1_IN6/ I/O COMP1_INP/VREF_OUT PC3/[USART1_TX](3)/ LCD_SEG23(2)/ 42 28 24 A2 ADC1_IN5/COMP1_INP/ COMP2_INM I/O X X X X X X X X HS X HS X [USART1 receive] / LCD segment 22 / X Port C2 ADC1_IN6 / Comparator 1 positive input / Voltage reference output HS X [USART1 transmit] / LCD segment 23 / ADC1_IN5 / Comparator X Port C3 1 positive input / Comparator 2 negative input HS X [USART1 synchronous clock] / I2C1_SMB / Configurable clock output / LCD segment 24 X Port C4 / ADC1_IN4 / Comparator 2 negative input / Comparator 1 positive input (3)/ PC4/[USART1_CK] I2C1_SMB/CCO/ I/O 43 29 25 C2 LCD_SEG24(2)/ ADC1_IN4/COMP2_INM/ COMP1_INP X X X PC5/OSC32_IN 44 30 26 A3 /[SPI1_NSS](3)/ [USART1_TX](3) I/O X X X HS X LSE oscillator input / [SPI1 master/slave X Port C5 select] / [USART1 transmit] PC6/OSC32_OUT/ 45 31 27 B3 [SPI1_SCK](3)/ [USART1_RX](3) I/O X X X HS X LSE oscillator output / X Port C6 [SPI1 clock] / [USART1 receive] 30/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx STM8L15x pin description (continued) - 21 - - 9 - 10 - I/O - PD0/TIM3_CH2/ [ADC1_TRIG](3)/ I/O ADC1_IN22/COMP2_INP/ COMP1_INP - PD1/TIM3_TRIG/ LCD_COM3(2)/ I/O ADC1_IN21/COMP2_INP/ COMP1_INP - PD1/TIM1_CH3N/[TIM3_T RIG](3)/ LCD_COM3(2)/ I/O ADC1_IN21/COMP2_INP/ COMP1_INP PD1/TIM1_CH3/[TIM3_TR IG](3)/LCD_COM3(2)/ 9 G2 I/O ADC1_IN21/COMP2_INP/ COMP1_INP X X X X X X X X X X X X X X X X X Doc ID 15962 Rev 5 Main function (after reset) PP OD High sink/source - PD0/TIM3_CH2/ [ADC1_TRIG](3)/ 8 G3 LCD_SEG7(2)/ADC1_IN2 2/COMP2_INP/ COMP1_INP X Output Ext. interrupt - floating - PC7/LCD_SEG25(2)/ - ADC1_IN3/COMP2_INM/ I/O COMP1_INP Pin name I/O level Type WLCSP28 20 Input UFQFPN28 46 UFQFPN32 UFQFPN48 and LQFP48 Pin number wpu Table 5. Pin description Default alternate function HS X LCD segment 25 /ADC1_IN3/ Comparator X Port C7 negative input / Comparator 1 positive input HS X Timer 3 - channel 2 / [ADC1_Trigger] / LCD segment 7 / ADC1_IN22 X Port D0 / Comparator 2 positive input / Comparator 1 positive input Port D0(7) Timer 3 - channel 2 / [ADC1_Trigger] / ADC1_IN22 / Comparator 2 positive input / Comparator 1 positive input HS X X HS X Timer 3 - trigger / LCD_COM3 / ADC1_IN21 / X Port D1 comparator 2 positive input / Comparator 1 positive input HS X [Timer 3 - trigger]/ TIM1 inverted channel 3 / LCD_COM3/ X Port D1 ADC1_IN21 / Comparator 2 positive input / Comparator 1 positive input HS X Timer 1 channel 3 / [Timer 3 - trigger] / LCD_COM3/ X Port D1 ADC1_IN21 / Comparator 2 positive input / Comparator 1 positive input 31/122 Pin description STM8L15x pin description (continued) PD2/TIM1_CH1 22 11 10 E4 /LCD_SEG8(2)/ I/O ADC1_IN20/COMP1_INP 23 12 - - - PD3/ TIM1_TRIG/ - LCD_SEG9(2)/ADC1_IN1 9/COMP1_INP PD3/ TIM1_TRIG/ LCD_SEG9(2)/ 11 F3 ADC1_IN19/TIM1_BKIN/ COMP1_INP/ RTC_CALIB X I/O X I/O X PD4/TIM1_CH2 I/O 33 21 20 C1 /LCD_SEG18(2)/ ADC1_IN10/COMP1_INP X X X X X X X X X Main function (after reset) PP OD High sink/source Output Ext. interrupt floating I/O level Pin name Type Input WLCSP28 UFQFPN28 UFQFPN32 UFQFPN48 and LQFP48 Pin number wpu Table 5. STM8L151xx, STM8L152xx Default alternate function HS X Timer 1 - channel 1 / LCD segment 8 / X Port D2 ADC1_IN20 / Comparator 1 positive input HS X Timer 1 - trigger / LCD segment 9 / ADC1_IN19 X Port D3 / Comparator 1 positive input HS X Timer 1 - trigger / LCD segment 9 / ADC1_IN19 / Timer 1 break input / X Port D3 RTC calibration / Comparator 1 positive input HS X Timer 1 - channel 2 / LCD segment 18 / X Port D4 ADC1_IN10/ Comparator 1 positive input HS X Timer 1 - channel 3 / LCD segment 19 / X Port D5 ADC1_IN9/ Comparator 1 positive input HS X Timer 1 - break input / LCD segment 20 / ADC1_IN8 / RTC X Port D6 calibration / Voltage reference output / Comparator 1 positive input - PD5/TIM1_CH3 - /LCD_SEG19(2)/ ADC1_IN9/COMP1_INP - PD6/TIM1_BKIN /LCD_SEG20(2)/ - ADC1_IN8/RTC_CALIB/ VREF_OUT/ COMP1_INP 36 24 - PD7/TIM1_CH1N /LCD_SEG21(2)/ - ADC1_IN7/RTC_ALARM/ I/O VREF_OUT/ COMP1_INP X X X HS X Timer 1 - inverted channel 1/ LCD segment 21 / ADC1_IN7 / RTC X Port D7 alarm / Voltage reference output /Comparator 1 positive input 14 - - PE0(4)/LCD_SEG1(2) X X X HS X X Port E0 34 22 35 23 - 32/122 I/O X I/O X I/O FT X X X X Doc ID 15962 Rev 5 LCD segment 1 STM8L151xx, STM8L152xx STM8L15x pin description (continued) Ext. interrupt - - PE1/TIM1_CH2N /LCD_SEG2(2) I/O X X X HS X X Port E1 Timer 1 - inverted channel 2 / LCD segment 2 16 - - - PE2/TIM1_CH3N /LCD_SEG3(2) I/O X X X HS X X Port E2 Timer 1 - inverted channel 3 / LCD segment 3 17 - - - PE3/LCD_SEG4(2) I/O X X X HS X X Port E3 LCD segment 4 - - PE4/LCD_SEG5 (2) I/O X X X HS X X Port E4 LCD segment 5 18 - PP wpu - OD floating 15 Pin name Type WLCSP28 Main function (after reset) Output UFQFPN28 I/O level Input UFQFPN32 UFQFPN48 and LQFP48 Pin number High sink/source Table 5. Pin description Default alternate function X X X HS X X Port E5 LCD segment 6 / ADC1_IN23 / Comparator 2 positive input / Comparator 1 positive input I/O X X X HS X X Port E6 LCD segment 26/PVD_IN - PE7/LCD_SEG27(2) I/O X X X HS X X Port E7 LCD segment 27 PF0/ADC1_IN24/ DAC_OUT I/O X X X HS X X Port F0 ADC1_IN24 / DAC_OUT 19 - - PE5/LCD_SEG6(2)/ - ADC1_IN23/COMP2_INP/ I/O COMP1_INP 47 - - - PE6/LCD_SEG26(2)/ PVD_IN 48 - - 32 - - - 13 9 - - VLCD(2) S LCD booster external capacitor (7) Reserved. Must be tied to VDD 13 - - - Reserved 10 - - - VDD S Digital power supply 11 - - - VDDA S Analog supply voltage 12 - - - VREF+ S ADC1 and DAC positive voltage reference - 8 7 G4 VDD1/VDDA/VREF+ S Digital power supply / Analog supply voltage / ADC1 positive voltage reference 9 7 6 F4 VSS1/VSSA/VREF- S I/O ground / Analog ground voltage / ADC1 negative voltage reference 39 - - S IOs supply voltage - VDD2 Doc ID 15962 Rev 5 33/122 Pin description STM8L15x pin description (continued) 1 PA0(8)/[USART1_CK](3)/ 32 28 A4 SWIM/BEEP/IR_TIM (9) S I/O Main function (after reset) PP OD High sink/source Output Ext. interrupt - VSS2 floating - I/O level WLCSP28 - Pin name Type UFQFPN28 40 Input UFQFPN32 UFQFPN48 and LQFP48 Pin number wpu Table 5. STM8L151xx, STM8L152xx Default alternate function IOs ground voltage X X(8) X HS (9) X X Port A0 [USART1 synchronous clock](3) / SWIM input and output / Beep output / Infrared Timer output 1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x reference manual (RM0031). 2. Available on STM8L152xx devices only. 3. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 4. In the 5 V tolerant I/Os, protection diode to VDD is not implemented. 5. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release. 6. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 7. Available on STM8L151xx devices only. 8. The PA0 pin is in input pull-up during the reset phase and after reset release. 9. High Sink LED driver capability available on PA0. 4.1 System configuration options As shown in Table 5: STM8L15x pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “ Routing interface (RI) and system configuration controller” section in the STM8L15xxx reference manual (RM0031). 34/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Memory and register map 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map 0x00 0000 0x00 07FF 0x00 0800 RAM (2 Kbytes) (1) including Stack (513 bytes) (1) Reserved 0x00 0FFF 0x00 1000 0x00 13FF 0x00 1400 Data EEPROM (1 Kbyte) 0x00 5000 0x00 5050 Reserved 0x00 47FF 0x00 4800 0x00 48FF 0x00 4900 0x00 4909 0x00 4910 0x00 4911 0x00 4912 0x00 4925 0x00 4926 0x00 4931 0x00 4932 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 0x00 5FFF 0x00 6000 0x00 67FF 0x00 6800 0x00 5070 0x00 509E Option bytes 0x00 50A0 0x00 50A6 Reserved 0x00 50B0 VREFINT_Factory_CONV(2) TS_Factory_CONV_V90(3) Reserved 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 FFFF 0x00 50C0 0x00 50D3 0x00 50E0 0x00 50F3 Unique ID 0x00 5140 Reserved 0x00 5200 0x00 5210 GPIO and peripheral registers 0x00 5230 0x00 5250 0x00 5280 Reserved 0x00 52B0 0x00 52E0 Boot ROM (2 Kbytes) 0x00 52FF 0x00 5340 0x00 5380 Reserved 0x00 7EFF 0x00 7F00 0x00 50B2 0x00 5400 0x00 5430 CPU/SWIM/Debug/ITC Registers 0x00 5440 GPIO Ports Flash DMA1 SYSCFG ITC-EXTI WFE RST PWR CLK WWDG IWDG BEEP RTC SPI1 I2C1 USART1 TIM2 TIM3 TIM1 TIM4 IRTIM ADC1 DAC LCD RI COMP Reset and interrupt vectors Medium-density Flash program memory (up to 32 Kbytes) 1. Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. The VREFINT_Factory_CONV byte represents the LSB of the VREFINT 12-bit ADC conversion result. The MSB have a fixed value: 0x6. 3. The TS_Factory_CONV_V90 byte represents the LSB of the V90 12-bit ADC conversion result. The MSB have a fixed value: 0x3. 4. Refer to Table 8 for an overview of hardware register mapping, to Table 7 for details on I/O port hardware registers, and to Table 9 for information on CPU/SWIM/debug module controller registers. Doc ID 15962 Rev 5 35/122 Memory and register map Table 6. STM8L151xx, STM8L152xx Flash and RAM boundary addresses Memory area Size Start address End address RAM 2 Kbytes 0x00 0000 0x00 07FF 16 Kbytes 0x00 8000 0x00 BFFF 32 Kbytes 0x00 8000 0x00 FFFF Flash program memory 5.2 Register map Table 7. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xxx PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x01 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xxx PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xxx PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xxx PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xxx PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 0x00 5016 36/122 Block Port A Port B Port C Port D Port E Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 7. Memory and register map I/O port hardware register map (continued) Register label Register name Reset status 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xxx PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 Address 0x00 501B Table 8. Block Port F General hardware register map Address Block Register label 0x00 501E to 0x00 5049 Register name Reset status Reserved area (44 bytes) 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash program memory unprotection key register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0x00 0x00 5052 0x00 5055 to 0x00 506F Flash Reserved area (27 bytes) Doc ID 15962 Rev 5 37/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 5070 DMA1_GCSR DMA1 global configuration & status register 0xFC 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 Address Block 0x00 5072 to 0x00 5074 Reserved area (3 bytes) 0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00 0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register (channel 0) 0x00 0x00 5078 DMA1_C0PARH DMA1 peripheral address high register (channel 0) 0x52 0x00 5079 DMA1_C0PARL DMA1 peripheral address low register (channel 0) 0x00 0x00 507A Reserved area (1 byte) DMA1 0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register (channel 0) 0x00 0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register (channel 0) 0x00 0x00 507D to 0x00 507E Reserved area (2 bytes) 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00 0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register (channel 1) 0x00 0x00 5082 DMA1_C1PARH DMA1 peripheral address high register (channel 1) 0x52 0x00 5083 DMA1_C1PARL DMA1 peripheral address low register (channel 1) 0x00 38/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Address Block Register label 0x00 5084 Register name Reset status Reserved area (1 byte) 0x00 5085 DMA1_C1M0ARH DMA1 memory 0 address high register (channel 1) 0x00 0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 Reserved area (2 bytes) 0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00 0x00 508B DMA1_C2NDTR DMA1 number of data to transfer register (channel 2) 0x00 0x00 508C DMA1_C2PARH DMA1 peripheral address high register (channel 2) 0x52 0x00 508D DMA1_C2PARL DMA1 peripheral address low register (channel 2) 0x00 0x00 508E Reserved area (1 byte) 0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register (channel 2) 0x00 DMA1_C2M0ARL DMA1 memory 0 address low register (channel 2) 0x00 DMA1 0x00 5090 0x00 5091 0x00 5092 Reserved area (2 bytes) 0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00 0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register (channel 3) 0x00 0x00 5096 DMA1_C3PARH_ C3M1ARH DMA1 peripheral address high register (channel 3) 0x40 0x00 5097 DMA1_C3PARL_ C3M1ARL DMA1 peripheral address low register (channel 3) 0x00 0x00 5098 Reserved area (1 byte) 0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register (channel 3) 0x00 0x00 509A DMA1_C3M0ARL DMA1 memory 0 address low register (channel 3) 0x00 0x00 509B to 0x00 509D Reserved area (3 bytes) 0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00 SYSCFG_RMPCR2 Remapping register 2 0x00 SYSCFG 0x00 509F Doc ID 15962 Rev 5 39/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 WFE_CR3 WFE control register 3 0x00 Address Block 0x00 50A2 ITC - EXTI 0x00 50A7 WFE 0x00 50A8 0x00 50A9 to 0x00 50AF Reserved area (7 bytes) 0x00 50B0 RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 PWR_CSR1 Power control and status register 1 0x00 PWR_CSR2 Power control and status register 2 0x00 RST 0x00 50B1 0x00 50B2 PWR 0x00 50B3 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK_DIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 CLK_SCSR System clock status register 0x01 0x00 50C8 CLK_SWR System clock switch register 0x01 0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000 0x00 50CA CLK_CSSR Clock security system register 0x00 0x00 50CB CLK_CBEEPR Clock BEEP register 0x00 0x00 50CC CLK_HSICALR HSI calibration register 0xxx 0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x 0x00 50C7 CLK 40/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Address Block Register label 0x00 50D0 to 0x00 50D2 Register name Reset status Reserved area (3 bytes) 0x00 50D3 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F WWDG 0x00 50D4 0x00 50D5 to 00 50DF Reserved area (11 bytes) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0x IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 513F BEEP_CSR1 BEEP BEEP control/status register 1 0x00 Reserved area (2 bytes) BEEP_CSR2 BEEP control/status register 2 0x1F Reserved area (76 bytes) Doc ID 15962 Rev 5 41/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 5140 RTC_TR1 Time register 1 0x00 0x00 5141 RTC_TR2 Time register 2 0x00 0x00 5142 RTC_TR3 Time register 3 0x00 Address Block 0x00 5143 Reserved area (1 byte) 0x00 5144 RTC_DR1 Date register 1 0x00 0x00 5145 RTC_DR2 Date register 2 0x00 0x00 5146 RTC_DR3 Date register 3 0x00 0x00 5147 Reserved area (1 byte) 0x00 5148 RTC_CR1 Control register 1 0x00 0x00 5149 RTC_CR2 Control register 2 0x00 0x00 514A RTC_CR3 Control register 3 0x00 0x00 514B Reserved area (1 byte) 0x00 514C RTC_ISR1 Initialization and status register 1 0x00 0x00 514D RTC_ISR2 Initialization and Status register 2 0x00 0x00 514E 0x00 514F Reserved area (2 bytes) RTC 0x00 5150 RTC_SPRERH Synchronous prescaler register high - 0x00 5151 RTC_SPRERL Synchronous prescaler register low - 0x00 5152 RTC_APRER Asynchronous prescaler register - 0x00 5153 Reserved area (1 byte) 0x00 5154 RTC_WUTRH Wakeup timer register high - 0x00 5155 RTC_WUTRL Wakeup timer register low - 0x00 5156 to 0x00 5158 0x00 5159 Reserved area (3 bytes) RTC_WPR 0x00 515A 0x00 515B Write protection register 0x00 Reserved area (2 bytes) 0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00 0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00 0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00 0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00 0x00 5160 to 0x00 51FF 42/122 Reserved area (160 bytes) Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5200 SPI1_CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00 SPI1_SR SPI1 status register 0x02 0x00 5204 SPI1_DR SPI1 data register 0x00 0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00 Address Block 0x00 5203 SPI1 0x00 5208 to 0x00 520F Reserved area (8 bytes) 0x00 5210 I2C1_CR1 I2C1 control register 1 0x00 0x00 5211 I2C1_CR2 I2C1 control register 2 0x00 0x00 5212 I2C1_FREQR I2C1 frequency register 0x00 0x00 5213 I2C1_OARL I2C1 own address register low 0x00 0x00 5214 I2C1_OARH I2C1 own address register high 0x00 0x00 5215 Reserved (1 byte) 0x00 5216 I2C1_DR I2C1 data register 0x00 I2C1_SR1 I2C1 status register 1 0x00 0x00 5218 I2C1_SR2 I2C1 status register 2 0x00 0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x 0x00 521A I2C1_ITR I2C1 interrupt control register 0x00 0x00 521B I2C1_CCRL I2C1 clock control register low 0x00 0x00 521C I2C1_CCRH I2C1 clock control register high 0x00 0x00 521D I2C1_TRISER I2C1 TRISE register 0x02 0x00 521E I2C1_PECR I2C1 packet error checking register 0x00 0x00 5217 0x00 521F to 0x00 522F I2C1 Reserved area (17 bytes) Doc ID 15962 Rev 5 43/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 5230 USART1_SR USART1 status register 0xC0 0x00 5231 USART1_DR USART1 data register undefined 0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1_CR1 USART1 control register 1 0x00 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 Address 0x00 5235 0x00 523B to 0x00 524F 44/122 Block USART1 Reserved area (21 bytes) Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2_SR1 TIM2 status register 1 0x00 0x00 5257 TIM2_SR2 TIM2 status register 2 0x00 0x00 5258 TIM2_EGR TIM2 event generation register 0x00 0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 525C TIM2_CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5265 TIM2_BKR TIM2 break register 0x00 0x00 5266 TIM2_OISR TIM2 output idle state register 0x00 Address 0x00 525B 0x00 5267 to 0x00 527F Block TIM2 Reserved area (25 bytes) Doc ID 15962 Rev 5 45/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3_SR1 TIM3 status register 1 0x00 0x00 5287 TIM3_SR2 TIM3 status register 2 0x00 0x00 5288 TIM3_EGR TIM3 event generation register 0x00 0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00 0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00 0x00 528C TIM3_CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF 0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF 0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00 0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00 0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 Address 0x00 528B 0x00 5297 to 0x00 52AF 46/122 Block TIM3 Reserved area (25 bytes) Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00 0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00 0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00 0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00 0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00 0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00 0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00 0x00 52B8 TIM1_EGR TIM1 event generation register 0x00 0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00 0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00 0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00 0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00 0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00 0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00 0x00 52BF TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF 0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF 0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00 0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00 0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00 0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00 0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00 0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00 0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00 0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00 0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00 0x00 52CE TIM1_BKR TIM1 break register 0x00 0x00 52CF TIM1_DTR TIM1 dead-time register 0x00 0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00 0x00 52D1 TIM1_DCR1 DMA1 control register 1 Address Block 0x00 52C0 TIM1 Doc ID 15962 Rev 5 47/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 52D2 TIM1_DCR2 TIM1 DMA1 control register 2 0x00 0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00 Address Block 0x00 52D4 to 0x00 52DF Reserved area (12 bytes) 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00 TIM4_IER TIM4 Interrupt enable register 0x00 0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00 0x00 52E4 TIM4 0x00 52EA to 0x00 52FE 0x00 52FF Reserved area (21 bytes) IRTIM IR_CR 0x00 5300 to 0x00 533F Infrared control register 0x00 Reserved area (64 bytes) 0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F 0x00 5343 ADC1_SR ADC1 status register 0x00 0x00 5344 ADC1_DRH ADC1 data register high 0x00 0x00 5345 ADC1_DRL ADC1 data register low 0x00 ADC1_HTRH ADC1 high threshold register high 0x0F 0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF 0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00 0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 0x00 5346 ADC1 48/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Register label Register name Reset status ADC1_TRIGR1 ADC1 trigger disable 1 0x00 ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 Address Block 0x00 534E 0x00 534F ADC1 0x00 5352 to 0x00 537F Reserved area (46 bytes) 0x00 5380 DAC_CR1 DAC control register 1 0x00 0x00 5381 DAC_CR2 DAC control register 2 0x00 0x00 5382 to 0x00 5383 Reserved area (2 bytes) 0x00 5384 DAC_SWTRIGR DAC software trigger register 0x00 0x00 5385 DAC_SR DAC status register 0x00 0x00 5386 to 0x00 5387 Reserved area (2 bytes) 0x00 5388 0x00 5389 DAC_RDHRH DAC right aligned data holding register high 0x00 DAC_RDHRL DAC right aligned data holding register low 0x00 DAC 0x00 538A to 0x00 538B Reserved area (2 bytes) 0x00 538C DAC_LDHRH DAC left aligned data holding register high 0x00 0x00 538D DAC_LDHRL DAC left aligned data holding register low 0x00 0x00 538E to 0x00 538F 0x00 5390 Reserved area (2 bytes) DAC_DHR8 0x00 5391 to 0x00 53AB DAC 8-bit data holding register 0x00 Reserved area (27 bytes) 0x00 53AC DAC_DORH DAC data output register high 0x00 0x00 53AD DAC_DORL DAC data output register low 0x00 0x00 53AE to 0x00 53FF Reserved area (82 bytes) Doc ID 15962 Rev 5 49/122 Memory and register map Table 8. STM8L151xx, STM8L152xx General hardware register map (continued) Register label Register name Reset status 0x00 5400 LCD_CR1 LCD control register 1 0x00 0x00 5401 LCD_CR2 LCD control register 2 0x00 0x00 5402 LCD_CR3 LCD control register 3 0x00 LCD_FRQ LCD frequency selection register 0x00 0x00 5404 LCD_PM0 LCD Port mask register 0 0x00 0x00 5405 LCD_PM1 LCD Port mask register 1 0x00 0x00 5406 LCD_PM2 LCD Port mask register 2 0x00 0x00 5407 LCD_PM3 LCD Port mask register 3 0x00 Address Block 0x00 5403 LCD 0x00 5408 to 0x00 540B Reserved area (4 bytes) 0x00 540C LCD_RAM0 LCD display memory 0 0x00 0x00 540D LCD_RAM1 LCD display memory 1 0x00 0x00 540E LCD_RAM2 LCD display memory 2 0x00 0x00 540F LCD_RAM3 LCD display memory 3 0x00 0x00 5410 LCD_RAM4 LCD display memory 4 0x00 LCD_RAM5 LCD display memory 5 0x00 LCD_RAM6 LCD display memory 6 0x00 0x00 5413 LCD_RAM7 LCD display memory 7 0x00 0x00 5414 LCD_RAM8 LCD display memory 8 0x00 0x00 5415 LCD_RAM9 LCD display memory 9 0x00 0x00 5416 LCD_RAM10 LCD display memory 10 0x00 0x00 5417 LCD_RAM11 LCD display memory 11 0x00 0x00 5418 LCD_RAM12 LCD display memory 12 0x00 0x00 5419 LCD_RAM13 LCD display memory 13 0x00 0x00 5411 0x00 5412 0x00 541A to 0x00 542F 50/122 LCD Reserved area (22 bytes) Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 8. Memory and register map General hardware register map (continued) Address Block Register label 0x00 5430 Register name Reserved area (1 byte) Reset status 0x00 0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00 0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00 0x00 5433 RI_IOIR1 I/O input register 1 undefined 0x00 5434 RI_IOIR2 I/O input register 2 undefined 0x00 5435 RI_IOIR3 I/O input register 3 undefined 0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00 RI_IOCMR2 I/O control mode register 2 0x00 0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00 0x00 5439 RI_IOSR1 I/O switch register 1 0x00 0x00 543A RI_IOSR2 I/O switch register 2 0x00 0x00 543B RI_IOSR3 I/O switch register 3 0x00 0x00 543C RI_IOGCR I/O group control register 0x3F 0x00 543D RI_ASCR1 Analog switch register 1 0x00 0x00 543E RI_ASCR2 Analog switch register 2 0x00 0x00 543F RI_RCR Resistor control register 1 0x00 0x00 5440 COMP_CSR1 Comparator control and status register 1 0x00 0x00 5441 COMP_CSR2 Comparator control and status register 2 0x00 COMP_CSR3 Comparator control and status register 3 0x00 0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00 0x00 5444 COMP_CSR5 Comparator control and status register 5 0x00 0x00 5437 RI 0x00 5442 COMP Doc ID 15962 Rev 5 51/122 Memory and register map Table 9. STM8L151xx, STM8L152xx CPU/SWIM/debug module/interrupt controller registers Register Label Register Name Reset Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 0x00 7F0B to 0x00 7F5F CPU(1) Reserved area (85 bytes) CPU 0x00 7F60 CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 ITC-SPR 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 52/122 Reserved area (2 bytes) SWIM SWIM_CSR SWIM control status register Reserved area (15 bytes) Doc ID 15962 Rev 5 0x00 STM8L151xx, STM8L152xx Table 9. Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Register Label Register Name Reset Status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM Debug module control register 1 0x00 0x00 7F97 DM_CR2 DM Debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address 0x00 7F95 Block DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only Doc ID 15962 Rev 5 53/122 Interrupt vector mapping STM8L151xx, STM8L152xx 6 Interrupt vector mapping Table 10. Interrupt mapping IRQ No. Source block RESET TRAP Description Reset Software interrupt 0 1 2 Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) Yes Yes Yes Yes 0x00 8000 - - - - 0x00 8004 Reserved FLASH DMA1 0/1 EOP/WR_PG_DIS DMA1 channels 0/1 Vector address 0x00 8008 - - - - Yes Yes (2) 0x00 800C Yes Yes(2) 0x00 8010 (2) 0x00 8014 3 DMA1 2/3 DMA1 channels 2/3 - - Yes 4 RTC RTC alarm interrupt Yes Yes Yes Yes 0x00 8018 Yes Yes Yes Yes(2) 0x00 801C Yes Yes Yes Yes(2) 0x00 8020 Yes Yes (2) 0x00 8024 (2) 0x00 8028 5 6 7 EXTI PortE/F interrupt/PVD E/F/PVD(3) interrupt EXTIB EXTID External interrupt port B External interrupt port D Yes Yes Yes 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 9 EXTI1 External interrupt 1 Yes Yes Yes Yes(2) 0x00 802C Yes Yes (2) 0x00 8030 Yes Yes (2) 0x00 8034 0x00 8038 10 11 EXTI2 EXTI3 External interrupt 2 External interrupt 3 Yes Yes Yes Yes 12 EXTI4 External interrupt 4 Yes Yes Yes Yes(2) 13 EXTI5 External interrupt 5 Yes Yes Yes Yes(2) 0x00 803C Yes Yes (2) 0x00 8040 0x00 8044 14 EXTI6 External interrupt 6 Yes Yes Yes Yes Yes Yes(2) - - Yes Yes 0x00 8048 - - Yes Yes 0x00 804C Yes Yes Yes Yes(2) 0x00 8050 Update /Overflow/Trigger/Break - - Yes Yes(2) 0x00 8054 TIM2 Capture/Compare - - Yes Yes(2) 0x00 8058 21 TIM3 Update /Overflow/Trigger/Break - - Yes Yes(2) 0x00 805C 22 TIM3 Capture/Compare - - Yes Yes(2) 0x00 8060 23 TIM1 Update /Overflow/Trigger/ COM - - - Yes(2) 0x00 8064 15 EXTI7 16 LCD 17 CLK/ TIM1/ DAC System clock switch/CSS interrupt/TIM1 Break/DAC 18 COMP /ADC1 Comparator interrupt/ADC1 19 TIM2 20 54/122 External interrupt 7 LCD interrupt Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 10. Interrupt mapping (continued) IRQ No. Source block 24 TIM1 25 Interrupt vector mapping TIM4 26 SPI1 27 USART 1 28 USART 1 29 I2C1 Description Capture/Compare Update/overflow/trigger End of Transfer Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode)(1) - - - Yes(2) 0x00 8068 Yes Yes(2) 0x00 806C (2) 0x00 8070 - - Vector address Yes Yes Yes Yes Transmission complete/transmit data register empty - - Yes Yes(2) 0x00 8074 Receive Register Data full/overrun/idle line detected/parity error - - Yes Yes(2) 0x00 8078 Yes Yes Yes Yes(2) 0x00 807C I2C1 interrupt(4) 1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. 2. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. 3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031). 4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Doc ID 15962 Rev 5 55/122 Option bytes 7 STM8L151xx, STM8L152xx Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 11 for details on option byte addresses. The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for the ROP and UBC values which can only be taken into account when they are modified in ICP mode (with the SWIM). Refer to the STM8L15x Flash programming manual (PM0051) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 11. Addr. Option byte addresses Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 00 4800 Read-out protection (ROP) OPT0 ROP[7:0] 0x00 00 4802 UBC (User Boot code size) OPT1 UBC[7:0] 0x00 00 4807 Reserved 00 4808 Independent watchdog option OPT3 [3:0] Reserved 00 4809 Number of stabilization clock cycles for HSE and LSE oscillators OPT4 Reserved 00 480A Brownout reset (BOR) OPT5 [3:0] Reserved Bootloader option bytes (OPTBL) OPTBL [15:0] 00 480B 00 480C 56/122 0x00 WWDG WWDG IWDG _HALT _HW _HALT LSECNT[1:0] BOR_TH IWDG _HW HSECNT[1:0] BOR_ ON 0x00 0x00 0x01 0x00 OPTBL[15:0] 0x00 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 12. Option bytes Option byte description Option byte Option description No. OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01: the UBC contains only the interrupt vectors. 0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt vectors. 0x03 - Page 0 to 2 reserved for UBC, memory write-protected ≥ 0xFE - Page 0 to 254 reserved for UBC, memory write-protected Refer to User boot code section in the STM8L15x reference manual (RM0031). OPT2 Reserved IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode OPT3 WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles Doc ID 15962 Rev 5 57/122 Option bytes Table 12. STM8L151xx, STM8L152xx Option byte description (continued) Option byte Option description No. OPT5 BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 18 for details on the thresholds according to the value of BOR_TH bits. OPTBL 58/122 OPTBL[15:0]: This option is checked by the boot ROM code after reset. Depending on content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 bootloader user manual for more details. Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 8 Unique ID Unique ID devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: ● For use as serial numbers ● For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. ● To activate secure boot processes Table 13. Address 0x4926 0x4927 0x4928 Unique ID registers (96 bits) Content description Unique ID bits 7 6 5 4 3 1 0 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x4929 Y co-ordinate on the wafer 0x492A Wafer number U_ID[39:32] U_ID[31:24] 0x492B U_ID[47:40] 0x492C U_ID[55:48] 0x492D U_ID[63:56] 0x492E 2 Lot number U_ID[71:64] 0x492F U_ID[79:72] 0x4930 U_ID[87:80] 0x4931 U_ID[95:88] Doc ID 15962 Rev 5 59/59 Electrical parameters STM8L151xx, STM8L152xx 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 9.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions STM8L PIN 50 pF 60/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 9.1.5 Electrical parameters Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage STM8L PIN VIN 9.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 14. Voltage characteristics Symbol Ratings Min Max VDD- VSS External supply voltage (including VDDA and VDD2)(1) - 0.3 4.0 Input voltage on true open-drain pins (PC0 and PC1)(2) VSS - 0.3 VDD + 4.0 Input voltage on FT pins (PA7 and PE0)(2) VSS - 0.3 VDD + 4.0 Input voltage on any other pin (3) VSS - 0.3 4.0 VIN VESD Electrostatic discharge voltage Unit V see Absolute maximum ratings (electrical sensitivity) on page 108 1. All power (VDD1, VDD2, VDDA) and ground (VSS1, VSS2, VSSA) pins must always be connected to the external power supply. 2. Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must never be exceeded. A negative injection is induced by VIN<VSS. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Doc ID 15962 Rev 5 61/122 Electrical parameters Table 15. STM8L151xx, STM8L152xx Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 IIO IINJ(PIN) ΣIINJ(PIN) Output current sourced by any I/Os and control pin - 25 Injected current on true open-drain pins (PC0 and PC1)(1) -5 Injected current on FT pins (PA7 and PE0)(1) -5 Injected current on any other pin (2) ±5 Total injected current (sum of all I/O and control pins) (3) ± 25 Unit mA 1. Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must never be exceeded. A negative injection is induced by VIN<VSS. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. 3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 16. Symbol TSTG TJ 62/122 Thermal characteristics Ratings Storage temperature range Min Unit -65 to +150 °C Maximum junction temperature Doc ID 15962 Rev 5 150 STM8L151xx, STM8L152xx 9.3 Electrical parameters Operating conditions Subject to general operating conditions for VDD and TA. 9.3.1 General operating conditions Table 17. General operating conditions Symbol fSYSCLK(1) Parameter System clock frequency VDD Standard operating voltage VDDA Analog operating voltage Power dissipation at TA= 85 °C for suffix 6 devices PD(3) TJ Min Max Unit 1.65 V ≤VDD < 3.6 V 0 16 MHz 1.65(2) 3.6 V 1.65(2) 3.6 V 1.8 3.6 V ADC not used Must be at the same potential as VDD ADC used UFQFPN48 288 LQFP48 288 UFQFPN32 288 LQFP32 288 UFQFPN28 282 WLCSP28 286 UFQFPN48 288 LQFP48 77 UFQFPN32 227 LQFP32 85 UFQFPN28 70 WLCSP28 71 mW Power dissipation at TA= 125 °C for suffix 3 devices TA Conditions Temperature range Junction temperature range 1.65 V ≤VDD < 3.6 V (6 suffix version) -40 85 1.65 V ≤VDD < 3.6 V (3 suffix version) -40 125 -40 °C ≤TA < 85 °C (6 suffix version) -40 105 -40 °C≤ TA < 125 °C (3 suffix version) °C °C -40 130 1. fSYSCLK = fCPU 2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled 3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in “Thermal characteristics” table. Doc ID 15962 Rev 5 63/122 Electrical parameters STM8L151xx, STM8L152xx 9.3.2 Power-up / power-down operating conditions Table 18. Operating conditions at power-up / power-down Symbol(1) tVDD Parameter(1) Conditions(1) Min Typ Max VDD rise time rate 0(2) ∞ VDD fall time rate 0(2) ∞ tTEMP Reset release delay VDD rising VPDR Power-down reset threshold Falling edge 1.46 1.5 1.54 Brown-out reset threshold 0 (BOR_TH[2:0]=000) Falling edge 1.67 1.7 1.74 VBOR0 Rising edge 1.69 1.75 1.80 Brown-out reset threshold 1 (BOR_TH[2:0]=001) Falling edge 1.87 1.93 1.97 VBOR1 Rising edge 1.96 2.04 2.07 Brown-out reset threshold 2 (BOR_TH[2:0]=010) Falling edge 2.22 2.3 2.35 VBOR2 Rising edge 2.31 2.41 2.44 Brown-out reset threshold 3 (BOR_TH[2:0]=011) Falling edge 2.45 2.55 2.60 VBOR3 Rising edge 2.54 2.66 2.7 Brown-out reset threshold 4 (BOR_TH[2:0]=100) Falling edge 2.68 2.80 2.85 VBOR4 Rising edge 2.78 2.90 2.95 Falling edge 1.80 1.84 1.88 VPVD0 PVD threshold 0 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 VPVD1 PVD threshold 1 Rising edge 2.08 2.14 2.18 Falling edge 2.2 2.24 2.28 VPVD2 PVD threshold 2 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 VPVD3 PVD threshold 3 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 VPVD4 PVD threshold 4 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 VPVD5 PVD threshold 5 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 VPVD6 PVD threshold 6 Rising edge 3.08 3.15 3.20 3 1. Based on characterization results, unless otherwise specified. 2. Guaranteed by design, not tested in production. 64/122 Doc ID 15962 Rev 5 Unit µs/V ms V STM8L151xx, STM8L152xx Electrical parameters Figure 12. POR/BOR thresholds Vdd 6DD 6 Operating power supply Vdd "/2THRESHOLD "/24HRESHOLD? 6"/2 WITHOUT"/2"ATTERYLIFEEXTENSION 60$2 2ESET 3AFE2ESET 3AFE2ESETRELEASE 6 0$24HRESHOLD Internal NRST WITH WITHOUT "/2 "/2 WITH "/2 "/2ACTIVATEDBYUSERFOR POWERDOWNDETECTION "/2ALWAYSACTIVE ATPOWERUP Doc ID 15962 Rev 5 4IME 65/122 Electrical parameters 9.3.3 STM8L151xx, STM8L152xx Supply current characteristics Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Table 19. Symbol Total current consumption in Run mode Para meter Max Conditions(1)(2) Typ (1) 55°C fCPU = 125 kHz HSE external clock (fCPU=fHSE) (7) 125 °C (3) (4) (4) 0.47 0.49 0.52 0.55 0.48 0.56 0.58 0.61 0.65 0.75 0.84 0.86 0.91 0.99 1.10 1.20 1.25 1.31 1.40 fCPU = 16 MHz 1.85 1.93 2.12 2.29 2.36 fCPU = 125 kHz 0.05 0.06 0.09 0.11 0.12 fCPU = 1 MHz 0.18 0.19 0.20 0.22 0.23 fCPU = 4 MHz 0.55 0.62 0.64 0.71 0.77 fCPU = 8 MHz 0.99 1.20 1.21 1.22 1.24 2.22 2.23(8) 2.24 2.28(8) 0.040 0.045 0.046 0.048 0.050 0.050 0.062(8) fCPU = 16 MHz LSI RC osc. =f f (typ. 38 kHz) CPU LSI LSE external clock fCPU = fLSE 1.90 0.035 0.040 0.048(8) (32.768 kHz) 66/122 105 °C 0.39 fCPU = 1 MHz HSI RC osc. fCPU = 4 MHz (16 MHz)(6) fCPU = 8 MHz All peripherals Supply OFF, current code IDD(RUN) in run executed mode from RAM, (5) VDD from 1.65 V to 3.6 V 85 °C Doc ID 15962 Rev 5 Unit mA STM8L151xx, STM8L152xx Table 19. Symbol Electrical parameters Total current consumption in Run mode (continued) Para meter Max (1)(2) Conditions Typ (1) 55°C HSI RC osc.(9) All peripherals Supply OFF, code current executed IDD(RUN) in Run from Flash, VDD from mode 1.65 V to 3.6 V HSE external clock (fCPU=fHSE) (7) LSI RC osc. 85 °C 105 °C 125 °C (3) (4) (4) fCPU = 125 kHz 0.43 0.55 0.56 0.58 0.62 fCPU = 1 MHz 0.60 0.77 0.80 0.82 0.87 fCPU = 4 MHz 1.11 1.34 1.37 1.39 1.43 fCPU = 8 MHz 1.90 2.20 2.23 2.31 2.40 fCPU = 16 MHz 3.8 4.60 4.75 4.87 4.88 fCPU = 125 kHz 0.30 0.36 0.39 0.44 0.47 fCPU = 1 MHz 0.40 0.50 0.52 0.55 0.56 fCPU = 4 MHz 1.15 1.31 1.40 1.45 1.48 fCPU = 8 MHz 2.17 2.33 2.44 2.56 2.77 fCPU = 16 MHz 4.0 4.46 4.52 4.59 4.77 0.110 0.123 0.130 0.140 0.150 0.100 0.101 0.104 0.119 0.122 fCPU = fLSI LSE external clock fCPU = fLSE (32.768 (10) kHz) Unit mA 1. Based on characterization results, unless otherwise specified 2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fSYSCLK 3. For devices with suffix 6 4. For devices with suffix 3 5. CPU executing typical data processing 6. The run from RAM consumption can be approximated with the linear formula: IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA 7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 30. 8. Data guaranteed, each individual device tested in production. 9. The run from Flash consumption can be approximated with the linear formula: IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA 10. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 31 Doc ID 15962 Rev 5 67/122 Electrical parameters STM8L151xx, STM8L152xx Figure 13. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz # # # # )$$25.(3);M!= 6$$;6= BJ 1. Typical current consumption measured with code executed from RAM 68/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 20. Electrical parameters Total current consumption in Wait mode(1) Max Conditions(2) Symbol Parameter Typ 55°C HSI Supply IDD(Wait) current in Wait mode CPU not clocked, all peripherals OFF, code executed from RAM with Flash in IDDQ mode,(5) VDD from 1.65 V to 3.6 V Supply IDD(Wait) current in Wait mode (3) 105 °C 125 °C (4) (4) fCPU = 125 kHz 0.33 0.39 0.41 0.43 0.45 fCPU = 1 MHz 0.35 0.41 0.44 0.45 0.48 fCPU = 4 MHz 0.42 0.51 0.52 0.54 0.58 fCPU = 8 MHz 0.52 0.57 0.58 0.59 0.62 fCPU = 16 MHz 0.68 0.76 0.79 0.82 0.85 Unit fCPU = 125 kHz 0.032 0.056 0.068 0.072 0.093 HSE fCPU = 1 MHz external clock fCPU = 4 MHz (fCPU=fHSE) fCPU = 8 MHz (6) 0.078 0.121 0.144 0.163 0.197 0.218 0.26 0.30 0.36 0.40 0.40 0.52 0.57 0.62 0.66 fCPU = 16 MHz 0.760 1.01 1.05 1.09 1.16 LSI fCPU = fLSI 0.035 0.044 0.046 0.049 0.054 LSE(7) external clock (32.768 kHz) fCPU = fLSE 0.032 0.036 0.038 0.044 0.051 fCPU = 125 kHz 0.38 0.48 0.49 0.50 0.56 fCPU = 1 MHz 0.41 0.49 0.51 0.53 0.59 fCPU = 4 MHz 0.50 0.57 0.58 0.62 0.66 fCPU = 8 MHz 0.60 0.66 0.68 0.72 0.74 fCPU = 16 MHz 0.79 0.84 0.86 0.87 0.90 fCPU = 125 kHz 0.06 0.08 0.09 0.10 0.12 0.10 0.17 0.18 0.19 0.22 0.24 0.36 0.39 0.41 0.44 0.50 0.58 0.61 0.62 0.64 fCPU = 16 MHz 1.00 1.08 1.14 1.16 1.18 LSI fCPU = fLSI 0.055 0.058 0.065 0.073 0.080 LSE(7) external clock (32.768 kHz) fCPU = fLSE 0.051 0.056 0.060 0.065 0.073 HSI CPU not clocked, all peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V 85 °C HSE(6) fCPU = 1 MHz external clock fCPU = 4 MHz (fCPU=HSE) fCPU = 8 MHz Doc ID 15962 Rev 5 mA mA 69/122 Electrical parameters STM8L151xx, STM8L152xx 1. Based on characterization results, unless specified 2. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU = fSYSCLK 3. For temperature range 6. 4. For temperature range 3. 5. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register. 6. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 30. 7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 31 Figure 14. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1) )$$7!)4(3);!= # # # # 6$$;6= AI 1. Typical current consumption measured with code executed from Flash 70/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 21. Electrical parameters Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V Parameter(1) Symbol Conditions(2) all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(3) IDD(LPR) Supply current in Low power run mode all peripherals OFF (4) external LSE clock (32.768 kHz) with TIM2 active (3) Typ(1) Max(1) TA = -40 °C to 25 °C 5.1 5.4 TA = 55 °C 5.7 6 TA = 85 °C 6.8 7.5 TA = 105 °C 9.2 10.4 TA = 125 °C 13.4 16.6 TA = -40 °C to 25 °C 5.4 5.7 TA = 55 °C 6.0 6.3 TA = 85 °C 7.2 7.8 TA = 105 °C 9.4 10.7 TA = 125 °C 13.8 17 TA = -40 °C to 25 °C 5.25 5.6 TA = 55 °C 5.67 6.1 TA = 85 °C 5.85 6.3 TA = 105 °C 7.11 7.6 TA = 125 °C 9.84 12 TA = -40 °C to 25 °C 5.59 6 TA = 55 °C 6.10 6.4 TA = 85 °C 6.30 7 TA = 105 °C 7.55 8.4 TA = 125 °C 10.1 15 Unit μA 1. Based on characterization results, unless otherwise specified 2. No floating I/Os 3. Timer 2 clock enabled and counter running 4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 31 Doc ID 15962 Rev 5 71/122 Electrical parameters STM8L151xx, STM8L152xx Figure 15. Typ. IDD(LPR) vs. VDD (LSI clock source) 18 16 -40°C 25°C 90°C 130°C I DD(LPR)L SI [µA] 14 12 10 8 6 4 2 0 1.6 2.1 2.6 VDD [V] 72/122 Doc ID 15962 Rev 5 3.1 3.6 ai18216 STM8L151xx, STM8L152xx Table 22. Symbol Electrical parameters Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V Parameter(1)(2) Typ Max Conditions (1)(2) (1)(2) 3 3.3 TA = 55 °C 3.3 3.6 TA = 85 °C 4.4 5 TA = 105 °C 6.7 8 TA = 125 °C 11 14 TA = -40 °C to 25 °C 3.4 3.7 TA = 55 °C 3.7 4 TA = 85 °C 4.8 5.4 TA = 105 °C 7 8.3 TA = -40 °C to 25 °C all peripherals OFF LSI RC osc. (at 38 kHz) (3) with TIM2 active IDD(LPW) Supply current in Low power wait mode all peripherals OFF LSE external clock(4) (32.768 kHz) with TIM2 active (3) TA = 125 °C 11.3 14.5 TA = -40 °C to 25 °C 2.35 TA = 55 °C 2.42 2.82 TA = 85 °C 3.10 3.71 TA = 105 °C 4.36 5.7 TA = 125 °C 7.20 11 TA = -40 °C to 25 °C 2.46 2.75 TA = 55 °C 2.50 2.81 TA = 85 °C 3.16 3.82 TA = 105 °C 4.51 5.9 TA = 125 °C 7.28 11 2.7 Unit μA 1. No floating I/Os. 2. Based on characterization results, unless otherwise specified. 3. Timer 2 clock enabled and counter is running. 4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 31. Doc ID 15962 Rev 5 73/122 Electrical parameters STM8L151xx, STM8L152xx Figure 16. Typ. IDD(LPW) vs. VDD (LSI clock source) 16.00 14.00 IDD(LPW) LSI [µA] -40°C 12.00 25°C 10.00 90°C 130°C 8.00 6.00 4.00 2.00 0.00 1.6 2.1 2.6 VDD [V] 3.1 3.6 ai18217 74/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 23. Symbol Electrical parameters Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V Parameter(1)(2) Conditions TA = -40 °C to 25 °C LCD OFF(3) LCD ON (static duty/ external VLCD) (5) IDD(AH) Supply current in Active-halt mode LSI RC (at 38 kHz) LCD ON (1/4 duty/ external VLCD) (6) LCD ON (1/4 duty/ internal VLCD) (7) Doc ID 15962 Rev 5 Typ (1)(2) 0.9 Max (4) 2.1 TA = 55 °C 1.2 3 TA = 85 °C 1.5 3.4 TA = 105 °C 2.6 6.6 TA = 125 °C 5.1 12 TA = -40 °C to 25 °C 1.4 3.1 TA = 55 °C 1.5 3.3 TA = 85 °C 1.9 4.3 TA = 105 °C 2.9 6.8 TA = 125 °C 5.5 13 TA = -40 °C to 25 °C 1.9 4.3 TA = 55 °C 1.95 4.4 TA = 85 °C 2.4 5.4 TA = 105 °C 3.4 7.6 TA = 125 °C 6.0 15 TA = -40 °C to 25 °C 3.9 8.75 TA = 55 °C 4.15 9.3 TA = 85 °C 4.5 10.2 TA = 105 °C 5.6 13.5 TA = 125 °C 6.8 16.3 Unit μA 75/122 Electrical parameters Table 23. STM8L151xx, STM8L152xx Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V (continued) Symbol Parameter(1)(2) Conditions LCD OFF(9) LCD ON (static duty) (5) IDD(AH) Supply current in Active-halt mode LSE external clock (32.768 kHz) (8) Max TA = -40 °C to 25 °C 0.5 1.2 TA = 55 °C 0.62 1.4 TA = 85 °C 0.88 2.1 TA = 105 °C 2.1 4.85 TA = 125 °C 4.8 11 TA = -40 °C to 25 °C 0.85 1.9 TA = 55 °C 0.95 2.2 TA = 85 °C 1.3 3.2 TA = 105 °C 2.3 5.3 TA = 125 °C 5.0 12 TA = -40 °C to 25 °C 1.5 2.5 1.6 3.8 TA = 55 °C LCD ON T = 85 °C (1/4 duty) (6) A TA = 105 °C 1.8 4.2 2.9 7.0 TA = 125 °C 5.7 14 TA = -40 °C to 25 °C 3.4 7.6 TA = 55 °C 3.7 8.3 TA = 85 °C 3.9 9.2 TA = 105 °C 5.0 14.5 TA = 125 °C 6.3 15.2 LCD ON (1/4 duty/ internal VLCD) (7) IDD(WUFAH) Typ (1)(2) Supply current during wakeup time from Active-halt mode (using HSI) 2.4 tWU_HSI(AH)(10) Wakeup time from Active-halt mode to (11) Run mode (using HSI) 4.7 Wakeup time from Active-halt mode to Run mode (using LSI) 150 tWU_LSI(AH)(10) (11) Unit μA mA 6.2 μs μs 1. No floating I/O, unless otherwise specified. 2. Based on characterization results, unless otherwise specified. 3. RTC enabled. Clock source = LSI 4. Based on Design estimation. 5. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected. 6. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 76/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters 7. LCD enabled with internal LCD booster VLCD = 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 8. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 31 9. RTC enabled. Clock source = LSE 10. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU. 11. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register. Table 24. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal Symbol Parameter Condition Typ LSE VDD = 1.8 V IDD(AH) (1) Supply current in Active-halt mode VDD = 3 V VDD = 3.6 V Unit 1.15 (2) LSE/32 1.05 LSE 1.30 LSE/32(2) 1.20 LSE 1.45 (2) LSE/32 µA 1.35 1. Based on measurements on bench with 32.768 kHz external crystal oscillator. 2. RTC clock is LSE divided by 32. Table 25. Total current consumption and timing in Halt mode at VDD = 2 V Symbol IDD(Halt) Typ Max (1)(2) (1)(2) TA = -40 °C to 25 °C 350 1400 TA = 55 °C 580 2000 TA = 85 °C 1160 2800 TA = 105 °C 2560 6700 Parameter (1)(2) Supply current in Halt mode (Ultra low power ULP bit =1 in the PWR_CSR2 register) Condition Unit nA IDD(WUHalt) Supply current during wakeup time from Halt mode (using HSI) 2.4 tWU_HSI(Halt)(3)(4) Wakeup time from Halt to Run mode (using HSI) 4.7 tWU_LSI(Halt) (3)(4) Wakeup time from Halt mode to Run mode (using LSI) 150 mA 6.2 µs µs 1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified 2. Based on characterization results, unless otherwise specified 3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register 4. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU Doc ID 15962 Rev 5 77/122 Electrical parameters STM8L151xx, STM8L152xx Current consumption of on-chip peripherals Table 26. Peripheral current consumption Symbol Typ. Parameter VDD = 3.0 V IDD(TIM1) TIM1 supply current(1) 13 IDD(TIM2) TIM2 supply current (1) 8 IDD(TIM3) TIM3 supply current (1) 8 IDD(TIM4) TIM4 timer supply current (1) 3 USART1 supply current (2) 6 IDD(SPI1) SPI1 supply current (2) 3 IDD(I2C1) I2C1 supply current (2) 5 IDD(DMA1) DMA1 supply current 3 IDD(WWDG) WWDG supply current 2 Peripherals ON(3) 44 IDD(USART1) IDD(ALL) IDD(ADC1) ADC1 supply current(4) 1500 IDD(DAC) DAC supply current(5) 370 IDD(COMP1) Comparator 1 supply current(6) IDD(COMP2) Comparator 2 supply current(6) IDD(PVD/BOR) IDD(BOR) IDD(IDWDG) Unit µA/MHz µA/MHz 0.160 Slow mode 2 Fast mode 5 Power voltage detector and brownout Reset unit supply current µA (7) 2.6 Brownout Reset unit supply current (7) 2.4 including LSI supply current 0.45 excluding LSI supply current 0.05 Independent watchdog supply current 1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling. Not tested in production. 3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion. 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD /2. Floating DAC output. 6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs. Supply current of internal reference voltage excluded. 7. Including supply current of internal reference voltage. 78/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 27. Current consumption under external reset Symbol IDD(RST) Electrical parameters Parameter Conditions Supply current under external reset (1) Typ VDD = 1.8 V 48 VDD = 3 V 76 VDD = 3.6 V 91 All pins are externally tied to VDD Unit µA 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 9.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 28. Symbol HSE external clock characteristics Parameter Conditions fHSE_ext External clock source frequency(1) VHSEH(2) OSC_IN input pin high level voltage (2) OSC_IN input pin low level voltage Min Typ Max Unit 1 16 MHz 0.7 x VDD VDD V VHSEL Cin(HSE) ILEAK_HSE VSS 0.3 x VDD OSC_IN input capacitance(1) 2.6 OSC_IN input leakage current pF VSS < VIN < VDD ±1 µA 1. Guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production. LSE external clock (LSEBYP=1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 29. Symbol LSE external clock characteristics Parameter Min Typ Max fLSE_ext External clock source frequency(1) VLSEH(2) OSC32_IN input pin high level voltage 0.7 x VDD VDD VLSEL(2) OSC32_IN input pin low level voltage VSS 0.3 x VDD Cin(LSE) OSC32_IN input capacitance(1) ILEAK_LSE OSC32_IN input leakage current 32.768 Unit kHz V 0.6 pF ±1 µA 1. Guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production. Doc ID 15962 Rev 5 79/122 Electrical parameters STM8L151xx, STM8L152xx HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 30. HSE oscillator characteristics Symbol fHSE Parameter Conditions Min High speed external oscillator frequency Typ 1 Max Unit 16 MHz RF Feedback resistor 200 kΩ C(1) Recommended load capacitance (2) 20 pF IDD(HSE) gm HSE oscillator power consumption C = 20 pF, fOSC = 16 MHz 2.5 (startup) 0.7 (stabilized)(3) C = 10 pF, fOSC =16 MHz 2.5 (startup) 0.46 (stabilized)(3) Oscillator transconductance mA 3.5 tSU(HSE)(4) Startup time VDD is stabilized mA/V 1 ms 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Guaranteed by design. Not tested in production. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 17. HSE oscillator circuit diagram fHSE to core Rm RF CO Lm CL1 OSC_IN Cm gm Resonator Consumption control Resonator STM8 OSC_OUT CL2 HSE oscillator critical gm formula g mcrit = ( 2 × Π × f HSE ) 2 × R m ( 2Co + C ) 2 Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification), Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification), CL1=CL2=C: Grounded external capacitance gm >> gmcrit 80/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 31. LSE oscillator characteristics Symbol Parameter Conditions fLSE Low speed external oscillator frequency RF Feedback resistor C(1) Recommended load capacitance (2) Min ΔV = 200 mV Typ Max Unit 32.768 kHz 1.2 MΩ 8 pF 1.4(3) IDD(LSE) gm LSE oscillator power consumption VDD = 1.8 V 450 VDD = 3 V 600 VDD = 3.6 V 750 Oscillator transconductance nA 3 tSU(LSE)(4) Startup time VDD is stabilized µA µA/V 1 s 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value. Refer to crystal manufacturer for more details. 3. Guaranteed by design. Not tested in production. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 18. LSE oscillator circuit diagram fLSE Rm Lm RF CO CL1 OSC_IN Cm gm Resonator Consumption control Resonator STM8 OSC_OUT CL2 Doc ID 15962 Rev 5 81/122 Electrical parameters STM8L151xx, STM8L152xx Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) Table 32. Symbol fHSI HSI oscillator characteristics Parameter (1) Conditions(1) Frequency Min VDD = 3.0 V -1 VDD = 3.0 V, 0 °C ≤TA ≤ 55 °C (2) -1.5 VDD = 3.0 V, -10 °C ≤TA ≤ 85 °C VDD = 3.0 V, -10 °C ≤TA ≤ 125 °C 1.65 V ≤VDD ≤ 3.6 V, -40 °C ≤TA ≤ 125 °C (2) 1.5 (2) % % 2 (2) % -2.5 (2) 2(2) % -4.5 (2) (2) % 3 % ±0.4 (2) ±0.5(2) % 2 -4.5 1.65 V ≤VDD ≤ 3.6 V, -40 °C ≤TA ≤ 125 °C Unit MHz 1 (2) -2 (2) VDD = 3.0 V, -10 °C ≤TA ≤ 70 °C Accuracy of HSI oscillator (factory calibrated) Max 16 VDD = 3.0 V, TA = 25 °C ACCHSI Typ TRIM HSI user trim resolution tsu(HSI) HSI oscillator setup time (wakeup time) 3.7 7.4 (2) µs IDD(HSI) HSI oscillator power consumption 100 140 (2) µA 1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified. 2. Data based on characterization results, not tested in production. Figure 19. Typical HSI frequency vs VDD (3)FREQUENCY;-(Z= # # # # 6$$;6= AI 82/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Low speed internal RC oscillator (LSI) Table 33. Symbol fLSI LSI oscillator characteristics Parameter (1) Conditions(1) Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator frequency drift(3) 0 °C ≤TA ≤ 85 °C Min Typ Max Unit 26 38 56 kHz 200(2) µs 4 % -10 1. VDD = 1.8 V to 3.0 V, TA = -40 to 125 °C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. This is a deviation for an individual part, once the initial frequency has been measured. Figure 20. Typical LSI frequency vs. VDD ,3)FREQUENCY;K(Z= # # # # 6$$;6= AI Doc ID 15962 Rev 5 83/122 Electrical parameters 9.3.5 STM8L151xx, STM8L152xx Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 34. RAM and hardware registers Symbol Parameter Conditions Min VRM Data retention mode (1) Halt mode (or Reset) 1.4 Typ Max Unit V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 35. Symbol VDD tprog Iprog tRET NRW Flash program and data EEPROM memory Parameter Operating voltage (all modes, read/write/erase) Conditions Min fSYSCLK = 16 MHz 1.65 Max (1) Unit 3.6 V Programming time for 1 or 128 bytes (block) erase/write cycles (on programmed byte) 6 ms Programming time for 1 to 128 bytes (block) write cycles (on erased byte) 3 ms 0.7 mA TA=+25 °C, VDD = 3.0 V Programming/ erasing consumption TA=+25 °C, VDD = 1.8 V Data retention (program memory) after 10000 erase/write cycles at TA=+85 °C TRET=+55 °C 20(1) Data retention (data memory) after 10000 erase/write cycles at TA=+85 °C TRET=+55 °C 20(1) Data retention (data memory) after 10000 erase/write cycles at TA=+85 °C TRET=+85 °C 1(1) Erase/write cycles (program memory) See notes (1)(2) 10(1) Erase/write cycles (data memory) See notes (1)(3) 1. Data based on characterization results, not tested in production. 2. Retention guaranteed after cycling is 10 years @ 55 °C. 3. Retention guaranteed after cycling is 1 year @ 55 °C. 4. Data based on characterization performed on the whole data memory. 84/122 Typ Doc ID 15962 Rev 5 300(1) (4) years kcycles STM8L151xx, STM8L152xx 9.3.6 Electrical parameters I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 36. Symbol VIL I/O static characteristics Parameter(1) Input low level voltage(2) Conditions(1) 0.3 x VDD Input voltage on FT pins (PA7 and PE0) VSS -0.3 0.3 x VDD Input voltage on any other pin VSS -0.3 0.3 x VDD Input voltage on FT pins (PA7 and PE0) with VDD < 2 V Input voltage on FT pins (PA7 and PE0) with VDD ≥ 2 V Input voltage on any other pin Vhys Ilkg RPU CIO(7) Schmitt trigger voltage hysteresis (3) Input leakage current (4) Weak pull-up equivalent resistor(6) Max VSS -0.3 Input voltage on true open-drain pins (PC0 and PC1) with VDD ≥ 2 V Input high level voltage (2) Typ Input voltage on true open-drain pins (PC0 and PC1) Input voltage on true open-drain pins (PC0 and PC1) with VDD < 2 V VIH Min Unit V 5.2 0.70 x VDD 5.5 V 5.2 0.70 x VDD 5.5 VDD+0.3 0.70 x VDD Standard I/Os 200 True open drain I/Os 200 mV VSS≤VIN≤VDD Standard I/Os - - 50 (5) VSS≤VIN≤VDD True open drain I/Os - - 200(5) VSS≤VIN≤VDD PA0 with high sink LED driver capability - - 200(5) 30 45 60 VIN=VSS I/O pin capacitance 5 nA kΩ pF 1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified. Doc ID 15962 Rev 5 85/122 Electrical parameters STM8L151xx, STM8L152xx 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor(corresponding IPU current characteristics described in Figure 24). 7. Data guaranteed by Design, not tested in production. Figure 21. Typical VIL and VIH vs VDD (standard I/Os) # # # # 6),AND6)(;6= 6$$;6= AI Figure 22. Typical VIL and VIH vs VDD (true open drain I/Os) # # # # 6),AND6)(;6= 6$$;6= AI 86/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Figure 23. Typical pull-up resistance RPU vs VDD with VIN=VSS # # # # 0ULL5PRESISTANCE;K7= 6$$;6= AI Figure 24. Typical pull-up current Ipu vs VDD with VIN=VSS 0ULL5PCURRENT;!= # # # # 6$$;6= AI Doc ID 15962 Rev 5 87/122 Electrical parameters STM8L151xx, STM8L152xx Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 37. Output driving current (standard ports) I/O Symbol Type Output low level voltage for an I/O pin Standard VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V 0.45 V IIO = +2 mA, VDD = 1.8 V 0.45 V IIO = +10 mA, VDD = 3.0 V 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.45 V IIO = -1 mA, VDD = 1.8 V VDD-0.45 V IIO = -10 mA, VDD = 3.0 V VDD-0.7 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Table 38. Output driving current (true open drain ports) Open drain I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions Min Max IIO = +3 mA, VDD = 3.0 V 0.45 IIO = +1 mA, VDD = 1.8 V 0.45 Unit V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 39. Output driving current (PA0 with high sink LED driver capability) IR I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions IIO = +20 mA, VDD = 2.0 V Min Max Unit 0.45 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 88/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Figure 25. Typ. VOL @ VDD = 3.0 V (standard ports) Figure 26. Typ. VOL @ VDD = 1.8 V (standard ports) # # # # # # # # 6/, ;6= 6/, ;6= )/, ;M!= )/,;M!= AI Figure 27. Typ. VOL @ VDD = 3.0 V (true open drain ports) AI Figure 28. Typ. VOL @ VDD = 1.8 V (true open drain ports) # # # # 6/, ;6= 6/, ;6= # # # # )/, ;M!= )/, ;M!= BJ AI Figure 29. Typ. VDD - VOH @ VDD = 3.0 V (standard ports) Figure 30. Typ. VDD - VOH @ VDD = 1.8 V (standard ports) # # # # # # # # 6$$6/( ;6= 6$$6/( ;6= )/( ;M!= ) /( ;M!= AI Doc ID 15962 Rev 5 BJ 89/122 Electrical parameters STM8L151xx, STM8L152xx NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 40. NRST pin characteristics Symbol Parameter Conditions Min Typ (1) Max VIL(NRST) NRST input low level voltage (1) VSS 0.8 VIH(NRST) NRST input high level voltage (1) 1.4 VDD VOL(NRST) IOL = 2 mA for 2.7 V ≤VDD ≤ 3.6 V NRST output low level voltage Unit V 0.4 IOL = 1.5 mA for VDD < 2.7 V 10%VDD NRST input hysteresis(3) VHYST RPU(NRST) mV (2) NRST pull-up equivalent resistor VF(NRST) NRST input filtered pulse (3) VNF(NRST) NRST input not filtered pulse (3) 30 45 60 kΩ 50 ns 300 1. Data based on characterization results, not tested in production. 2. 200 mV min. 3. Data guaranteed by design, not tested in production. Figure 31. Typical NRST pull-up resistance RPU vs VDD # # # # 0ULLUPRESISTANCE;K7= 6$$;6= AI 90/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Figure 32. Typical NRST pull-up current Ipu vs VDD 0ULL5PCURRENT;!= # # # # 6$$ ;6= AI The reset network shown in Figure 33 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 40. Otherwise the reset is not taken into account internally. Figure 33. Recommended NRST pin configuration VDD RPU RSTIN EXTERNAL RESET CIRCUIT 0.01 μF Filter INTERNAL RESET STM8L Doc ID 15962 Rev 5 91/122 Electrical parameters 9.3.7 STM8L151xx, STM8L152xx Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) SPI1 characteristics Parameter Min Max Master mode 0 8 Slave mode 0 8 SPI1 clock rise and fall time Capacitive load: C = 30 pF - 30 NSS setup time Slave mode 4 x 1/fSYSCLK - NSS hold time Slave mode 80 - SCK high and low time Master mode, fMASTER = 8 MHz, fSCK= 4 MHz 105 145 Master mode 30 - Slave mode 3 - Master mode 15 - Slave mode 0 - SPI1 clock frequency (2) tw(SCKH) tw(SCKL)(2) Conditions(1) tsu(MI) (2) tsu(SI)(2) Data input setup time th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK tdis(SO)(2)(4) 30 - Data output disable time Slave mode (2) Data output valid time Slave mode (after enable edge) - 60 tv(MO)(2) Data output valid time Master mode (after enable edge) - 20 Slave mode (after enable edge) 15 - Master mode (after enable edge) 1 - tv(SO) th(SO)(2) th(MO)(2) Data output hold time 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z. 92/122 Doc ID 15962 Rev 5 Unit MHz ns STM8L151xx, STM8L152xx Electrical parameters Figure 34. SPI1 timing diagram - slave mode and CPHA=0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134 Figure 35. SPI1 timing diagram - slave mode and CPHA=1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15962 Rev 5 93/122 Electrical parameters STM8L151xx, STM8L152xx Figure 36. SPI1 timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 94/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 42. Symbol I2C characteristics Parameter Standard mode I2C Fast mode I2C(1) Min(2) Min (2) Max (2) Unit Max (2) tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 0 tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) START condition hold time 4.0 0.6 tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 μs STOP to START condition time (bus free) 4.7 1.3 μs tw(STO:STA) Cb Capacitive load for each bus line 400 μs 900 ns μs 400 pF 1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. Note: For speeds around 200 kHz, the achieved speed can have a± 5% tolerance For other speed ranges, the achieved speed can have a± 2% tolerance The above variations depend on the accuracy of the external components used. Doc ID 15962 Rev 5 95/122 Electrical parameters STM8L151xx, STM8L152xx Figure 37. Typical application with I2C bus and timing diagram 1) VDD 4.7kΩ I2C VDD 4.7kΩ BUS 100Ω SDA 100Ω SCL STM8L REPEATED START START tsu(STA) tw(STO:STA) SDA tr(SDA) tf(SDA) tsu(SDA) th(SDA) tr(SCL) tf(SCL) STOP SCL th(STA) tw(SCLH) tw(SCLL) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 96/122 Doc ID 15962 Rev 5 tsu(STO) START STM8L151xx, STM8L152xx 9.3.8 Electrical parameters LCD controller (STM8L152xx only) Table 43. LCD characteristics(1) Symbol Parameter VLCD LCD external voltage VLCD0 LCD internal reference voltage 0 2.6 V VLCD1 LCD internal reference voltage 1 2.7 V VLCD2 LCD internal reference voltage 2 2.8 V VLCD3 LCD internal reference voltage 3 2.9 V VLCD4 LCD internal reference voltage 4 3.0 V VLCD5 LCD internal reference voltage 5 3.1 V VLCD6 LCD internal reference voltage 6 3.2 V VLCD7 LCD internal reference voltage 7 3.3 V CEXT VLCD external capacitance Supply current(2) Min Typ 0.1 Unit 3.6 V 2 µF 3 µA Supply current(2) at VDD = 3 V 3 µA Low drive resistive network 6.6 MΩ RLN (4) (= 3 X RL) High drive resistive network 360 kΩ V33 Segment/Common higher level voltage V23 Segment/Common 2/3 level voltage 2/3VLCDx V V12 Segment/Common 1/2 level voltage 1/2VLCDx V V13 Segment/Common 1/3 level voltage 1/3VLCDx V V0 Segment/Common lowest level voltage IDD at VDD = 1.8 V Max. (3) RHN (= 3 X RH) VLCDx 0 V V 1. Data guaranteed by Design, not tested in production. 2. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels active, no LCD connected. 3. RHN is the total resistive network value. The bridge is made of 3 RH serial resistors. 4. RLN is the total resistive network value. The bridge is made of 3 RL serial resistors. VLCD external capacitor (STM8L152xx only) The application can achieve a stabilized LCD reference voltage by connecting an external capacitor CEXT to the VLCD pin. CEXT is specified in Table 43. Doc ID 15962 Rev 5 97/122 Electrical parameters 9.3.9 STM8L151xx, STM8L152xx Embedded reference voltage Based on characterization results, unless otherwise specified. Table 44. Reference voltage characteristics Symbol Parameter Conditions Min Typ Max. Unit IREFINT Internal reference voltage consumption 1.4 TS_VREFINT ADC sampling time when reading the internal reference voltage(1) 5 10 µs IBUF Internal reference voltage buffer consumption (used for ADC) 13.5 25 µA VREFINT out Reference voltage output 1.202 1.224 1.242 VREFINT_DIV1 1/4 reference voltage 25 VREFNT_DIV2 1/2 reference voltage 50 VREFNT_DIV3 3/4 reference voltage 75 ILPBUF Internal reference voltage low power buffer consumption (used for comparators or output) 730 IREFOUT µA V %VREFINT_COMP 1200 nA Buffer output current(2) 1 µA CREFOUT Reference voltage output load 50 pF tVREFINT Internal reference voltage startup time 3 ms tBUFEN Internal reference voltage buffer startup time once enabled (1) 10 µs ACCVREFINT Accuracy of VREFINT stored in the VREFINT_Factory_CONV byte(3) ±5 mV 50 ppm/°C 20 ppm/°C TBD ppm STABVREFINT STABVREFINT 2 Stability of VREFINT over temperature -40 °C ≤TA ≤ 125 °C Stability of VREFINT over temperature 0 °C ≤TA ≤ 50 °C Stability of VREFINT after 1000 hours 20 1. Defined when ADC output reaches its final value ±1/2LSB 2. To guaranty less than 1% VREFOUT deviation 3. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy. 98/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 9.3.10 Electrical parameters Temperature sensor Based on characterization results, unless otherwise specified. Table 45. TS characteristics Symbol Parameter Sensor reference voltage at 90°C ±5 °C, V90 (1) TL Typ Max. Unit 0.580 0.597 0.614 V ±1 ±2 °C 1.62 1.65 mV/°C 3.4 6 µA 10 µs 10 µs VSENSOR linearity with temperature (2) Avg_slope Average slope IDD(TEMP) Consumption TSTART Min (2) TS_TEMP(2) Temperature sensor startup time 1.59 (3) ADC sampling time when reading the temperature sensor 5 1. Measured at VDD = 3 V ±10 mV. The 8 LSB of the V90 ADC conversion result are stored in the TS_Factory_CONV_V90 byte. 2. Guaranteed by Design, not tested in production. 3. Defined for ADC output reaching its final value ±1/2LSB. 9.3.11 Comparator characteristics Data guaranteed by design, not tested in production. Table 46. Comparator 1 characteristics Symbol VDDA Parameter Min Typ Max Unit Analog supply voltage 1.65 3.6 V Temperature range -40 125 °C R400 R400 value 300 400 500 kΩ R10 R10 value 7.5 10 12.5 kΩ VIN Comparator input voltage range 0.6 VDDA V 1.225 1.242 V Startup time after enable 7 10 µs Propagation delay(2) 3 10 µs ±10 mV 260 nA TA VREFINT tSTART td Internal reference voltage (1) Voffset Comparator offset error ICMP1 Consumption(3) 1.202 160 1. Based on characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Doc ID 15962 Rev 5 99/122 Electrical parameters STM8L151xx, STM8L152xx Data guaranteed by design, not tested in production. Table 47. Comparator 2 characteristics Symbol VDDA Parameter Min Typ Max Unit Analog supply voltage 1.65 3.6 V TA Temperature range -40 125 °C VIN Comparator input voltage range 0 VDDA V Startup time after enable in fast mode 20 µs Startup time after enable in slow mode 30 µs tdf Propagation delay in fast mode(1) 2.5 µs tds Propagation delay in slow mode(1) 6 µs ±10 mV IDD(CMP2F) Consumption in fast mode 5 µA IDD(CMP2S) Consumption in slow mode 2 µA tSTART Voffset Comparator offset error 1. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 9.3.12 12-bit DAC characteristics Data guaranteed by design, not tested in production. Table 48. DAC characteristics Symbol Parameter VDDA Conditions Min Typ Max Unit Analog supply voltage 1.8 3.6 V TA Temperature range -40 125 °C IDD(DAC)(1) DAC supply current IVREF+ Middle code 370 550 Worst code 500 700 140 360 µA Current on VREF+ supply RL Resistive load(2) (3) DACOUT buffer ON RO Output impedance DACOUT buffer OFF CL Capacitive 8 Settling time (full scale: for a 12bit input code transition between the lowest and the highest input codes when DAC_OUT reaches the final value ±1LSB) 10 kΩ 50 pF DACOUT buffer ON 0.2 VREF+-0.2 V DACOUT buffer OFF 0 VREF+ -1 LSB V 12 µs 1 Msps RL ≥5 kΩ, CL≤ 50 pF Max frequency for a correct DAC_OUT (@95%) change when RL ≥ 5 kΩ, CL ≤50 pF Update rate small variation of the input code (from code i to i+1LSB). 100/122 kΩ load(4) DAC_OUT DAC_OUT voltage(5) tsettling 5 µA Doc ID 15962 Rev 5 7 STM8L151xx, STM8L152xx Table 48. Electrical parameters DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit tWAKEUP Wakeup time from OFF state. Input code between lowest and highest possible codes. RL ≥5 kΩ, CL≤50 pF 9 15 µs PSRR+ Power supply rejection ratio (to VDDA) (static DC measurement) RL≥ 5 kΩ, CL≤50 pF -60 -35 dB Typ Max Unit 1.5 3 1.5 3 2 4 1. Includes supply current on VDDA and VREF+ 2. Resistive load between DACOUT and GNDA 3. Output on PF0 (48-pin package only) 4. Capacitive load at DACOUT pin 5. It gives the output excursion of the DAC Data based on characterization results, not tested in production. Table 49. DAC accuracy Symbol Parameter Conditions RL ≥5 kΩ, CL≤50 pF DNL DACOUT buffer ON(2) (1) Differential non linearity No load DACOUT buffer OFF RL ≥5 kΩ, CL≤ 50 pF INL Integral non DACOUT buffer ON(2) linearity(3) No load DACOUT buffer OFF 2 4 ±10 ±25 No load DACOUT buffer OFF ±5 ±8 DACOUT buffer OFF ±1.5 ±5 ±0.2 ±0.5 RL ≥5 kΩ, CL≤ 50 pF Offset Offset1 Offset error DACOUT buffer ON(2) (4) Offset error at Code 1 (5) RL ≥5 kΩ, CL≤ 50 pF Gain error DACOUT buffer ON(2) Gain error No load DACOUT buffer OFF RL ≥5 kΩ, CL≤ 50 pF TUE DACOUT buffer ON(2) Total unadjusted error 12-bit LSB No load DACOUT buffer OFF % ±0.3 ±0.5 12 30 12-bit LSB 8 12 1. Difference between two consecutive codes - 1 LSB. 2. For 48-pin packages only. For 28-pin and 32-pin packages, DAC output buffer must be kept off and no load must be applied. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023. 4. Difference between measured value and ideal value = VREF/2. Doc ID 15962 Rev 5 101/122 Electrical parameters STM8L151xx, STM8L152xx 5. Difference between measured value and ideal value Code 1. Table 50. DAC output on PB4-PB5-PB6(1) Symbol Rint Parameter Internal resistance between DAC output and PB4-PB5-PB6 output Conditions Max 2.7 V < VDD < 3.6 V 1.4 2.4 V < VDD < 3.6 V 1.6 2.0 V < VDD < 3.6 V 3.2 1.8 V < VDD < 3.6 V 8.2 Unit kΩ 1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing interface I/O switch registers. 12-bit ADC1 characteristics Table 51. Symbol ADC1 characteristics Parameter (1) VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IVDDA Current on the VDDA input pin IVREF+ Conditions 2.4 V ≤VDDA≤ 3.6 V Min (1) Max(1) Unit 1.8 3.6 V 2.4 VDDA V 1.8 V≤VDDA≤ 2.4 V Typ(1) VDDA V VSSA V 1000 Current on the VREF+ input pin 1450 µA 700 (peak)(2) µA 450 (average)(2) µA 400 VAIN Conversion voltage range 0(3) VREF+ TA Temperature range -40 125 °C 50(4) kΩ RAIN External resistance on VAIN CADC Internal sample and hold capacitor fADC 102/122 ADC sampling clock frequency on PF0 fast channel on all other channels on PF0 fast channel 16 pF on all other channels 2.4 V≤VDDA≤3.6 V without zooming 0.320 16 MHz 1.8 V≤VDDA≤2.4 V with zooming 0.320 8 MHz Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 51. Symbol fCONV Electrical parameters ADC1 characteristics (continued) Parameter (1) Max(1) Unit VAIN on PF0 fast channel 1(4)(5) MHz VAIN on all other channels 760(4)(5) kHz Conditions Min (1) Typ(1) 12-bit conversion rate fTRIG External trigger frequency tconv 1/fADC tLAT External trigger latency 3.5 1/fSYSCLK tS Sampling time tconv 12-bit conversion time tWKUP Wakeup time from OFF state tIDLE(6) Time before a new conversion tVREFINT VAIN on PF0 fast channel VDDA < 2.4 V 0.43(4)(5) µs VAIN on PF0 fast channel 2.4 V ≤VDDA≤ 3.6 V 0.22(4)(5) µs VAIN on slow channels VDDA < 2.4 V 0.86(4)(5) µs VAIN on slow channels 2.4 V ≤VDDA≤ 3.6 V 0.41(4)(5) µs 16 MHz 12 + tS 1/fADC 1(4) µs 3 µs TA = +25 °C 1 s TA = +70 °C 20 ms TA = +125 °C 2 ms refer to Table 44 ms Internal reference voltage startup time 1. Data guaranteed by design, not tested in production. 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 µA) - one variable (max 400 µA), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at 1Msps 3. VREF- or VDDA must be tied to ground. 4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ.. 5. Value obtained for continuous conversion on fast channel. 6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE. Doc ID 15962 Rev 5 103/122 Electrical parameters Table 52. STM8L151xx, STM8L152xx ADC1 accuracy with VDDA = 3.3 V to 2.5 V Typ Max(1) 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.5 fADC = 4 MHz 0.7 1.2 Symbol Parameter Conditions fADC = 16 MHz DNL INL TUE Offset Integral non linearity Total unadjusted error Offset error Unit LSB LSB fADC = 16 MHz Gain Gain error fADC = 8 MHz 1 1.5 fADC = 4 MHz 1. Data based on characterization, not tested in production. Table 53. ADC1 accuracy with VDDA = 2.4 V to 3.6 V Symbol Parameter Typ Max(1) Unit 1 2 LSB 1.7 3 LSB DNL Differential non linearity INL Integral non linearity TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1.5 3 LSB Typ Max(1) Unit 1. Data based on characterization, not tested in production. Table 54. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V Symbol Parameter DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB 1. Data based on characterization, not tested in production. 104/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Figure 38. ADC1 accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 39. Typical connection diagram using the ADC 34-,XXX 6$$ 2!). 6!). 3AMPLEANDHOLD!$# CONVERTER 64 6 2!$# !).X #PARASITIC 64 6 ),N! BIT CONVERTER #!$# AIC 1. Refer to Table 51 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 40 or Figure 41, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Doc ID 15962 Rev 5 105/122 Electrical parameters STM8L151xx, STM8L152xx Figure 40. Power supply and reference decoupling (VREF+ not connected to VDDA) STM8L V REF+ 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF- ai17031 Figure 41. Power supply and reference decoupling (VREF+ connected to VDDA) STM8L VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai17032 9.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 106/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Electrical parameters Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard. ● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 55. EMS data Symbol Parameter Conditions VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fCPU= 16 MHz, conforms to IEC 61000 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, Using HSI fCPU = 16 MHz, conforms to IEC 61000 Using HSE Level/ Class 3B 4A 2B Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin. Doc ID 15962 Rev 5 107/122 Electrical parameters STM8L151xx, STM8L152xx Table 56. EMI data (1) Symbol Parameter SEMI VDD = 3.6 V, TA = +25 °C, LQFP32 conforming to IEC61967-2 Peak level Monitored frequency band Conditions Max vs. Unit 16 MHz 0.1 MHz to 30 MHz -3 30 MHz to 130 MHz -9 130 MHz to 1 GHz 4 SAE EMI Level 2 dBμV - 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. Table 57. ESD absolute maximum ratings Symbol VESD(HBM) VESD(CDM) Ratings Conditions Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Maximum value (1) Unit 2000 TA = +25 °C V 500 1. Data based on characterization results, not tested in production. Static latch-up ● LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 58. Electrical sensitivities Symbol LU 108/122 Parameter Static latch-up class Doc ID 15962 Rev 5 Class II STM8L151xx, STM8L152xx 9.4 Electrical parameters Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 17: General operating conditions on page 63. The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: ● TAmax is the maximum ambient temperature in ° C ● ΘJA is the package junction-to-ambient thermal resistance in ° C/W ● PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) ● PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. ● PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*I OH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 59. Symbol Thermal characteristics(1) Parameter Value Unit ΘJA Thermal resistance junction-ambient UFQFPN28 - 4 x 4 mm 118 °C/W ΘJA Thermal resistance junction-ambient WLCSP28 70 °C/W ΘJA Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm 59 °C/W ΘJA Thermal resistance junction-ambient UFQFPN 32 - 5 x 5 mm 38 °C/W ΘJA Thermal resistance junction-ambient LQFP 48- 7 x 7 mm 65 °C/W ΘJA Thermal resistance junction-ambient UFQFPN 48- 7 x 7mm 32 °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. Doc ID 15962 Rev 5 109/122 Package characteristics STM8L151xx, STM8L152xx 10 Package characteristics 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 110/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 10.2 Package characteristics Package mechanical data Figure 42. UFQFPN28 – 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4)(1) " 5 Figure 43. Recommended footprint (dimensions in mm)(1) - C F !"?-" 1. Drawing is not to scale. Doc ID 15962 Rev 5 111/122 Package characteristics Table 60. STM8L151xx, STM8L152xx UFQFPN28 – 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0 0.050 0 0 0.002 D 3.900 4.000 4.100 0.1535 0.1575 0.1614 E 3.900 4.000 4.100 0.1535 0.1575 0.1614 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 L1 0.250 0.350 0.450 0.0098 0.0138 0.0177 T b e 0.152 0.200 0.250 0.0060 0.300 0.0079 0.500 0.0197 Number of pins N 28 1. Values in inches are converted from mm and rounded to 4 decimal digits. 112/122 0.0098 Doc ID 15962 Rev 5 0.0118 STM8L151xx, STM8L152xx Package characteristics Figure 44. WLCSP28 – 28-pin wafer level chip scale package, package outline : $ E 8 9 E E !BALL LOCATION $ETAIL! E % .OTCH ' AAA 8 7AFERBACKSIDE ! ! & 3IDEVIEW $IE)$ "UMPSIDE "UMP ! EEE: : 3EATINGPLANE BX $ETAIL! ROTATEDBY # -%?!!- Table 61. WLCSP28 – 28-pin wafer level chip scale package, package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.440 0.590 0.640 0.0173 0.0232 0.0252 A1 0.165 0.190 0.215 0.0065 0.0075 0.0085 A2 0.375 0.400 0.425 0.0148 0.0157 0.0167 b 0.265 0.270 0.275 0.0104 0.0106 0.0108 D 1.677 1.697 1.717 0.0660 0.0668 0.0676 E 2.815 2.835 2.855 0.1108 0.1116 0.1124 e1 1.190 1.200 1.210 0.0469 0.0472 0.0476 e2 0.390 0.400 0.410 0.0154 0.0157 0.0161 e3 0.390 0.400 0.410 0.0154 0.0157 0.0161 Doc ID 15962 Rev 5 113/122 Package characteristics Table 61. STM8L151xx, STM8L152xx WLCSP28 – 28-pin wafer level chip scale package, package mechanical data (continued) inches(1) mm Dim. Min Typ Max Min Typ Max e4 2.390 2.400 2.410 0.0941 0.0945 0.0949 F 0.239 0.249 0.259 0.0094 0.0098 0.0102 G 0.208 0.218 0.228 0.0082 0.0086 0.0090 eee 0.050 0.0020 Number of pins N 28 1. Values in inches are converted from mm and rounded to 4 decimal digits. 114/122 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Package characteristics Figure 45. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5)(1)(2)(3) Figure 46. UFQFPN32 recommended footprint(1)(4) Seating plane C ddd C A A1 A3 D e 16 9 17 8 E b E2 24 1 L 32 Pin # 1 ID R = 0.30 D2 L Bottom view A0B8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters. Table 62. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.5 0.55 0.6 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0 0.0008 0.0020 A3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 D 4.90 5.00 5.10 0.1929 0.1969 0.2008 D2 3.50 0.1378 E 4.90 5.00 5.10 0.1929 0.1969 0.2008 E2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e L ddd 0.500 0.30 0.40 0.0197 0.50 0.0118 0.08 0.0157 0.0197 0.0031 Number of pins N 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15962 Rev 5 115/122 Package characteristics STM8L151xx, STM8L152xx Figure 47. LQFP32 – 32-pin low profile quad flat package outline ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 Pin 1 identification E1 E 9 L A1 1 K c 8 5V_ME Table 63. LQFP32 – 32-pin low profile quad flat package, package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.6 A1 0.05 A2 1.35 b 0.3 c 0.09 D 8.8 D1 6.8 D3 Max 0.063 0.15 0.0020 1.4 1.45 0.0531 0.0551 0.0571 0.37 0.45 0.0118 0.0146 0.0177 0.2 0.0035 9 9.2 0.3465 0.3543 0.3622 7 7.2 0.2677 0.2756 0.2835 5.6 0.0059 0.0079 0.2205 E 8.8 9 9.2 0.3465 0.3543 0.3622 E1 6.8 7 7.2 0.2677 0.2756 0.2835 E3 5.6 0.2205 e 0.8 0.0315 L 0.45 L1 k ccc 0.6 0.75 0.0177 1 0.0 ° 3.5 ° 7.0 ° 0.0 ° 0.1 3.5 ° 0.0039 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. 116/122 0.0295 0.0394 Number of pins N 0.0236 Doc ID 15962 Rev 5 7.0 ° STM8L151xx, STM8L152xx Package characteristics Figure 48. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 49. Recommended footprint outline(1)(2)(3) (dimensions in mm)(1) 7.30 48 37 1 ! 36 4 6.20 0.20 7.30 B E 6.20 5.60 5.80 5.60 0.30 12 25 13 0.55 24 5.80 0.50 0.75 ai15697 !"?-) 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. Table 64. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T b e 0.152 0.200 0.250 0.0060 0.300 0.0079 0.500 0.0098 0.0118 0.0197 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15962 Rev 5 117/122 Package characteristics STM8L151xx, STM8L152xx Figure 50. LQFP48 – 48-pin low profile quad flat package outline (7x7) D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME Table 65. LQFP48 – 48-pin low profile quad flat package (7x7), package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.6 A1 0.05 A2 1.35 b 0.17 c 0.09 D 8.8 D1 6.8 D3 Max 0.063 0.15 0.002 1.4 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.2 0.0035 9 9.2 0.3465 0.3543 0.3622 7 7.2 0.2677 0.2756 0.2835 5.5 0.0059 0.0079 0.2165 E 8.8 9 9.2 0.3465 0.3543 0.3622 E1 6.8 7 7.2 0.2677 0.2756 0.2835 E3 5.5 0.2165 e 0.5 0.0197 L 0.45 L1 k ccc 0.6 0.75 0.0177 1 0.0° 3.5° 7.0° 0.0° 0.08 3.5° 7.0° 0.0031 48 1. Values in inches are converted from mm and rounded to 4 decimal digits. 118/122 0.0295 0.0394 Number of pins N 0.0236 Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx 11 Device ordering information Device ordering information Figure 51. STM8L15xxx ordering information scheme Example: STM8 L 151 C 4 U 6 Product class STM8 microcontroller Family type L = Low power Sub-family type 151 = Ultralow power 152 = Ultralow power with LCD Pin count C = 48 pins K = 32 pins G = 28 pins Program memory size 4 = 16 Kbytes 6 = 32 Kbytes Package U = UFQFPN T = LQFP Y = WLCSP Temperature range 3 = - 40 °C to 125 °C 6 = - 40 °C to 85 °C For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the ST sales office nearest to you. Doc ID 15962 Rev 5 119/122 Revision history 12 STM8L151xx, STM8L152xx Revision history Table 66. Document revision history Date Revision 06-Aug-2009 1 Initial release 2 Updated peripheral naming throughout document. Added Figure 7: STM8L151Cx 48-pin pinout (without LCD) on page 25 Added capacitive sensing channels in Features on page 1 Updated PA7, PC0 and PC1 in Table 5: STM8L15x pin description Changed CLK and REMAP register names in Table 8 Changed description of WDGHALT in Table 12 Added typical power consumption values in Table 18 to Table 26 Correct VIH max in Table 36 3 Added WLCSP28 package Modified Figure 9: Memory map on page 35 and added 2 notes. Modified Low power run mode in Section 3.1: Low power modes on page 14 Added Section 8: Unique ID on page 59 Modified Table 10: Interrupt mapping on page 54 (added reserved area at address 0x00 8008) Modified OPT4 option bits in Table 11: Option byte addresses on page 56 Table 12: Option byte description on page 57: modified OPT0 description (“disable” instead of “enable”) and OPT1 description Added OPTBL option bytes Modified Section 9: Electrical parameters on page 60 4 Changed title of the document (STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6) Changed pinout (VSS1, VDD1, VSS2, VDD 2 instead of VSS, VDD, VSSIO, VDDIO Changed packages Changed first page Modified note 1 in Table 5: STM8L15x pin description on page 27 Added note to PA7, PC0, PC1 and PE0 in Table 5: STM8L15x pin description on page 27 Modified Figure 9: Memory map on page 35 Modified Table 61: WLCSP28 – 28-pin wafer level chip scale package, package mechanical data on page 113 (min and max columns swapped) Modified Figure 44: WLCSP28 – 28-pin wafer level chip scale package, package outline on page 113 (A1 ball location) Section : on page 79: renamed Rm, Lm and Cm EXTI_CONF replaced with EXTI_CONF1 in Table 8: General hardware register map on page 37 Updated Section 9: Electrical parameters on page 60 10-Sep-2009 11-Dec-2009 02-Apr-2010 120/122 Changes Doc ID 15962 Rev 5 STM8L151xx, STM8L152xx Table 66. Revision history Document revision history Date 23-Jul-2010 Revision Changes 5 Modified Introduction and Description Modified Table 4: Legend/abbreviation for table 5 on page 27 and Table 5: STM8L15x pin description on page 27 (for PA0, PA1, PB0 and PB4 and for reset states in the floating input column) Modified Figure 1: STM8L15xxx device block diagram on page 13 and Figure 2: STM8L15x clock tree diagram on page 18 Modified Figure 3.1: Low power modes on page 14 and Figure 3.5: Low power real-time clock on page 18 Modified CLK_PCKENR2 and CLK_HSICALR reset values in Table 8: General hardware register map on page 37 Modified notes below Figure 9: Memory map on page 35 Modified PA_CR1 reset value in Table 7 on page 36 Modified reset values for Px_IDR registers in Table 7 on page 36 Modified Table 14: Voltage characteristics on page 61, Table 15: Current characteristics on page 62 Modified VIH in Table 36: I/O static characteristics on page 85 Modified Table 20: Total current consumption in Wait mode on page 69 Modified Figure 37: Typical application with I2C bus and timing diagram 1) on page 96 Modified IL value in Figure 39: Typical connection diagram using the ADC on page 105 Modified RH and RL in Table 43: LCD characteristics on page 97 Added graphs in Section 9: Electrical parameters on page 60 Modified note 3 below Table 44: Reference voltage characteristics on page 98 Added notes to Modified note 1 below Table 45: TS characteristics on page 99 Changed VESD(CDM) value in Table 57 on page 108 Modified notes or added notes below UFQFPN32 and UFQFPN48 packages Doc ID 15962 Rev 5 121/122 STM8L151xx, STM8L152xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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