SY100S350 Micrel, Inc. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems. When both enable signals (Ea and Eb) are at a logic LOW, the latches are transparent and the input signals( D0–D5) appear at the outputs (Q0–Q5) after a propagation delay. If either or both of the enable signals are at a logic HIGH, then the latches store the last valid data present on its inputs before Ea or Eb went to a logic HIGH. The Master Reset (MR) overrides all other input signals and takes the outputs to a logic LOW state. All inputs have 75kΩ pull-down resistors. Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75kΩ input pull-down resistors More than 40% faster than Fairchild Approximately 30% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 28-pin PLCC package BLOCK DIAGRAM D5 Eb Ea MR D4 PIN NAMES Pin Function D0 — D5 Data Inputs Ea, Eb Common Enable Inputs (Active LOW) MR Asynchronous Master Reset Input Q0 — Q5 Data Outputs Q0 — Q5 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs D E D1 M9999-042307 [email protected] or (408) 955-1690 R Q3 Q2 R Q2 Q1 R D E Q4 Q3 D E D0 R D E Q5 Q4 D E D2 R D E D3 Q5 Q1 Q0 R Q0 Rev.: I 1 Amendment: /0 Issue Date: April 2007 SY100S350 Micrel, Inc. Ordering Information Q1 Q1 Q0 D0 Q0 VEES D1 PACKAGE/ORDERING INFORMATION 11 10 9 8 7 6 5 D2 12 13 D3 VEE VEES 4 3 14 15 Ea 16 17 Eb 18 MR Q2 Q2 VCCA 2 1 Top View PLCC J28-1 VCC VCC 28 27 Q3 26 Q3 Part Number Package Type Operating Range Package Marking Lead Finish SY100S350JC J28-1 Commercial SY100S350JC Sn-Pb SY100S350JCTR(1) J28-1 Commercial SY100S350JC Sn-Pb SY100S350JZ(2) J28-1 Commercial SY100S350JZ with Pb-Free bar-line indicator Matte-Sn SY100S350JZTR(1, 2) J28-1 Commercial SY100S350JZ with Pb-Free bar-line indicator Matte-Sn Notes: Q4 Q5 Q4 VEES D5 Q5 D4 19 20 21 22 23 24 25 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. 28-Pin PLCC (J28-1) TRUTH TABLE(1) Each Latch Inputs Outputs Dn Ea Eb MR Qn Qn Operating Mode H L X X L L X H L L H X L L L L H L Latched(2) Latched(2) L H Latched(2) Latched(2) Latch X X X H L H Asynchronous NOTES: 1. H = HIGH State L = LOW State X = Don't Care 2. Retains data that is present before E positive transition. M9999-042307 [email protected] or (408) 955-1690 2 SY100S350 Micrel, Inc. DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Min. Input HIGH Current MR Dn Ea, Eb Power Supply Current Typ. Max. — — — — — — 250 250 250 –98 –78 –49 Unit Condition µA VIN = VIH (Max.) mA Inputs Open AC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dn to Output 300 900 300 900 300 900 ps tPLH tPHL Propagation Delay Ea, Eb to Output 300 1000 300 1000 300 1000 ps tPLH tPHL Propagation Delay MR to Output 300 1200 300 1200 300 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time, Dn to En 500 — 500 — 500 — ps tH Hold Time, Dn to En 500 — 500 — 500 — ps tr Release Time, MR to En 1000 — 1000 — 1000 — ps tPW (L) Pulse Width, Ea, Eb 1000 — 1000 — 1000 — ps tPW (H) Pulse Width, MR 1000 — 1000 — 1000 — ps M9999-042307 [email protected] or (408) 955-1690 3 Condition SY100S350 Micrel, Inc. TIMING DIAGRAMS 0.7 ± 0.1 ns –0.95V DATA –1.69V tW(L) –0.95V ENABLE LATCHES TRANSPARENT TRANSPARENT –1.69V tPHL, tPLH tPHL, tPLH tPHL, tPLH 80% 50% 20% OUTPUT tTHL, tTLH Enable Timing Note: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND DATA ENABLE LATCHED TRANSPARENT TRANSPARENT tR RELEASE TIME MR tW(L) tPHL, tPLH tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing DATA tS th ENABLE Data Set-up and Hold Times Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-042307 [email protected] or (408) 955-1690 4 SY100S350 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. A MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-042307 [email protected] or (408) 955-1690 5