Micrel, Inc. Precision Edge® ® SY89536L Precision Edge 3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER SY89536L FEATURES ■ Integrated synthesizer plus fanout buffers, clock dividers, and translator in a single 64-pin package ■ Accepts any reference input between 14MHz to 160MHz (single-ended or differential) ■ 33MHz to 500MHz output frequency range ■ LVPECL and HSTL outputs ■ 3.3V ±10% power supply ■ Low jitter: <50ps cycle-to-cycle ■ Low pin-to-pin skew: <50ps ■ TTL/CMOS compatible control logic ■ 3 independently programmable output frequency banks: • 9 differential output pairs @BankB (HSTL) • 2 differential output pairs @BankA (LVPECL) • 2 differential output pairs @BankC (LVPECL) ■ Available in 64-pin EPAD-TQFP Precision Edge® DESCRIPTION The SY89536L programmable clock synthesizer is part of a 3.3V, high-frequency, precision PLL-based clock synthesizer family optimized for multi-frequency, large clocktree applications. This device integrates the following blocks into a single monolithic IC: • • • • The SY89536L includes a flexible input design that accepts any reference input; single-ended LVTTL/CMOS, SSTL and differential LVPECL, LVDS, HSTL, and CML. This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a crystal oscillator, see the SY89531L. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. APPLICATIONS ■ ■ ■ ■ ■ PLL (Phase-Lock-Loop)-based synthesizer Fanout buffer Clock generator (divider) Logic translation (LVPECL, HSTL) PRODUCT SELECTION GUIDE Servers Workstations Parallel processor-based systems Other high-performance computing Communications Input Device Crystal Output Reference BankA BankB BankC HSTL LVPECL SY89531L* X LVPECL SY89532L* X LVPECL LVPECL LVPECL SY89533L* X LVPECL LVDS LVPECL SY89534L* X LVPECL LVPECL LVPECL SY89535L* X LVPECL LVDS LVPECL SY89536L X LVPECL HSTL LVPECL *Refer to individual data sheet for details. Precision Edge is a registered trademark of Micrel, Inc. M9999-110405 [email protected] or (408) 955-1690 Rev.: C 1 Amendment: /0 Issue Date: October 2005 Precision Edge® SY89536L Micrel, Inc. PACKAGE/ORDERING INFORMATION NC* GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB QB0 Ordering Information(1) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC* NC* NC* GND PSEL1 PSEL0 LOOP_REF LOOP_FILTER GND REFCLK /REFCLK VBB_REF M(3) M(2) M(1) M(0) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 GND FSEL_B2 FSEL_B1 FSEL_B0 GND VCCOB VCCOB /QB8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /QB0 QB1 /QB1 QB2 /QB2 QB3 /QB3 QB4 /QB4 QB5 /QB5 QB6 /QB6 QB7 /QB7 QB8 Part Number Package Type Operating Range Package Marking Lead Finish SY89536LHC H64-1 Commercial SY89536LHC Sn-Pb SY89536LHCTR(2) H64-1 Commercial SY89536LHC Sn-Pb SY89536LHH(3) H64-1 Commercial SY89536LHH with Pb-Free Pb-Free bar-line indicator NiPdAu SY89536LHHTR(2, 3) H64-1 Commercial SY89536LHH with Pb-Free Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 64-Pin EPAD-TQFP (H64-1) *NC: Do not connect, leave floating. M9999-110405 [email protected] or (408) 955-1690 2 Precision Edge® SY89536L Micrel, Inc. PIN DESCRIPTION Power Pin Number Pin Name Pin Function 60, 61 VCC_Logic Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 62 VCCA Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 55 30, 31, 50 21 VCCOA VCCOB VCCOC 4, 9, 25, 63, 29 (exposed pad) GND Power for Output Drivers: Connect VCCOA and VCCOC pins to 3.3V supply and VCCOB pins to 1.8V supply. Ground: All GND pins must be tied together on the PCB. Exposed pad must be soldered to a ground plane. Configuration Pin Number Pin Name Pin Function 4 VCO_SEL LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default condition is logic HIGH). Internal 25kΩ pull-up. 5, 6 PSEL(1:0) LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25kΩ pull-up. Default is logic HIGH. See “Pre-Divide Frequency Select” table. 7 LOOP REF Analog Input/Output: Provides the reference voltage for PLL loop filter. 8 LOOP FILTER 13,14,15,16 M (3:0) 22, 23, 24 FSEL_C (2:0) LVTTL/CMOS Compatible Input: Bank C post-divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_C0 = LSB. 26, 27, 28 FSEL_B (2:0) LVTTL/CMOS Compatible Input: Bank B post-divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_B0 = LSB. 56, 57, 58 FSEL_A (2:0) LVTTL/CMOS Compatible Input: Bank A post-divide select. Internal 25kΩ pull-up. Default is logic HIGH. See Post-Divide Frequency Select” table. FSEL_A0 = LSB. 59 OUT_SYNC Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter Considerations” for loop filter values. LVTTL/CMOS Compatible Input: Used to change the PLL feedback divider. Internal 25kΩ pull-up. M0 = LSB. Default is logic HIGH. See “Feedback Divide Select” table. Banks A, B, C Output Synchronous Control: (LVTTL/CMOS compatible). Internal 25kΩ pull-up. After any bank has been programmed, toggle with a HIGH-LOW-HIGH pulse to resynchronize all output banks. Input/Output Pin Number Pin Name Pin Function 1, 2, 3 NC 10, 11 REFCLK, /REFCLK Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS, HSTL, SSTL logic levels. See “Input Interface” section. 12 VBB_REF Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA. 51, 52, 53, 54 QA1 to QA0 Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2). Terminate outputs with 50Ω to VCC –2V. See “Output Termination Recommendations” section. 32–49 QB8 to QB0 Bank B Output Drivers: Differential HSTL outputs. See “Output Termination Recommendations” section. Output frequency is controlled by FSEL_B (0:2). 17, 18, 19, 20 QC1 to QC0 Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2). Terminate outputs with 50Ω to VCC–2V. See “Output Termination Recommendations” section. 64 NC M9999-110405 [email protected] or (408) 955-1690 No Connect: Leave floating. No Connect: Leave floating. 3 Precision Edge® SY89536L Micrel, Inc. Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VIN) ................................... –0.5V to +4.0V VCC Pin Potential to Ground Pin (All VCC) .. –0.5V to +4.0V Input Voltage (VIN) ........................................ –0.5V to VCCI DC Output Current (IOUT) LVPECL, HSTL outputs ....................................... –50mA Lead Temperature (soldering, 20 sec.) ..................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage VCCOA and VCCOC .................................... 3.0V to +3.6V VCCOB ....................................................... 1.6V to +2.0V Ambient Temperature (TA) ............................. 0°C to +85°C Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: TQFP (θJA) Still-Air .............................................. 23°C/W TQFP (θJA) 200lfpm ............................................ 18°C/W TQFP (θJA) 500lfpm ............................................ 15°C/W With Die attach NOT soldered to GND, Note 3: TQFP (θJA) Still-Air .............................................. 44°C/W TQFP (θJA) 200lfpm ............................................ 36°C/W TQFP (θJA) 500lfpm ............................................ 30°C/W Package Thermal Resistance (Junction-to-Case) TQFP (θJC) ......................................................... 4.0°C/W DC ELECTRICAL CHARACTERISTICS Power Supply Symbol Parameter Condition Min Typ Max Units VCCA VCC_LOGIC PLL and Logic Supply Voltage Note 4 3.0 3.3 3.6 V VCCOA/C Bank A and C VCC Output 3.0 3.3 3.6 V VCCOB Bank B VCC Output 1.6 1.8 2.0 V — 230 295 mA LVPECL/HSTL ICC Note 1. Note 2. Note 3. Note 4. Note 5. Total Supply Current Note 5 Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. VCCA, VCC_LOGIC, VCCOA/C are not internally connected together inside the device. They must be connected together on the PCB. VCCOB is a separate supply. No load. Outputs floating, Banks A, B, and C enabled. M9999-110405 [email protected] or (408) 955-1690 4 Precision Edge® SY89536L Micrel, Inc. DC ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL Input Control Logic (VCCA, VCC_LOGIC, VCCOA/C pins = +3.3V ±10%) Symbol Parameter VIH Condition Min Typ Max Units Input HIGH Voltage 2.0 — — V VIL Input LOW Voltage — — 0.8 V IIH Input HIGH Current — — 150 µA IIL Input LOW Current — — –300 µA Min Typ Max Units 100 — — mV REFCLK (Pins 10, 11) INPUT (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%) Symbol Parameter Condition VID Differential Input Voltage VIH Input HIGH Voltage — — VCC +0.3 V VIL Input LOW Voltage –0.3 — — V Min Typ Max Units 100k LVPECL Outputs (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%) Symbol Parameter Condition VOH Output HIGH Voltage Note 6 VCC–1.145 VCC–1.020 VCC–0.895 V VOL Output LOW Voltage Note 6 VCC–1.945 VCC–1.820 VCC –1.695 V VID Differential Input Voltage Note 7 100 200 — — — — mV mV VIH Input HIGH Voltage Note 7 — — VCC +0.3 V VIL Input LOW Voltage Note 7 –0.3 — — V IIH Input HIGH Current –600 — –300 µA IIL Input LOW Current –1200 — –700 µA VBB Output Reference Voltage VCC–1.325 VCC–1.425 VCC–1.525 V HSTL Outputs (Bank B QB0:8) (All VCC pins except VCCOB = +3.3V ±10%, VCCOB = +1.8V ±10%)(Note 8) Symbol Parameter VOUT Min Typ Max Units Output Voltage Swing — 800 — mV VOH Output HIGH Voltage 1.0 — 1.2 V VOL Output LOW Voltage 0.2 — 0.4 V Note 6. Note 7. Condition 50Ω to VCC –2V. Banks A, B, and C enabled. VCC = 3.0V to 3.6V. M9999-110405 [email protected] or (408) 955-1690 5 Precision Edge® SY89536L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCC_LOGIC = VCCA/C = +3.3V ±10%, VCCOB = +1.8V ±10% Symbol Parameter Condition Min Typ Max Units fIN Reference Input Frequency 14 — 160 MHz fOUT Output Frequency Range 33.33 — 500 MHz tVCO Internal VCO Frequency Range 600 — 1000 MHz tskew Within Device Skew Within Bank PECL Note 9 — — 50 ps Within Bank HSTL Note 9 — — 75 ps Bank-to-Bank Note 9 — 60 150 ps Note 10 — — 200 ps — — 10 ms Part-to-Part Skew tLOCK Maximum PLL Lock Time tJITTER Cycle-to-Cycle Jitter Period Jitter tpw (min) (Pk-to-Pk) Note 11 — — 50 ps (rms) Note 12 — — 50 ps 50 — — ps — — 1.0 2.0 — — MHz MHz Minimum Pulse Width Target PLL Loop Bandwidth Feedback Divider Ratio: 66 Feedback Divider Ratio: 30 Note 13 Note 13 tDC fOUT Duty Cycle 45 50 55 % tr, tf Output Rise/Fall Time (20% to 80%) LVPECL_Out HSTL_Out — 100 250 — 400 400 ps ps tOUTPUT_RESET Note 14 — — 10 ns tHOLD_FSEL Note 14 5 — — ns tSETUP_FSEL Note 14 5 — — ns tOUTPUT_SYNC Note 14 1 — — VCO clock cycle — 50 — ns 500 — — ps FSEL-to-Valid Output Transition Time tSETUP_OUT_SYNC Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. All HSTL outputs loaded with 50Ω to GND. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn– Tn+1 where T is the time between rising edges of the output signal. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Using recommended loop filter components. See “Timing Diagrams." M9999-110405 [email protected] or (408) 955-1690 6 Precision Edge® SY89536L Micrel, Inc. TIMING DIAGRAMS Conditions: Internal VCO, unless otherwise stated. VCO FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME Frequency Programming VCO (ext.) FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET TIME tSETUP_OUT_SYNC Frequency Programming (External VCO Clock) VCO FSEL 001 010 FOUT OUT_SYNC fSEL to VALID OUTPUT TRANSITION TIME TIME Output Frequency Updates to Valid Output M9999-110405 [email protected] or (408) 955-1690 7 Precision Edge® SY89536L Micrel, Inc. FUNCTIONAL BLOCK DIAGRAM NC NC NC NC GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 (LSB) FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB 1 2 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 QB0 48 /QB0 3 VCO_SEL 4 PESL1 5 PSEL0 6 LOOPREF 7 LOOPFILTER 8 47 QB1 46 /QB1 45 QB2 44 /QB2 2x 0 = Use Internal PLL 1 = Bypass Internal PLL (default) 3-Bit Divider A 2, 4, 6, 8, 10, 12,18 43 QB3 A EN 42 /QB3 Mux 1 GND 9 REFCLK 10 /REFCLK 14MHz to 20MHz 11 VBB_REF 12 Pre Divider 1, 2, 4, 8 VCC—1.425V Reference or Bandgap Reference 41 QB4 5 Clock Phase Detector Charge Pump Buf 40 /QB4 VCO 3-Bit Divider B 2, 4, 6, 8, 10, 12, 18 (600MHz to 1000MHz) 600MHz to 1000MHz 39 QB5 EN M-Divide 30, 32, 34, 36, 38, 40, 42, 44, 48, 50, 52, 54, 56, 60, 62, 66 14MHz to 20MHz 38 /QB5 3 37 QB6 36 /QB6 3-Bit Divider C 2, 4, 6, 8, 10, 12, 18 (MSB) M3 13 M2 14 9x B 4 35 QB7 C EN 34 /QB7 M1 15 33 QB8 (LSB) M0 16 3 2x 32 /QB8 31 VCCOB 18 19 20 21 22 23 24 25 26 27 28 29 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 (LSB) GND FSEL_B2 FSEL_B1 FSEL_B0 (LSB) GND M9999-110405 [email protected] or (408) 955-1690 17 8 30 VCCOB Precision Edge® SY89536L Micrel, Inc. FUNCTIONAL DESCRIPTION At the core of the SY89536L clock synthesizer is a precision PLL driven by a differential or single-ended reference input. For users who wish to supply a crystal input, please use the SY89531L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. PLL Programming and Operation IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential HSTL output pairs. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A, B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A, B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOWHIGH. Setting a value of 000 for FSEL is an output disable forcing the Q outputs to be LOW and the /Q outputs to be HIGH. Doing so will decrease power consumption by approximately 5mA per bank. To determine the correct settings for SY89536L follow these steps: 1. Refer to the “Suggested Selections for Specific Customer Applications” section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a reference input frequency between 14MHz and 20MHz. The user can also choose a higher input frequency, and use the PSEL pre-divider to divide it down to the 14MHz to 20MHz range. In this example, we choose 18MHz for the reference input frequency. This results in an input/output ratio of 66/18. 4. Refer to the “Feedback Divide Select” table and the “Post-Divide Frequency Select” table to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that REFCLK ÷ PSEL × MSEL is between 600MHz and 1000MHz. M9999-110405 [email protected] or (408) 955-1690 The user may need to experiment with different REFCLK input frequencies to satisfy these requirements. 330Ω 0.2µF 470pF Loop Filter Loop Reference Figure 1. External Loop Filter Connection External Loop Filter Considerations The SY89536L features an external PLL loop filter that allows the user to tailor the PLL’s behavior to their application and operating environment. We recommend using ceramic capacitors with NPO or X7R dielectric, as they have very low effective series resistance. For applications that require ultra-low cycle-to-cycle jitter, use the components shown in Figure 1. The PLL loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. For instance, the PLL’s loop bandwidth can be decreased by using a smaller resistor in the loop filter. This results in less noise from the PLL input, but potentially more noise from the VCO. Refer to “AC Electrical Characteristics” for target PLL loop bandwidth. The designer should take care to keep the loop filter components on the same side of the board and as close as possible to the SY89536L’s LOOP_REF and LOOP_FILTER pins. To insure minimal noise pick-up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces. Power Supply Filtering Techniques As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCC_Logic, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 2. 9 Precision Edge® SY89536L Micrel, Inc. Power Supply side Ferrite Bead* Thermal Considerations This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed die pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow around the part. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology’s web site, www.amkor.com. REFCLK Input Interface The flexible REFCLK inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused REFCLK inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a resistor between the complement input and ground. See “Input Interface” section, Figures 4a through 4h. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the REFCLK inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies. Device side VCC Pins 22µF 1µF 0.01µF *For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45Ω DC, Murata P/N BLM21A1025 *For VCCOA,B,C use ferrite bead = 3A, 0.025Ω DC, Murata, P/N BLM31P005 *Component size: 0805 Figure 2. Power Supply Filtering Output Logic Characteristics See “Output Termination Recommendations” for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary output in the same manner as the normal output that is being used. Unused output pairs can be left floating. LVPECL operation: • Typical voltage swing is 700mVPP to 800mVPP into 50Ω. • Common mode voltage is VCC–1.3V, typical. • 100Ω termination across the output pair is NOT recommended for LVPECL. See “Output Termination” section, Figures 5 to 7. HSTL operation (Bank B): • Typical voltage swing is 250mVPP to 450mVPP into effective 50Ω. VCC R2 990Ω R2 990Ω REFCLK R1 825Ω /REFCLK R1 825Ω GND Figure 3. Simplified Input Structure M9999-110405 [email protected] or (408) 955-1690 10 Precision Edge® SY89536L Micrel, Inc. PRE-DIVIDE FREQUENCY SELECT TABLE (PSEL) PSEL1 (MSB) PSEL0 Reference Input Frequency 0 0 REFCLK ÷ 8 0 1 REFCLK ÷ 4 1 0 REFCLK ÷ 2 1 1 REFCLK ÷ 1 POST-DIVIDE FREQUENCY SELECT TABLE (FSEL) FSEL_A2(1) (MSB) FSEL_A1(1) FSEL_A0(1) (LSB) 0 0 0 0 0 1 VCO ÷ 2 0 1 0 VCO ÷ 4 0 1 1 VCO ÷ 6 1 0 0 VCO ÷ 8 1 0 1 VCO ÷ 10 1 1 0 VCO ÷ 12 1 1 1 VCO ÷ 18 Output Disable Function, all outputs: Q = LOW, /Q = HIGH Note 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2). M9999-110405 [email protected] or (408) 955-1690 Output Divider 11 Precision Edge® SY89536L Micrel, Inc. FEEDBACK DIVIDE SELECT TABLE (MSEL) M3 M2 M1 M0 VCO Frequency(1) 0 0 0 0 REFCLK ÷ PSEL × 34 0 0 0 1 REFCLK ÷ PSEL × 36 0 0 1 0 REFCLK ÷ PSEL × 38 0 0 1 1 REFCLK ÷ PSEL × 40 0 1 0 0 REFCLK ÷ PSEL × 42 0 1 0 1 REFCLK ÷ PSEL × 44 0 1 1 0 REFCLK ÷ PSEL × 48 0 1 1 1 REFCLK ÷ PSEL × 50 1 0 0 0 REFCLK ÷ PSEL × 52 1 0 0 1 REFCLK ÷ PSEL × 54 1 0 1 0 REFCLK ÷ PSEL × 56 1 0 1 1 REFCLK ÷ PSEL × 60 1 1 0 0 REFCLK ÷ PSEL × 62 1 1 0 1 REFCLK ÷ PSEL × 66 1 1 1 0 REFCLK ÷ PSEL × 30 1 1 1 1 REFCLK ÷ PSEL × 32 SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS(Notes 1, 2, 3) Protocol Rate (MHz) FSEL (Post Divider) MSEL (Feedback Div.) REFCLK (MHz) PSEL FOUT PCI 33 18 36 16.67 1 33 Fast Ethernet 100 6 40 15 1 100 1/8 FC 133 6 52 15.36 1 133 ESCON 200 4 50 16 1 200 FOUT = Note 1. (REFCLK ÷ PSEL × MSEL) FSEL 600MHz < (REFCLK ÷ PSEL × MSEL) < 1000MHz. Note 2. 14MHz ≤ (REFCLK ÷ PSEL) ≤ 20MHz. Note 3. Where two settings provide the user with the identical desired frequency, the setting with the higher PLL input reference frequency (and lower feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within their respective ranges. M9999-110405 [email protected] or (408) 955-1690 12 Precision Edge® SY89536L Micrel, Inc. INPUT INTERFACE VCC ≥ VCC(DRIVER) VCC(DRIVER) VCC ≥ VCC(DRIVER) VCC(DRIVER) TTL LVTTL REFCLK REFCLK /REFCLK 1% CML SY89536L 102Ω 1% /REFCLK SY89536L Figure 4b. CML DC-Coupled Figure 4a. 3.3V “TTL” VCC ≥ VCC(DRIVER) VCC(DRIVER) REFCLK 2.3V to 2.7V 3.0V to 3.6V PECL /REFCLK 2.5V LVTTL SY89536L REFCLK 50Ω 1% 50Ω 1% /REFCLK SY89536L 1% VCC—2V Figure 4c. 2.5V “LVTTL” Figure 4d. 3.3V LVPECL DC-Coupled VCC VCC(DRIVER) VCC REFCLK CML REFCLK 102Ω 1% /REFCLK HSTL 3.92kΩ 1% /REFCLK 50Ω 50Ω SY89536L SY89536L Figure 4f. CML AC-Coupled (Short Trace Lengths) Figure 4e. HSTL M9999-110405 [email protected] or (408) 955-1690 3.92kΩ 1% 13 Precision Edge® SY89536L Micrel, Inc. VCC VCC(DRIVER) 82Ω 1% 82Ω 1% VCC REFCLK CML VCC /REFCLK 130Ω 1% 130Ω 1% SY89536L REFCLK LVDS 100Ω 1% /REFCLK SY89536L Figure 4h. LVDS Figure 4g. CML AC-Coupled (Long Trace Lengths) M9999-110405 [email protected] or (408) 955-1690 14 Precision Edge® SY89536L Micrel, Inc. OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V ZO = 50Ω “Source” “Destination” Vt = VCC –2V Figure 5. PECL Parallel Termination Thevenin Equivalent (Note 1) +3.3V +3.3V ZO = 50Ω ZO = 50Ω 50Ω 50Ω “Source” “Destination” 50Ω Rb C1 (optional) 0.01µF Figure 6. PECL Three-Resistor “Y-Termination” (Notes 1, 2, 3) +3.3V +3.3V ZO = 50Ω 50Ω ZO = 50Ω 50Ω Source Destination Figure 7. HSTL Differential Termination (Note 1) Note 1. Place termination resistors as close to destination inputs as possible. Note 2. PECL Y-termination is a power-saving alternative to Thevenin termination. Note 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46Ω to 50Ω. M9999-110405 [email protected] or (408) 955-1690 15 Precision Edge® SY89536L Micrel, Inc. 64-PIN EPAD-TQFP (DIE UP) (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-110405 [email protected] or (408) 955-1690 16