TB1328FG TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic TB1328FG Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs The TB1328FG includes Audio and video SW blocks, pre-filters for AD converter, sync separations and an H/V format detector for TV signals. The TB1328FG contributes to a reduction in the proportion of PCB occupied by LCR filters and to the simplification of designs in analog interfaces. 2 The TB1328FG is equipped with an I CBUS interface through which various functions can be controlled. LQFP64-P-1010-0.50A Weight: 0.34 g (typ.) Features AUDIO SW BLOCK ・ Audio (L/R) inputs: 8 channels ・ Audio (L/R) output: 2 channels VIDEO SW BLOCK ・ CVBS inputs ・ Y/C inputs ・ Component video inputs (co-use as RGB inputs) ・ Output: 1 channel (Y/CVBS/G,C/Cb/B,Cr/R) ・ Monitor output (SY/Y/C/CVBS) VIDEO BLOCK ・ Gain switching: -3 dB / 0 dB / +3 dB(Output: 1 channel) ・ GCA-Amp for only CVBS: 4 to –6dB,6bit(Output: 1 channel) ・ Bandwidth filter: pre-filter for ADC; 5 to 46 MHz variable(Output: 1 channel) ・ +6dB Amp, No pre-filter (Monitor output) SYNC SEPARATION BLOCK ・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60 ・ HD/VD input: 1 channel; positive and negative input acceptable ・ HD/VD output: positive and negative output selectable ・ Masking pseudo-sync for copyguard signal OTHERS ・ Line detector for Japanese D-pin ・ S2, S1, insertion detection for S-pin ・ Horizontal and vertical frequency counter ・ Input signal format detection circuit ・ No-input detection ・ Automatic sync process switching mode ・ Programmable number of video inputs 1 2006-11-13 TB1328FG Block Diagram 1 (simplified complete diagram) This IC will not function with non-standard signals such as weak signals, ghost signals, etc. Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2 2006-11-13 TB1328FG Block Diagram 2 (Video block) Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. "YCbCr OUT" "CbCr PIN1" "CbCr PIN2" "CbCr PIN3" "MON OUT" "YCbCr1 OUT" as R/G/B as Cb/Cr as C as Y as CVBS 3 2006-11-13 TB1328FG Block Diagram 3 (Audio block) AR1 IN 26 ATT AL1 IN 28 ATT AR2 IN 30 ATT AL2 IN 32 ATT AR3 IN 33 ATT AL3 IN 35 ATT AR4 IN 37 ATT AL4 IN 39 ATT AR5 IN 41 ATT AL5 IN 43 ATT AR6 IN 45 ATT 5 AR1 OUT 3 AL1 OUT 15 AR2 OUT 13 AL2 OUT Total 0dB Total 0dB Total 0dB Total 0dB AL6 IN 47 ATT AR7 IN 57 ATT AL7 IN 59 ATT AR8 IN 61 ATT AL8 IN 63 ATT Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 4 2006-11-13 TB1328FG DC2(S1) 14 DC DET “DC2” DC1(S2) 1 DC DET “DC1” 21 Vdd (3.3V) 19 Vss XO 20 XTAL I2CBUS Block Diagram 4 (Other blocks) 18 SCL 17 SDA REG 3.3V (typ.) TEST clock DC4(LINE3-1) 29 DC DET “DC4” TEST DC5(LINE2-1) 31 DC DET “DC5” DC8(LINE3-2) 51 DC DET “DC8” DC9(LINE2-2) 53 DC DET “DC9” DC3(SW LINE1) 27 DC DET “DC3” DC6(LINE1-1) 34 DC DET “DC6” DC7(SW LINE2) 49 DC DET “DC7” DC10(LINE1-2) 55 DC DET “DC10” TEST TEST POL DET POL DET TEST HD IN 23 BIAS POL 8 HD OUT VD IN 22 BIAS POL 9 VD OUT SYNC2 IN 11 SYNC TIP H/V SEP H-C/D H DUMMY V SEP V-C/D V DUMMY HD WIDTH "HV OUT" TEST “HV DUMMY” 25 SYNC TIP H/V SEP FREQ COUNTER SYNC1 IN I2CBUS V SEP "HV DET" H/V SEP NO-SIGNAL DET “SIG DET” "SIG SW" 10 SYNC FILTER This IC will not function with non-standard signals such as weak signals, ghost signals, etc. Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 5 2006-11-13 6 CVBS/Y/G OUT 2 DC1(S2) 1 CVBS3 IN 64 MONITOR OUT 63 AL8 IN 62 SC2 IN VD OUT HD OUT V/S Vcc (5V) Cr/R OUT AR1 OUT Cb/B OUT AL1 OUT 10 SYNC FILTER 9 11 12 SYNC2 IN 8 V/S GND 7 13 14 15 AL2 OUT 6 DC2(S1) 5 AR2 OUT 4 AL2 IN 32 AR2 IN 30 27 26 DC3 (SW LINE1) AR1 IN 16 SDA 17 SCL 18 Vss 19 XTAL 20 Vdd (3.3V) 21 VD IN 22 HD IN 23 AU GND 24 SYNC1 IN 25 28 AL1 IN DC4(LINE3-1) 29 AU Vcc (9V) 3 45 AR6 IN 61 AR8 IN 44 SC1 IN 60 SY2 IN 43 AL5 IN 59 AL7 IN 42 SY1 IN 58 Y3/G3 IN 41 AR5 IN TB1328FG 40 Y1/G1 IN 57 AR7 IN 39 AL4 IN 56 Cb3/B3 IN 38 Cb1/B1 IN 55 DC10(LINE1-2) 37 AR4 IN 54 Cr3/R3 IN 36 Cr1/R1 IN 53 DC9(LINE2-2) 35 AL3 IN DC5(LINE2-1) 31 33 34 DC6(LINE1-1) 52 Y2/G2 IN 46 AR3 IN 51 DC8(LINE3-2) Cr2/r2 IN 50 Cb2/B2 IN 49 DC7(SW LINE2) 47 AL6 IN 48 TB1328FG Pin Assignment 2006-11-13 TB1328FG Pin Functions The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal VCC pin for the logical circuits. 21 Vdd (3.3 V) 19 Vss 7 12 16 24 V/S VCC (5 V) V/S GND AU VCC (9 V) AU GND Supply power through a resistor from pin 11 as in the Application Circuit. This pin voltage is clipped to 3.3 V (typ.) by the internal regulator. 3.3 V (typ.) GND pin for the logical circuits. VCC pin for the sync and video circuits. Connect 5.0 V (typ.) GND pin for the sync and video circuits. VCC pin for the audio circuits. Connect 9.0 V (typ.) GND pin for the audio circuits. − − − 5.0 V (typ.) − − − 9.0 V (typ.) − − 7 42 SY1 IN CVBS or Y input pin. 46 CVBS3 IN 60 SY2 IN Input the CVBS or Y signal in NTSC, PAL or SECAM via a clamp capacitor. 42 46 60 Sync tip level: 2.3 V (typ.) 200Ω 200Ω Y/CVBS signal amplitude: 1.0 Vp-p (with sync) 12 Chroma signal input pin. SC2 IN 2.9 V bias (typ.) 100.2kΩ 62 Input C signal via a capacitor. This pin’s voltage is detected and the status is returned to I2CBUS Read functions S2 or S6. It is used for detecting whether S-pin is connected or not. Burst signal amplitude: 0.3 Vp-p 3V SC1 IN 1V 44 Y2/G2 IN 58 Y3/G3 IN Y, G or CVBS input pin. 40 52 58 Input the signal via a clamp capacitor. The clamp system is selectable by CLAMP1, 2 or 3 registers. Sync tip level: 2.3 V (typ.) 200Ω Bias level: 2.9 V (typ.) Y/G/CVBS signal amplitude: 1.0 Vp-p (with sync) 3V Y1/G1 IN 52 3V/1.5V 40 100.2kΩ 200Ω 7 12 2.9 V bias (typ.) 56 Cb3/B3 IN 100.2kΩ Cb2/B2 IN Cb, B or C input pin. Input the signal via a capacitor. 7 3V 50 Cb1/B1 IN 1V 38 Cb/B signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p 2006-11-13 TB1328FG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 7 Cr, R or CVBS input pin. 54 Cr3/R3 IN Input the signal via a capacitor. 36 54 Bias level: 2.9 V (typ.) 200Ω Cr/R signal amplitude: 0.7 Vp-p (without sync) CVBS/Y signal amplitude: 1.0 Vp-p (with sync) 3V Cr1/R1 IN 3V/1.5V 36 100.2kΩ 200Ω Sync tip level: 2.3 V (typ.) 12 Cr, R or C input pin. 1V Input the signal via a capacitor. 26 AR1 IN 28 AL1 IN 30 AR2 IN 32 AL2 IN 33 AR3 IN 35 AL3 IN 37 AR4 IN 39 AL4 IN 41 AR5 IN 43 AL5 IN 45 AR6 IN 47 AL6 IN 57 AR7 IN 59 AL7 IN 61 AR8 IN 63 AL8 IN 14 DC2(S1) 31 DC5(LINE2-1) 34 DC6(LINE1-1) DC voltage input. 51 DC8(LINE3-2) 53 DC9(LINE2-2) Input the signal via a resistor for protection purposes. 55 DC10(LINE1-2) 1 DC1(S2) 49 DC7(SW LINE2) Cr/R signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p Audio input pin. Bias level: 4.4 V (typ.) Input the signal via a resistor and a capacitor. When the resistor value is 5.6 kΩ, the internal gain becomes 0 dB (typ.). DC voltage input. 150.2Ω Input the signal via a resistor for protection purposes. 3V 1V This pin is also used as test signal output pin for shipping only. 720.5Ω 1V Audio input: 2.8Ｖp-p (100%) 3V Cr2/R2 IN 3V 48 100.2kΩ 2.9 V bias (typ.) This pin is also used as test signal output pin for shipping only. 8 3V DC4(LINE3-1) 1V 29 Input the signal via a resistor for protection purposes. 1kΩ DC3(SW LINE1) 150.2Ω 27 3.25kΩ DC voltage input. 2006-11-13 TB1328FG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal Sync tip level: 1.8 V (typ.) Composite SYNC input pin to separate into H- and V-SYNC. 11 SYNC IN 2 25 SYNC IN 1 Input the signal via a clamp capacitor. or Remark: SYNC1 IN is not available when A-SYNC = 1 (ON). 1Vp-p HD or VD input pin. 23 HD IN 22 VD IN 1.45 V bias (typ.) Input a separated horizontal or vertical sync signal (1.0 to 2.0 Vp-p) via a resistor and a coupling capacitor. or The polarity of the input signal is detected and its leading edge becomes a timing trigger. 2 CVBS/Y/GOUT Video signal output pin. 4 Cb/B OUT 6 Cr/R OUT Refer to Bus Control Functions for the output from each pin. 3 AL1 OUT 5 AR1 OUT 13 AL2 OUT 15 AR2 OUT AC: -3, 0 or +3 dB (typ.) Audio signal output pin. Refer to Bus Control Functions for the output from each pin. 7 Video signal output pin for a monitor output. 64 MONITOR OUT AC: +6 dB (typ.) 64 Refer to Bus Control Functions for the output from the pin. 12 or HD or VD output pin. 8 HD OUT 9 VD OUT The polarity of the output is selectable by HV-POL register. The tailing edge of the VD-OUT has a jitter. Use the leading edge only. A filter pin for sync detection. 10 SYNC FILTER − Connect a capacitor between this pin and GND. 9 2006-11-13 TB1328FG Pin No. Pin Name 20 XTAL Function Interface Circuit Input Signal/Output Signal Crystal connection pin. − Connect a 3.579545 MHz crystal for NTSC demodulation to generate internal clocks. 7 17 SDA SDA pin for I2CBUS. 5kΩ 17 H to L: 1.3 V (typ.) L to H: 2.1 V (typ.) 50Ω ACK 19 7 18 SCL 2 SCL pin for I CBUS. 18 5kΩ H to L: 1.3 V (typ.) L to H: 2.1 V (typ.) 19 10 2006-11-13 TB1328FG BUS Control Map Write Mode Slave address: DEH SA D7 D6 D5 D4 00 (0) (0) (0) fc HALF 01 (0) (0) (0) (0) 02 (0) (0) FILPASS YC MIX 03 f0 SW 04 GCA V timing D2 D1 D0 PRESET YCbCrOUT (0) (0) 00000000 (0) (0) 00000000 MON OUT 00000000 BANDWIDTH1 GCA SW 00000000 GCA GAIN(D5～D0) 05 (0) (0) (0) (0) 06 (0) CbCr PIN3 CbCr PIN2 CbCr PIN1 07 00000000 CVBS/ＹGAIN (0) CbCr GAIN CLAMP3 CLAMP2 00000000 CLAMP1 (00000000)TEST0 08 09 D3 00000000 AU2 OUT (0) (0) AU1 OUT (0) (0) 00000000 (0) (0) 00010001 (0) (0) 00000000 0A (0) (0) (0) (0) (0) (0) (0) (0) 00000000 0B (0) (0) (0) (0) (0) (0) (0) (0) 00000001 (0) (0) 0C HV-SEP2 HV-SEP1 SYNC LPF2 SYNC LPF1 00000000 0D A-SYNC SIG LPF (0) (0) (0) (0) (0) (0) 00000000 0E (0) PS MASK V-DET HD WIDTH HV POL (0) HV DET HV OUT 00000000 0F H DMY V DMY (0) 10 11 12 HV FREQ2 H COUNT MAX (0) SIG DET N (0)TEST1 (0) 00000000 H COUNT MIN 00000000 SIG RESET N SIG RESET SIG SW SIG DET IMPE 00000000 SIG DET LVL 00000000 13 (00000000)TEST2 00000000 14 (00000000)TEST3 00000000 NOTE:To activate GCA V timing without V separation (input V sync signal to SYNC2 IN(11 pin)), set D7=1(SA 12H,13H 14H). After changing GCA SW, GCA gain, set D7=0(SA:12H,13H, 14H). Read Mode 0 Slave address: DFH D7 D6 D5 D4 D3 POR H FM2 V FM2 H IN V IN 1 2 H FORMAT ＊ 3 ＊ D1 D0 V-SYNC-W HD-POL VD-POL ∗ V FORMAT SIG DET DC4（29Pin） 4 D2 HV-OUT FORMAT DC3(27Pin) DC8(51Pin) DC7(49Pin) 5 ∗ ∗ ∗ ∗ 6 S6(62Pin) SC2in S5(56Pin) Cb3in S4(50Pin) Cb2in S3(48Pin) Cr2in DC2(14PIN) DC1(1PIN) DC6(34Pin) DC5(31Pin) DC10(55Pin) DC9(53Pin) S2(44Pin) SC1in 7 H FREQ DET 8 V FREQ DET S1(38Pin) Cb1in ∗ ∗ ∗: Undefined 11 2006-11-13 TB1328FG Bus Control Functions Write Mode Register Name Function Switches the frequency of bandwidth limit filters for Cb/Cr fc HALF The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y. 0: OFF (same for 3 outputs) Preset Value OFF (0) 1: ON (1/2 fc for Cb/Cr) Selects the output form Y/Cb/Cr OUT (pins 2,4,6). YCbCrOUT (Y OUT, Cb OUT, Cr OUT)= 0000: Mute (mute, mute, mute) 0001: SY1 (pin 42), SC1 (pin 44), mute 0010: SY2 (pin 60), SC2 (pin 62), mute 0011~0101: Not available 0110: CVBS3 (pin 46), mute, mute 0111: Y1 (pin 40), Cb1 (pin 38), Cr1 (pin 36) (mute, when CbCr PIN1=1) 1000: Y2 (pin 52), Cb2 (pin 50), Cr2 (pin 48) (mute, when CbCr PIN2=1) 1001: Y3 (pin 58), Cb3 (pin 56), Cr3 (pin 54) (mute, when CbCr PIN3=1) 1010: Not available 1011: Cr1(as CVBS) (pin 36), mute, mute(when CbCr PIN1=1) 1100: Cr3(as CVBS) (pin 54), mute, mute(when CbCr PIN3=1) 1101 ~ 1111: Not available Mute (0000) Refer also to Function Descriptions. FILPASS Switches the bandwidth limit filter. OFF 0: OFF (filters active) YC MIX 1: ON (bypass) Mixes Y with C for MONITOR OUT (pin64). 0: OFF (for CVBS) 1: MIX (Y+C) (0) OFF (0) Selects the output form MONITOR OUT (pin 64) . When YC MIX=1, a mixed signal is outputted. MONITOR OUT 0000: Mute 0001: SY1 (pin 42) (+SC1 (pin 44)) 0010: SY2 (pin 60) (+SC2 (pin 62)) 0011~0101: Not available 0110: CVBS3 (pin 46) (+Cr2 (pin 48), when CbCr PIN2=1) 0111: Y1 (pin 40) (+Cb1 (pin 38)) 1000: Y2 (pin 52) (+Cb2 (pin50)) 1001: Y3 (pin 58) (+Cb3 (pin 56)) 1010: Not available 1011: Cr1((CVBS) (pin 36),when CbCr PIN1=1 ) 1100: Cr3((CVBS) (pin 54) when CbCr PIN3=1 ) 1101 ~ 1111: Not available Mute (0000) Refer also to Function Descriptions. Switches the f0 of bandwidth limit filter for YCbCr(RGB) LOW f0 SW 0: LOW BANDWIDTH 1: HIGH Switches the f0 of bandwidth limit filter for YCbCr(RGB) and CVBS output form Y/Cb/Cr OUT (pins 2,4,6) 0000000: MIN (low) 1111111: MAX (high) GCA V timing 0: GCA V timing OFF 1:GCA V timing ON GCA SW 0: GCA OFF 1:GCA ON GCA Gain 000000: Gain MAX (high) (0) MIN （0000000） 0: GCA V timing OFF 0: GCA OFF 111111: Gain MIN (low) Max (000000) NOTE: If GCA SW is GCA OFF, set GCA Gain to minimum. After setting D7=1(SA:04H,12H,13H,14H) and GCA Gain to MIN(3FH), set D7=0(SA:04H,12H,13H,14H). 12 2006-11-13 TB1328FG Register Name Function Preset Value Switches output gain. Gain of CVBS / Y / G OUT outputs (pins 2) is controlled. CVBS / Y GAIN 00: 0dB 10: +3dB 01: -3dB 11: Not available Remark: GAIN = 01 (-3dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. Switches output gain. Gain of CbCr(B/R) OUT outputs (pins 4,6) is controlled. CbCr GAIN 00: 0dB 10: +3dB 01: -3dB 0dB 11: Not available (00) Remark: GAIN = 01 (-3dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. Changes CbCr1-IN pins function. 0: Component Cb/Cr input (pin 40: Y/G, pin 38: Cb/B, pin 36: Cr/R ) CbCr PIN1 1: Separated C and CVBS input (pin 40: Y, pin 38: C, pin 36: CVBS) Cb/Cr input (0) * If ”1: Separated C and CVBS input” is selected for CbCr PIN1, then CLAMP1 mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS)” Changes CbCr2-IN pins function. CbCr PIN2 0: Component Cb/Cr input (pin 52: Y/G, pin 50: Cb/B, pin 48: Cr/R, pin 46: CVBS) Cb/Cr input (0) 1: Separated C input (pin 52: Y, pin 50: C, pin 48:C,pin 46: Y) Changes CbCr3-IN pins function. 0: Component Cb/Cr input (pin 58: Y/G, pin 56: Cb/B, pin 54: Cr/R) CbCr PIN3 1: Separated C and CVBS input t (pin 58: Y, pin 56: C, pin 54: CVBS) Cb/Cr input (0) * If ”1: Separated C and CVBS input” is selected for CbCr PIN3, then CLAMP3 mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS)” Switches Y1 (3)/G1(G3) & Cr1(3)/R1(3) clamping mode. The clamping mode for pin 40(58) & pin 36(54) is set. CLAMP1(3) 0: SYNC TIP CLAMP (for Y/G with sync) & BIAS (Cr/R ) 1: BIAS (for RGB without sync) * If ”1: Separated C and CVBS input” is selected for CbCr PIN1(3), then CLAMP mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS/Y)” SYNC TIP (0) Switches Y2 clamping mode. CLAMP2 SYNC TIP The clamping mode for pin 52 is set. 0: SYNC TIP CLAMP (for Y/G with sync) 1: BIAS (for RGB without sync) TEST0 TEST modes for shipping test. Set all to zero. (0) all 0 Switches audio outputs from AL/AR1 (2)-OUT (pins 3/5 (13/15)). AU1(2) OUT 0000: MUTE 0010: AL/AR2 (pins32/30) 0100: AL/AR4 (pins39/37) 0110: AL/AR6 (pins 47/45) 1000: AL/AR8 (pins63/61) 0001: AL/AR1 (pins28/26) 0011: AL/AR3 (pins35/33) 0101: AL/AR5 (pins43/41) 0111: AL/AR7 (pins59/57) 1001～1111: Not available 13 AL/AR1 (0001) 2006-11-13 TB1328FG Register Name Function Preset Value Switches the separation level. The H/V sync separation level to SYNC1(2)-IN (pin 25 (11)) is switched. HV-SEP1(2) 00: LOW 11: HIGH LOW (00) Remark: The separation level is changed according to the ratio of negative sync width per 1H period. Turns on the LPF for the sync-tip clamp. SYNC LPF1(2) SYNC LPF1(2) for SYNC1(2)-IN pin changes the speed of sync-tip clamp response. Turn this function on for no input detection. 0: OFF OFF (0) 1: ON Automatic sync processing mode. A-SYNC Sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. Format detection is performed for SYNC2-IN or HD/VD-IN signal selected by HV DET. The result of detection is returned to H,V FORMAT, H,V FM2 and FORMAT. HV FREQ setting is invalid when this mode is active. OFF (0) 0: OFF (Manual switching mode by HV FREQ setting) 1: ON Remark: SYNC1-IN (pin25) is not available when A-SYNC=1(ON). In this case, format detection and H/V separation are applied to SYNC2-IN (pin11). Turns on the LPF for the sync input pin (pin25; SYNC1-IN). SIG LPF When no input detection for weak strength signals is required, turn this function on to reduce noise on the input. Turn this function off for detections such as H, V FORMAT and H, V FREQ DET. 0: OFF 0: ON (Normal) (0) 1: ON Switches the mask mode for pseudo-sync. PS MASK OFF 1: OFF (for “Sync on G”) ON (0) (1)OFF mode is used for “Sync on G” input. 14 2006-11-13 TB1328FG Register Name V-DET Function Switches the V format detection mode. 0: 50/60Hz only Preset Value 50/60 only 1: Full detection (0) Switches the width of HD-OUT (pin 8) from SYNC2-IN (pin11). 0: WIDE HD WIDTH 1: NARROW Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur. Switches the polarity of HD/VD output. HV-POL WIDE (0) Positive The polarity of HD/VD OUT (pin 8, 9) is set. (0) 0: Positive 1: Negative Selects the input for format detection. HV DET When A-SYNC=0 (Manual mode) 0: SYNC1-IN (pin 25) SYNC 1: HD/VD-IN (pins 23/22) (0) When A-SYNC=1 (Automatic mode) This function is invalid. The input is selected by HV OUT. HV OUT Switches the outputs from HD/VD-OUT (pin 8/9). 0: SYNC2-IN (pin11) 1: HD/VD-IN (pins 23/22) SYNC2-IN (0) Outputs the dummy HD when no-input. H DMY The dummy HD/VD output’s frequency depends on HV FREQ2 setting (when A-SYNC = OFF) or H,V FORMAT (when A-SYNC = ON). No input detection is based on H IN result. 0: OFF 1: ON (Dummy HD output when no-input) OFF (0) NOTE: The HD output does not synchronize with input sync when A-SYNC = OFF and when a sync is input. Outputs the dummy VD when no-input. V DMY The dummy HD/VD output’s frequency depends on HV FREQ2 setting (when A-SYNC=OFF) or H,V FORMAT (when A-SYNC=ON). No-input detection is based on V IN result. 0: OFF 1: ON (Dummy VD output when no-input) OFF (0) NOTE: The VD output does not synchronize with input sync when A-SYNC = OFF and when a sync is input. 15 2006-11-13 TB1328FG Register Name Function Preset Value Input format setting. Set the horizontal and vertical mode according to the format that is input. When A-SYNC = ON mode, this setting is invalid. HV FREQ2 H COUNT MAX 00000: 15.625 kHz, 50 Hz (625i) 00001: 15.75 kHz, 60 Hz (525i) 00010: 31.25 kHz, 50 Hz (625p) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00100: 28.125 kHz, 50 Hz (1125/50i) 00101: 33.75 kHz, 60 Hz (1125/60i) 00110: 37.5 kHz, 50 Hz (750/50p) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01000: 31.25 kHz, 50 Hz (1250i) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 ~ 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10001: 27 kHz, 24 Hz (1125/24p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10011: 33.75 kHz, 30 Hz (1125/30p) 10100: 27kHz, 48 Hz (1125/24sf) 10101 ~ 11111: Not available 1111: 62 counts (2 counts / step) Selects H-sync lower threshold count number for the no-input detection. 000: 16 counts SIG DET N (00000) Selects H-sync higher threshold count number for the no-input detection. 0000: 32 counts H COUNT MIN 15.625 kHz, 50 Hz 111: 30 counts (2 counts / step) Selects the signal detection count number for input existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts ~ 32 counts (0000) 16 counts (000) 1 count (0000) 1111: 30 counts (2 counts / step) Selects the signal detection count number for input non-existence threshold of the no-input detection. 1 count SIG RESET N 0000: 1 count 0001: 2 counts ~ (0000) 1111: 30 counts (2 counts / step) Resets the counter for no-input detection. Normal SIG RESET When 1 is sent, the counter for no-input detection is cleared. 0: Normal SIG SW Selects the input to the counter for no-input detection. 0: SYNC2-IN (pin 11) (0) 1: Reset 1: SYNC1-IN (pin 25) SYNC2-IN (0) Changes the internal impedance for no-input detection. SIG DET IMPE The time constant of LPF for no-input detection is changed by this function and the capacitor value of SYNC FILTER (pin10). 20 kΩ (00) 00: 20 kΩ 10: 10 kΩ 01: 15 kΩ 11: 6 kΩ Changes the threshold for no-input detection. SIG DET LVL TEST1,2,3 00: 0.55 V 10: 1.05 V 01: 0.80 V 11: 1.30 V TEST modes for shipping test. Set all to zero. 16 0.55 V (00) all 0 2006-11-13 TB1328FG Read Mode Register Name Function Power On Reset POR 0: Normal 1: Register preset After power on, 1 is returned at first read. 0 is returned at second and subsequent reads. Horizontal format detection 2 H FM2 0: Known 1: Unknown Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data. Vertical format detection 2 V FM2 0: Known 1: Unknown Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data. Input detection to horizontal syncs H IN 0: No-input V IN 1: Signal detected Input detection to vertical syncs 0: No-input 1: Signal detected V-SYNC width detection 0: Wide V-SYNC-W 1: Narrow Detects V-SYNC width for detecting 1250i format. Under A-SYNC=1(ON), V-SYNC-W shows 1 when VD width from VD-IN pin is narrower than approx. 69 us, or when V-SYNC width from SYNC-IN pin is narrower than approx. 54 us. Polarity detection to HD-IN HD-POL 0: Positive 1: Negative Detects the width from the HD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx. 13.5 us, HD-POL shows 1. Polarity detection to VD-IN VD-POL 0: Positive 1: Negative Detects the width from the VD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx. 4.5 ms, VD-POL shows 1. Horizontal format detection H FORMAT 0000: 15.625/15.75 kHz 0001: 28.125 kHz 0010: 31.25/31.5 kHz 0100: 37.5/37.9 kHz 0101: 45/48 kHz 0110: 56.25 kHz 1000: 75 kHz 1001 ~ 1111: Undefined 0011: 33.75 kHz 0111: 64/67.5 kHz Detects the horizontal format (horizontal frequency). Vertical format detection V FORMAT 000: 50 Hz 100: 25 Hz 001: 60 Hz 101: 24 Hz 010: 48 Hz 110 ~ 111: Undefined 011: 30 Hz Detects the vertical format (horizontal frequency) according to V FREQ DET data. No-input detection. SIG DET 0: No-input 1: A signal detected The signal to the no-input detection circuit is selected by SIG SW. Refer to relevant functions, H COUNT MAX, H COUNT MIN, SIG DET N, SIG RESET N, SIG RESET, SIG DET IMPE and SIG DET LVL. Format detection result. H and V dummy output frequencies depend on this result. HV-OUT FORMAT 00000: 15.625 kHz, 50 Hz (625i) 00010: 31.25 kHz, 50 Hz (625p) 00100: 28.125 kHz, 50 Hz (1125/50i) 00110: 37.5 kHz, 50 Hz (750/50p) 01000: 31.25 kHz, 50 Hz (1250i) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 ~ 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10100: 27 kHz, 48 Hz (1125/24sf) 10101 ~ 11111: Not available 17 00001: 15.75 kHz, 60 Hz (525i) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00101: 33.75 kHz, 60 Hz (1125/60i) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 10001: 27 kHz, 24 Hz (1125/24p) 10011: 33.75 kHz, 30 Hz (1125/30p) 2006-11-13 TB1328FG Register Name Function DC voltage detection for D-pin or S-pin 00: Low (0 V) 01: Mid (2.2 V) 10: Undefined 11: High (5 V) Remark1; See below for the relationship between this function number and the pin number. DC1 - pin 1, DC2 - pin 14, DC3 - pin 27, DC4 - pin 29, DC5 - pin 31, DC6 - pin 34, DC7 - pin 49, DC8 - pin 51, DC9 - pin 53, DC10 - pin 55, DC1 ~ 10 Remark2; for D-pin SW LINE: 00: Connected LINE1: 00: 525 (480) LINE2: 00: interlace LINE3: 00: 4:3 01: ---01: 750 (720) 01: ---01: 4:3 letter box 10: ---10: ---10: ---10: ---- 11: Not-connected 11: 1125 (1080) 11: progressive 11: 16:9 Remark3; for S-pin 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 Detects if S-pin is connected or not. 0: Low (not-connected) S1 ~ 6 1: Open (connected) Remark1; An external circuit is necessary to use this function. Refer to Function description. Remark2; See below for the relationship between this function number and the pin number. S1 - pin 38, S2 - pin 44, S3 - pin 48, S4 - pin 50, S5 - pin 56, S6 - pin 62 Counts the vertical frequency of an input selected by SYNC SW. When V-DET=0; 00000000: over 3.5 kHz 01001111: 44 Hz or less 01010000～11111111: No input V FREQ DET When V-DET=1; 00000000: over 3.5 kHz 10011001: 23 Hz or less 10011010～11111111: No input To calculate the vertical frequency (Y) ; Convert data read from V FREQ DET into decimal value and call it X. Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4) [Hz] The error range of X is −1 to +1. Counts the horizontal frequency of an input selected by SYNC SW. H FREQ DET When for SYNC-IN; 00000001: No input 11111111: over 85kHz When for HD/VD-IN; 00000000: No input 11111111: over 85kHz To calculate the horizontal frequency (Y) ; Convert data read from H FREQ DET into decimal value and call it X. Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X) [Hz] The error range of X is −1 to +1. Note 1: In determining the decision algorithms (detection range, detection times and so on) for H/V frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal 2 conditions and I CBUS data transmission in the course of prototype TV set evaluation. Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection result will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a judgment will be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time. 18 2006-11-13 TB1328FG Function Descriptions Output selections Outputs are switched by I2CBUS registers, as in the following tables. YCbCr1 OUT Register settings Outputs YCbCr OUT Reserved CbCr PIN3 CbCr PIN2 CbCr PIN1 CVBS/Y/G OUT (pin 2) Available input Cb/B OUT (pin 4) Cr/R OUT (pin 6) CVBS YC 0000 ∗ ∗ ∗ ∗ Mute Mute Mute 0001 ∗ ∗ ∗ ∗ SY1 (pin 42) SC1 (pin 44) Mute y y 0010 ∗ ∗ ∗ ∗ SY2 (pin 60) SC2 (pin 62) Mute y y 0011 ∗ ∗ ∗ ∗ 0100 ∗ ∗ ∗ ∗ 0101 ∗ ∗ ∗ ∗ ∗ ∗ 0 ∗ CVBS3 (pin46) Mute Mute y ∗ ∗ 1 ∗ CVBS3 (pin 46) Cr2 (pin 48) Mute y y ∗ ∗ ∗ 0 Y1 (pin 40) Cb1 (pin 38) Cr1 (pin 36) y y ∗ ∗ ∗ 1 Y1 (pin 40) Cb1 (pin 38) Mute y y 0110 0111 1000 Not available ∗ ∗ 0 ∗ Y2 (pin 52) Cb2 (pin 50) Cr2 (pin 48) y y ∗ ∗ 1 ∗ Y2 (pin 52 Cb2 (pin 50) Mute y y ∗ 0 ∗ ∗ Y3 (pin 58) Cb3 (pin 56) Cr3 (pin 54) y y ∗ 1 ∗ ∗ Y3 (pin 58) Cb3 (pin 56) Mute y y 1010 ∗ ∗ ∗ ∗ 1011 ∗ ∗ ∗ ∗ Cr1 (pin 36) Mute Mute y Cr3 (pin 54) Mute Mute y 1001 1100 ∗ ∗ ∗ ∗ 1101~1111 ∗ ∗ ∗ ∗ YCbCr RGB y y y Not available Not available ∗: Don’t care MONITOR OUT Register settings MON OUT 0000 0001 0010 Outputs YC MIX Reserved CbCr PIN3 CbCr PIN2 CbCr PIN1 ∗ 0 1 0 1 ∗ ∗ ∗ ∗ ∗ ∗ MONITOR OUT (pin 64) ∗ Mute ∗ SY1 (pin 42) ∗ ∗ ∗ ∗ ∗ SY2 (pin 60) ∗ ∗ ∗ 0100 ∗ ∗ ∗ ∗ ∗ 0101 ∗ ∗ ∗ ∗ ＊ ∗ ∗ ∗ 0 ∗ CVBS3 (pin46) 0110 0 ∗ CVBS3 (pin 46) 0111 0 1 1000 0 1 1001 0 1 ∗ ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Not available y y y y y y y y y CVBS3 (pin 46) + Cr2 (pin 48) Y1 (pin 40) y y Y1 (pin 40) + Cb1 (pin38) Y2 (pin 52) y y Y2 (pin 52) + Cb2 (pin 50) Y3 (pin 58) YC y SY2 (pin 60) + SC2 (pin 62) ∗ ∗ CVBS SY1 (pin 42) + SC1 (pin 44) 0011 1 Available input y y Y3 (pin 58) + Cb3 (pin 56) 1010 ∗ ∗ ∗ ∗ ∗ Not available y 1011 ∗ ∗ ∗ ∗ ∗ Cr1 (pin 36) y 1100 ∗ ∗ ∗ ∗ ∗ Cr3(pin 54) y 1101~1111 ∗ ∗ ∗ ∗ ∗ Not available ∗: Don’t care 19 2006-11-13 TB1328FG Vertical sync separation for 1250i/50 When HV FREQ2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special circuit. The phase of the VD-out (pin 9) depends on the H-SYNC timing shown in the figure below. There is no VD-out when there is no H-SYNC input. In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H, V FREQ DET) to detect the 1250i/50. NOTE: The VD-OUT’s tailing edge has a jitter. Use the leading edge only. INPUT (First field ) V-SYNC VD OUT (Pin 9) Leading edge Trailing edge with a jitter INPUT (Second field ) V-SYNC VD OUT (Pin 9) Leading edge Trailing edge with a jitter HD width HD-OUT width is selectable by HD WIDTH as below. HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur. 1125/60p signal SYNC-IN (Y-IN) HD-OUT (HD WIDTH=1) 0.7us (typ) HD-OUT (HD WIDTH=0) 1.7us (typ) HD/VD input amplitude When a 5.6 kΩ is added before the input pin as in the following figure, 5.0 Vp-p pulse input is allowed. However, the acceptable minimum amplitude then becomes 2.0 Vp-p. 2.0 to 5.0 Vp-p Input 1.0 to 2.0 Vp-p Input or 100Ω pin 22,23 HD/VD-IN 1uF/4.7uF 1uF/4.7uF or Normal application pin 22,23 HD/VD-IN 5.6kΩ For large input application 20 2006-11-13 TB1328FG Automatic sync processing mode (A-SYNC) Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H,V FREQ DET. Also, the detected format is returned to H, V FORMAT and H, V FM2 when the H/V frequencies are in internally-defined ranges. Input detection results, which indicate whether there is an input or not, for H, V-SYNC or HD,VD, are returned to H,V IN. HV-OUT FORMAT indicates the active mode. In automatic sync processing mode (when A-SYNC = ON), this device operates as indicated in the following table according to these READ data. SYNC1-IN pin is also not used for detecting format. INPUT CONDITION Standard format HV-OUT FORMAT, H, V FORMAT status H, V FM2 status H, V IN status HD, VD outputs Known Signal The separated sync as input The format as input The status indicates not The separated sync as the current condition Unknown Signal input but the last detected format. Dummy HD and VD, of Known: The status indicates not which the frequency the current condition The status indicates not No input No input depends on the HV-OUT but the last detected the current condition but FORMAT status the last detected format. format. NOTE 3: Dummy HD and VD may become unstable while the mode is changing form one format to another. Non-standard format Manual sync processing mode (A-SYNC=OFF) In this mode, SYNC1-IN pin is used only for detecting the input format and SYNC2-IN pin is used only for separating H and V syncs for HD and VD outputs. It is possible to detect some input’s formats by means of time-sharing while separating syncs to another input. The following is an example of how to detect H/V frequency when A-SYNC = OFF. 1. Input the signal from Yvi-OUT pin into SYNC1-IN pin. 2. Read data such as H, V FREQ DET and H, V FORMAT. 3. Detect the H/V frequency by microprocessor or similar means, depending on the data obtained. 4. Input the detected signal into SYNC2-IN pin and set HV FREQ2 and so on for SYNC2-IN pin to the detected mode. 5. Continue to monitor the obtained data for SYNC1-IN pin such as H, V FREQ DET and H, V FORMAT. When any alterations are recognized, re-set HV FREQ2 and so on for SYNC2-IN pin. Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined taking into account the above-mentioned errors in measuring H/V frequencies and other factors such as signal conditions and I2CBUS data transmission in the course of prototype TV set evaluation. I2CBUS I2CBUS Note also, in A-SYNC = OFF and H, V DMY = ON mode, dummy HD and VD are output according to HV FREQ2 setting when there is no input. Fig. The signal route when A-SYNC = ON Fig. The signal route when A-SYNC = OFF 21 2006-11-13 TB1328FG Sync separation level The sync separation level is changed according to the ratio of H-sync width to one line. Typical sync separation levels for each format are as follows. HV-SEP data 625/50i 525/60i 625/50p 525/60p 1125/50i 1125/60i 750/50p 750/60p 1250/50i 1125/50p 1125/60p 525/30p 1125/24p 1125/25p 1125/30p 1125/24sf VGA/60 SVGA/60 XGA/60 SXGA/60 00 01 10 11 18 18 19 19 27 25 25 24 22 28 27 18 27 27 26 28 20 20 20 22 26 26 27 27 34 33 32 31 30 36 34 26 34 34 32 34 26 27 27 29 31 31 32 32 40 38 38 36 36 41 39 31 40 40 38 40 32 33 33 34 43 43 44 44 52 50 50 49 48 52 52 43 52 52 50 52 43 44 44 45 Unit [%] ; where 286 mVp-p sync for 525/60i and 300 mVp-p sync for others Format detection and sync separation performance are affected by the separation level set by HV-SEP setting and the value of the connected coupling capacitor. Careful evaluation is required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag and APL (Average Picture Level) fluctuations. For “Sync on G” signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period. 22 2006-11-13 TB1328FG No input detection This function detects if there is an input or not. It is useful for detecting no-input of 525i or 625i, including signals of weakened strength. (1)0 (no-input) Æ 1 (detected) When Nmin ≦ N1≦ Nmax, and when N2 ≧ Ndet, SIG DET returns 1. Where, Nmin: the number set by H COUNT MIN Nmax: the number set by H COUNT MAX Ndet: the number set by SIG DET N N1: the number of H-sync into the counter during an internal window (approx. 2ms) N2: the number of condition where “Nmin ≦ N1 ≦ Nmax” is detected (2) 1 (detected) Æ 0 (no-input) When N1 ≦ Nmin, N1 ≧ Nmax, and when N3 ≧ Nreset, SIG DET returns 0. Where, Nreset: the number set by SIG RESET N N3: the number of condition where “N1 ≦ Nmin and N1 ≧ Nmax” is detected Fig. block diagram of no-input detection Determine the use of no-input detection following sufficient evaluations using a prototype TV set. 23 2006-11-13 TB1328FG S-pin insertion detection C-IN pins detect DC level to recognize if S-pin is inserted or not. C-IN pin DC DET "S1～6" Chroma Insertion No-insertion S-pin connector Fig. an application of S-pin insertion detection V Freq detection Counts the vertical frequency of an input selected by SYNC SW. When V-DET=0; 00000000: over 3.5 kHz 01001111: 44 Hz or less 01010000～11111111: No input When V-DET=1; 00000000: over 3.5 kHz 10011001: 23 Hz or less 10011010～11111111: No input To calculate the vertical frequency (Y) ; Convert data read from V FREQ DET into decimal value and call it X. Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4) [Hz] The error range of X is −1 to +1. ＢＩＮ 0 1～110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 ＤＥＣ ＨＥＸ 0 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Freqｅｎｃｙ[Hz]Freqｅｎｃｙ[Hz] V-det=0 V-det=1 Over 3500 Over 3500 ～ 63.6 63.6 62.4 62.4 61.3 61.3 60.3 60.3 59.2 59.2 58.3 58.3 57.3 57.3 56.4 56.4 55.5 55.5 54.6 54.6 53.8 53.8 53.0 53.0 52.2 52.2 51.4 51.4 50.7 50.7 49.9 49.9 49.2 49.2 48.6 48.6 47.9 47.9 47.2 47.2 46.6 46.6 46.0 46.0 45.4 45.4 44.8 44.8 44Hz or less 44.2 24 ＢＩＮ 1010000～1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011～10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001～10011000 10011001 10011010～11111111 ＤＥＣ ＨＥＸ Freqｅｎｃｙ[Hz]Freqｅｎｃｙ[Hz] V-det=0 V-det=1 ～ No Input ～ 111 6F No Input 31.5 112 70 No Input 31.2 113 71 No Input 30.9 114 72 No Input 30.7 115 73 No Input 30.4 116 74 No Input 30.1 117 75 No Input 29.9 118 76 No Input 29.6 119 77 No Input 29.4 120 78 No Input 29.1 121 79 No Input 28.9 122 7A No Input 28.7 ～ No Input ～ 135 87 No Input 25.9 136 88 No Input 25.7 137 89 No Input 25.5 138 8A No Input 25.3 139 8B No Input 25.1 140 8C No Input 25.0 141 8D No Input 24.8 142 8E No Input 24.6 143 8F No Input 24.4 144 90 No Input 24.3 ～ No Input ～ 153 99 No Input 23Hz or less 154～255 9A～FF No Input No Input 2006-11-13 TB1328FG H Freq detection Counts the horizontal frequency of an input selected by SYNC SW. When for SYNC-IN; 00000001: No input 11111111: over 85kHz When for HD/VD-IN; 00000000: No input 11111111: over 85kHz To calculate the horizontal frequency (Y) ; Convert data read from H FREQ DET into decimal value and call it X. Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X) [Hz] The error range of X is −1 to +1. ＢＩＮ 0 1 10～101100 101101 101110 101111 110000～1010011 1010100 1010101 1010110 1010111～1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110～1101110 1101111 1110000 1110001 1110010 1110011 1110100～10000100 ＤＥＣ ＨＥＸ 0 1 0 1 45 46 47 2D 2E 2F 84 85 86 54 55 56 93 94 95 96 97 98 99 100 101 5D 5E 5F 60 61 62 63 64 65 111 112 113 114 115 6F 70 71 72 73 Freqｅｎｃｙ[kHz] Freqｅｎｃｙ[kHz] Sync IN HD/VD IN No Input No Input 0.33 ～ 15.00 15.00 15.33 15.33 15.67 15.67 ～ 28.00 28.00 28.33 28.33 28.67 28.67 ～ 31.00 31.00 31.33 31.33 31.67 31.67 32.00 32.00 32.33 32.33 32.67 32.67 33.00 33.00 33.33 33.33 33.67 33.67 ～ 37.00 37.00 37.33 37.33 37.67 37.67 38.00 38.00 38.33 38.33 ～ 25 ＢＩＮ 10000101 10000110 10000111 10001000 10001001 10001010～10100101 10100110 10100111 10101000 10101001 10101010 10101011～10111101 10111110 10111111 11000000 11000001 11000010 110000１1～11011110 11011111 11100000 11100001 11100010 11100011 11100100～11111110 11111111 ＤＥＣ ＨＥＸ 133 134 135 136 137 85 86 87 88 89 166 167 168 169 170 A6 A7 A8 A9 AA 190 191 192 193 194 BE BF C0 C1 C2 223 224 225 226 227 DF E0 E1 E2 E3 255 FF Freqｅｎｃｙ[kHz] Freqｅｎｃｙ[kHz] Sync IN HD/VD IN 44.33 44.33 44.67 44.67 45.00 45.00 45.33 45.33 45.67 45.67 ～ 55.33 55.33 55.67 55.67 56.00 56.00 56.33 56.33 56.67 56.67 ～ 63.33 63.33 63.67 63.67 64.00 64.00 64.33 64.33 64.67 64.67 ～ 74.33 74.33 74.67 74.67 75.00 75.00 75.33 75.33 75.67 75.67 ～ Over 85 Over 85 2006-11-13 TB1328FG GCA gain GCA gain is controlled by Y/G/CVBS OUT gain, and controls only CVBS Input signal. GCA gain is controlled by a 6bit I2C-Bus, and this LSI does not have an Input level detection circuit.. In order to perform GCA control, it is necessary to input CVBS/Y/G OUT to SYNC2 IN. By doing so, V latch starts with a Vsepa signal and GCA control becomes possible. In this case, the BUS must be set as CVBS/Y GAIN=1 (-3dB). 0.44Vp-p -3dB CVBS input GCA CVBS output 100IRE 768LSB 0.7Vp-p 256LSB 1.40Vp-p The following figure shows typical GCA gain characteristics. 5 0.8 0.7 3 Output Level（Vp-p) GAIN Typ.（ｄB） 1 0.5 -1 0.4 0.3 Typ. Gain Output Level 0.6 -3 0.2 -5 0.1 0 -7 0.4 0.6 0.8 1 Input Level 1.2 1.4 1.6 Min Typ Max Input Level（Vp-p) 0.44 0.6605 0.881 0.9998 1.1015 1.3221 1.4 0.7 0.7 0.7 0.7 0.7 0.7 0.7 Output Level（Vp-p GAIN Typ.（ｄB） 4.0329 0.5043 -1.998 -3.096 -3.938 -5.523 -6.0206 Bin 000000 001101 011010 100001 100111 110100 111111 Dec 0 13 26 33 39 52 63 Hex 00 0D 1A 21 27 34 3F 26 2006-11-13 TB1328FG 10 Gain [dB] 0 -10 -20 -30 f0 SW = low, BANDWIDTH = min, fc HALF = on f0 SW = low, BANDWIDTH = min -40 f0 SW = high, BANDWIDTH = min f0 SW = high, BANDWIDTH = max -50 0.1 1 10 100 Frequency [MHz] Fig. Typical pre-filter frequency characteristics Cutoff frequency (-3 dB point) [MHz] 50 fo fo fo fo 40 SW SW SW SW = = = = high low high, fc HALF = on low, fc HALF = on 30 20 10 0 0 20 40 60 80 100 120 127 BANDWIDTH data Fig. Typical cutoff frequency characteristics of pre-filter (-3 dB point) 27 2006-11-13 TB1328FG 250 fo fo fo fo Delay time [ns] 200 SW SW SW SW = = = = high low high, fc HALF = on low, fc HALF = on 150 100 50 0 0 20 40 60 80 100 120 127 BANDWIDTH data Fig. Typical delay-time characteristics of pre-filter (group delay @ 1MHz) Recommended crystal oscillator When a connected crystal oscillator is used for the XO, the following oscillation specifications are required. Oscillation frequency (fundamental): 3.579545MHz (for NTSC decoding) Frequency tolerance: +/- 50ppm External CW input into crystal oscillator pin Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 28 through a capacitor as below. The required specs on the CW are as follows. Input frequency (fundamental): 3.579545MHz +/- 50ppm Input amplitude: 1.0Vp-p +/- 0.5Vp-p CW 20 XTAL 220pF 28 2006-11-13 TB1328FG How to deal with unused pins Unused pins should be dealt with as below. Pins not mentioned below should be connected properly. Pin No. Pin Name Procedure Pin No. 38 Pin Name Procedure 1 DC1(S2) Procedure 2 Cb1/B1 IN Procedure 1 2 CVBS/Y/G OUT Procedure 3 3 AL1 OUT 39 AL4 IN Procedure 1 Procedure 3 40 Y1/G1 IN 4 Cb/B OUT Procedure 1 Procedure 3 41 AR5 IN Procedure 1 5 AR1 OUT 6 Cr/R OUT Procedure 3 42 SY1 IN Procedure 1 Procedure 3 43 AL5 IN 8 HD OUT Procedure 1 Procedure 3 44 SC1 IN Procedure 1 9 VD OUT Procedure 3 45 AR6 IN Procedure 1 10 SYNC FILTER Procedure 3 46 CVBS3 IN Procedure 1 11 SYNC2 IN Procedure 1 47 AL6 IN Procedure 1 13 AL2 OUT Procedure 3 48 Cr2/R2 IN Procedure 1 14 DC2(S1) Procedure 2 49 DC7(SW LINE2) Procedure 2 15 AR2 OUT Procedure 3 50 Cb2/B2 IN Procedure 1 22 VD IN Procedure 4 51 DC8(LINE3-2) Procedure 2 23 HD IN Procedure 4 52 Y2/G2 IN Procedure 1 25 SYNC1 IN Procedure 1 53 DC9(LINE2-2) Procedure 2 26 AR1 IN Procedure 1 54 Cr3/R3 IN Procedure 1 27 DC3(SW LINE1) Procedure 2 55 DC10(LINE1-2) Procedure 2 28 AL1 IN Procedure 1 56 Cb3/B3 IN Procedure 1 29 DC4(LINE3-1) Procedure 2 57 AR7 IN Procedure 1 30 AR2 IN Procedure 1 58 Y3/G3 IN Procedure 1 31 DC5(LINE2-1) Procedure 2 59 AL7 IN Procedure 1 32 AL2 IN Procedure 1 60 SY2 IN Procedure 1 33 AR3 IN Procedure 1 61 AR8 IN Procedure 1 34 DC6(LINE1-1) Procedure 2 62 SC2 IN Procedure 1 35 AL3 IN Procedure 1 63 AL8 IN Procedure 1 36 Cr1/R1 IN Procedure 1 64 MONITOR OUT Procedure 3 37 AR4 IN Procedure 1 − − − Procedure 1: Connect a 0.01 µF capacitor between this pin and GND. Procedure 2: Connect to GND. Procedure 3: Leave open. Procedure 4: Connect a 10 kΩ resistor between this pin and GND. 29 2006-11-13 TB1328FG 2 How To Start I CBUS The following describes how to send bus data after power on. Use software to handle the procedure. 1. Turn power on. 2. Transmit all write data. 2 How To Transmit/Receive Via I CBUS Slave Address: DEH / DFH A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 1 1 0/1 Start and Stop Conditions SDA SCL S P Start condition Stop condition Bit Transmission SDA SCL SDA must not be changed SDA may be changed Acknowledgement SDA from transmitter High impedance at bit 9 SDA from receiver Low impedance at bit 9 only SCL from master 1 8 9 S Clock pulse for acknowledgement 30 2006-11-13 TB1328FG Data Transmit Format 1 S Slave address 7-bit 0 A MSB S: Start condition Sub address 8-bit A Transmit data 8-bit A P MSB MSB A: Acknowledgement P: End condition Data Transmit Format 2 S Slave address 0 A Sub address ･･････ A Transmit data 1 Sub address A A ･･････ Transmit data n A P Data Receive Format S Slave address 7-bit 1 A Receive data 1 8-bit ･････････ A P MSB MSB MSB Receive data n To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The slave receiver changes to a transmitter. The end condition is always created by the master. Optional Data Transmit Format (Automatic Increment Mode) S Slave address 7-bit 0 A 1 MSB Sub address 7-bit MSB A Transmit data 1 8-bit MSB ････ Transmit data n 8-bit A P MSB In this way, sub addresses are automatically incremented from the specified sub address and data are set. I2CBUS Conditions Parameter Symbol Min. Typ. Max. Unit V Low level input voltage VIL 0 − 1.1 High level input voltage VIH 2.4 − V/S-Vcc V Hysteresis of Schmitt trigger inputs Vhys − 0.7 − V Low level output voltage at 3 mA sink current VOL1 0 − 0.4 V Ii -10 − 10 µA Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Ci − − 10 pF fSCL 0 − 400 kHz tHD;STA 0.6 − − µs tLOW 1.3 − − µs Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock tHIGH 0.6 − − µs Set-up time for a repeated START condition tSU;STA 0.6 − − µs Data hold time tHD;DAT 0 − − ns Data set-up time tSU;DAT 100 − − ns Set-up time for STOP condition tSU;STO 0.6 − − µs tBUF 1.3 − − µs High period of SCL clock Bus free time between a STOP and START condition NOTE: These parameters are not tested during production and are provided only as information to assist the design of applications. 31 2006-11-13 TB1328FG Absolute Maximum Ratings (Ta = 25°C) Characteristics Supply voltage Symbol Rating 9V Vcc VCCmax9 12.0 5V Vcc VCCmax5 6.0 3.3V Vcc Unit V VCCmax3 6.0 Input pin voltage Vin GND − 0.3 ~ Vcc + 0.3 V Y or Sync input amplitude (pin 22,23,25,36,38,40,42,46,48,50,52,54,56,58,60) Yin 2.0 Vp-p PD(Note 4) 1388 mW Power dissipation reduction rate 1/θja 11.1 mW/°C Operating temperature Topr −20 ~ 75 °C Storage temperature Tstg −55 ~ 150 °C Power dissipation Note 4: Refer to the figure below. However, these conditions apply only to the case where the device is mounted on a board (50 x 50 mm). Mount the device on a board which is larger than this. Power consumption reduction ratio PD (mW) 1388 833 0 0 25 75 Ambient temperature 150 Ta (°C) Figure PD - Ta Curve Note 5: Pins of this product are sensitive to electrostatic discharge. When handling this product, protect the environment to avoid electrostatic discharge. Note 6: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product or equipment. The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, operation when these ratings are exceeded may cause break down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each maximum rating will never be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this document. 32 2006-11-13 TB1328FG Operating conditions Characteristic Description Supply voltage (VCC) Min. Typ. Max. Pin 16 8.5 9.0 9.5 Pin 7 4.7 5.0 5.3 Pin 21; Supply power from V/S Vcc (pin 7) via a resistor. 3.1 3.3 3.5 − 1.0 − Unit V Y/G signal input amplitude Pins40,52,58; with sync CVBS/SY input amplitude Pins42,46,60,(36,54); with sync − 1.0 − Vp-p Y/G signal input frequency Pins 40,52,58 0 - 60 MHz CVBS/SY input frequency Pins 42,46,60,(36,54) 0 - 8 MHz SC (Chroma) signal input amplitude Pin 44,62(38,48,50,56) − − 2 Vp-p Cb, Cr, Pb, Pr signal input amplitude Pins36,38,48,50,54,56; 100% color bar signal − 0.7 − Vp-p Cb, Cr, Pb, Pr signal input frequency Pins 36,38,48,50,54,56 0 - 60 MHz R, G, B signal input amplitude Pins36,38,40,48,50,52,54,56,58; 100% white signal without sync − 0.7 − Vp-p 0 ⎯ 60 MHz 1.0 - 2.0 Vp-p Pins 23 for freq counter 0 ⎯ 85 kHz Pins 22 for freq counter 23 ⎯ 3500 Hz R, G, B signal input frequency Pins 36,38,40,48,50,52,54,56,58 HD, VD signal input amplitude Pins 22,23 HD input frequency VD input frequency DC detection input voltage DC1~10 S1~6 SDA input current Vp-p Pins 1,14,27,29,31,34,49,51,53,55 Pins 38,44,48,50,56,62 Pins 17 H 3.5 ⎯ V/S Vcc M 1.4 2.2 2.4 L GND ⎯ 0.6 L GND ⎯ 0.6 V − − 3 mA V Remark: Supply power to all Vcc pins (pin 7,16,21). 33 2006-11-13 TB1328FG Electrical Characteristics (Unless otherwise specified, AU VCC = 9 V, V/S VCC = 5 V, Vdd = 3.3 V, Ta = 25°C, I2CBUS data: preset values) Current Consumption (f0 SW1/2 = 1, BANDWIDTH1/2 = max) Pin Name Symbol Test Conditions Min Typ. Max AU VCC (pin16) ICCAU − 6.1 7.8 10.3 V/S VCC (pin7) ICCVS − 54.3 67.9 89.6 Vdd (pin21) ICCD Resistance to 5 V; R = 180 Ω 6.2 9.3 12.7 Unit mA Pin Voltage (test condition: no signal input) Pin No. Pin Name Symbol Test Conditions Min Typ. Max 1 DC1(S2) V1 − − 0.1 − 2 CVBS/Y1/G1 OUT V2 − 1.0 1.3 1.6 3 AL1 OUT V3 − 3.8 4.1 4.4 V4 − 1.0 1.3 1.6 V5 − 3.8 4.1 4.4 4 5 Cb1/B1 OUT AR1 OUT 6 Cr1/R1 OUT V6 − 1.0 1.3 1.6 10 SYNC FILTER V10 − 3.0 3.3 3.6 11 SYNC2 IN V11 − 1.5 1.8 2.1 13 AL2 OUT V13 − 3.8 4.1 4.4 14 DC2(S1) V14 − − 0.1 − 15 AR2 OUT V15 − 3.8 4.1 4.4 20 XTAL V20 − 3.8 4.05 4.3 22 VD IN V22 − 1.2 1.5 1.8 23 HD IN V23 − 1.2 1.5 1.8 25 SYNC1 IN V25 − 1.5 1.8 2.1 26 27 28 29 30 31 32 33 34 AR1 IN DC3(SWLINE1) AL1 IN DC4(LINE3-1) AR2 IN DC5(LINE2-1) AL2 IN AR3 IN DC6(LINE1-1) V26 − 4.2 4.4 4.6 V27 − − 0.2 − V28 − 4.2 4.4 4.6 V29 − − 0.2 − V30 − 4.2 4.4 4.6 V31 − − 0.1 − V32 − 4.2 4.4 4.6 V33 − 4.2 4.4 4.6 V34 − − 0.1 − 35 AL3 IN V35 − 4.2 4.4 4.6 36 Cr1/R1 IN V36 − 2.6 2.9 3.2 37 AR4 IN V37 − 4.2 4.4 4.6 38 Cb1/B1 IN V38 − 2.6 2.9 3.2 39 AL4 IN V39 − 4.2 4.4 4.6 40 Y1/G1 IN V40 − 2.0 2.3 2.6 41 AR5 IN V41 − 4.2 4.4 4.6 42 SY1 IN V42 − 2.0 2.3 2.6 34 Unit V 2006-11-13 TB1328FG Pin No. Pin Name Symbol Test Conditions Min Typ. Max 43 AL5 IN V43 − 4.2 4.4 4.6 44 SC1 IN V44 − 2.6 2.9 3.2 45 AR6 IN V45 − 4.2 4.4 4.6 46 CVBS3 IN V46 − 2.0 2.3 2.6 47 AL6 IN V47 − 4.2 4.4 4.6 48 Cr2/R2 IN V48 − 2.6 2.9 3.2 V49 − − 0.1 − 50 Cb2/B2 IN V50 − 2.6 2.9 3.2 51 DC8(LINE3-2) V51 − − 0.1 − 49 DC7(SWLINE2) V52 − 2.0 2.3 2.6 53 DC9(LINE2-2) V53 − − 0.1 − 54 Cr3/R3 IN V54 − 2.6 2.9 3.2 52 Y2/G2 IN V55 − − 0.1 − 56 Cb3/B3 IN V56 − 2.6 2.9 3.2 57 AR7 IN V57 − 4.2 4.4 4.6 58 Y3/G3 IN V58 − 2.0 2.3 2.6 59 AL7 IN V59 − 4.2 4.4 4.6 60 SY2 IN V60 − 2.0 2.3 2.6 61 AR8 IN V61 − 4.2 4.4 4.6 62 SC2 IN V62 − 2.6 2.9 3.2 63 AL8 IN V63 − 4.2 4.4 4.6 64 MONITOR OUT V64 − 0.9 1.2 1.5 55 DC10(LINE1-2) 35 Unit V 2006-11-13 TB1328FG Audio Block Characteristic Symbol Test Conditions Min Typ Max Unit I/O gain (AL/AR1, AL/AR2,) Gauf input = 2.8Vp-p, 1 kHz, input resistance 5.6 kΩ -1.0 0 1.0 dB I/O frequency characteristic Fau -3 dB point, NOTE A 100 ⎯ ⎯ kHz Total harmonic distortion (AL/AR1, AL/AR2,) thd input = 2.8 Vp-p 1 kHz, NOTE A ⎯ 0.02 0.05 % NOTE A, NOTE B 5.6 6.5 ⎯ Vp-p Input dynamic range Vdyau Output offset voltage Vauswof Offset on AU1(2) OUT between AU1(2) OUT = 0000 to 1000 -30 0 +30 mV Ripple rejection ratio Vrrr 100Hz and 100mVp-p ripple is added to AU Vcc, NOTE A 30 45 ⎯ dB Mute mode attenuation Gaumute input = 2.8Vp-p, 1 kHz, NOTE A 75 85 ⎯ dB Crosstalk among inputs Gaucrs input = 2.8Vp-p, 1 kHz, NOTE A 75 85 ⎯ dB S/N ratio Gausn input = 2.8Vp-p, 1 kHz, NOTE A 80 90 ⎯ dB Pins 26,28,30,32,33,35,37,39,41,43,45,47 ,57,59,61,63 65 87 109 kΩ Input impedance of input pins Imau NOTE A: These parameters are not tested during production and are provided only as information to assist the design of applications. NOTE B: Input = 1kHz, the amplitude at which the total harmonic distortion becomes 1%. Video Block Characteristic Sync-tip clamp mode Input dynamic range I/O gain Sync-tip clamp GCA mode Symbol Test Conditions Min Typ. Max 1.5 1.7 − 1.5 1.7 − 1.4 2.1 − 1.35 1.5 − YCbCr-OUT -3.5 -3.0 -2.5 FILPASS = 0/1, input = 0.2Vp-p 10 kHz, BANDWIDTH = cnt, f0 SW = 1 -0.5 0 0.5 2.5 3.0 3.5 MONITOR OUT 5.5 6.0 6.5 − − -6.5 − -3.3 − Vdsync Vdsyncgca Bias mode Vdbias Monitor out Vdmoni GAIN = -3dB G-3 GAIN = 0dB G0 GAIN = +3dB G+3 GAIN = +6dB G+6 GCA min Gmin GCA cnt Gcnt GCA max Gmax FILPASS = 0, BANDWIDTH = max, Sine wave input for Bias mode, Y with sync for others. Input = 0.2Vpp 10kHz BUS setting Y/CVBS GAIN=-3dB 4.5 − − Gycmy SY-IN to MONITOR-OUT, No input into SC-IN, YC MIX = 1 5.5 6.0 6.5 Gycmc SC-IN to MONITOR-OUT, No input into SY-IN, YC MIX = 1 5.5 6.0 6.5 YC MIX gain Unit Vp-p dB dB 36 2006-11-13 TB1328FG Characteristic I/O frequency characteristic 1-1 (YCbCr) I/O frequency characteristic 1-2 (YCbCr) I/O frequency characteristic 1-3 (YCbCr) I/O frequency characteristic 1-4 (CbCr) I/O frequency characteristic 1-5 (CbCr) YCbCr GAIN = -3dB YCbCr GAIN = 0dB Test Conditions fg-3 Fg0 FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A 80 100 − 80 100 − 80 100 − 14.0 16.5 18.0 BANDWIDTH = cnt fLcnt 9.5 10.5 11.5 BANDWIDTH = min fLmin 4.0 4.5 5.0 BANDWIDTH = max fHmax BANDWIDTH = cnt fHcnt BANDWIDTH = min fHmin BANDWIDTH = max fhfLmax BANDWIDTH = cnt fhfLcnt BANDWIDTH = min fhfLmin BANDWIDTH = max fhfHmax BANDWIDTH = cnt fhfHcnt BANDWIDTH = min fhfHmin BANDWIDTH = max FILPASS = 0, GAIN = 00, f0 SW =0, 0.2 Vp-p input, -3 dB point, NOTE A FILPASS = 0, GAIN = 00, f0 SW = 1, 0.2 Vp-p input, -3 dB point, NOTE A FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, -3 dB point, NOTE A FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 0.2 Vp-p input, -3 dB point, NOTE A Fdg-3 YCbCr GAIN = 0dB Fdg0 YCbCr GAIN = +3dB Fdg+3 FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A fdHmax BANDWIDTH = cnt fdLcnt BANDWIDTH = min fdHmin BANDWIDTH = max fdHmax FILPASS = 0, f0 SW = 0, 0.2 Vp-p input, -3 dB point, NOTE A FILPASS = 0, f0 SW = 1, 0.2 Vp-p input, -3 dB point, NOTE A 41 46 51 27 30.3 34 12 13.4 15 7.4 8.3 9.1 4.6 5.2 5.8 2.1 2.4 2.6 21 24.1 27 14 15.7 18 6.0 6.8 8.0 − 0 − − 0 − − 0 − -0.90 0 0.90 -0.5 0 0.5 -0.23 0 0.23 -3.2 0 3.2 -1.05 0 1.05 BANDWIDTH = cnt fdHcnt BANDWIDTH = min fdHmin -0.70 0 0.70 YCbCr GAIN = -3dB TdL-3 − 4 10 YCbCr GAIN = 0dB TdL0 − 4 10 I/O delay time 1-1 FILPASS = 1, 1 MHz, NOTE A TdL+3 − 4 10 BANDWIDTH = max TdLmax 28 33 38 BANDWIDTH = cnt TdLcnt 45 48 55 BANDWIDTH = min TdLmin 96 107 120 BANDWIDTH = max TdHmax 10 16 20 BANDWIDTH = cnt TdHcnt 15 20 25 BANDWIDTH = min TdHmin 35 39 45 YCbCr GAIN = +3dB I/O delay time 1-2 I/O delay time 1-3 (YCbCr) Max fg+3 Differential 1-2 of frequency characteristic among YCbCr outputs (YCbCr) Typ. fLmax YCbCr GAIN = -3dB (YCbCr) Min BANDWIDTH = max YCbCr GAIN = +3dB Differential 1-1 of frequency characteristic among YCbCr outputs Differential 1-3 of frequency characteristic among YCbCr outputs Symbol FILPASS = 0, GAIN = 00, f0 SW = 0, 1 MHz, NOTE A FILPASS = 0, GAIN = 00, f0 SW = 1, 1 MHz, NOTE A 37 Unit MHz MHz MHz MHz MHz MHz MHz MHz ns ns ns 2006-11-13 TB1328FG Characteristic I/O delay time 1-4 (CbCr) BANDWIDTH = max Symbol TdhfLmax BANDWIDTH = cnt TdhfLcnt BANDWIDTH = min TdhfLmin BANDWIDTH = max TdhfHmax I/O delay time 1-5 (CbCr) Differential 1-1 of delay time among YCbCr outputs BANDWIDTH = cnt TdhfHcnt BANDWIDTH = min Differential 1-3 of delay time between Y and Cb/Cr outputs Differential 1-4 of delay time between Cb and Cr outputs I/O frequency characteristic 2 (CVBS,GCA) FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE A FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 1 MHz, NOTE A Max 55 60 65 80 91 100 190 220 260 20 24 30 29 34 39 66 72 80 Tddg-3 -10 0 10 YCbCr GAIN = 0dB Tddg0 -10 0 10 Tddg+3 -10 0 10 TddHmax -10 0 10 -10 0 10 BANDWIDTH = max BANDWIDTH = cnt TddHcnt FILPASS = 1, 1 MHz, NOTE A FILPASS = 0, f0 SW = 0, 1 MHz, NOTE A BANDWIDTH = min TddHmin -10 0 10 BANDWIDTH = max TddHmax 0 8 20 5 14 20 25 33 45 BANDWIDTH = cnt TddHcnt BANDWIDTH = min TddHmin BANDWIDTH = max TddHmax BANDWIDTH = cnt TddHcnt BANDWIDTH = min TddHmin GCA GAIN = min fdgcamin GCA GAIN = cnt fdgcacnt GCA GAIN = max fdgcamax GCA GAIN = min TgdLmin GCA GAIN = cnt TgdLcnt GCA GAIN = max TgdLmax I/O frequency characteristic 3 (MONITOR) Mute mode attenuation FILPASS = 0, f0 SW = 1, fc HALF = 1, 1 MHz, NOTE A fgm Gmute Among input channels Gcrschs Among inputs in a channel Gcrsins HD/VD/ SYNC-in to Video-out Gcrsync Unit ns ns ns ns ns -10 0 10 -10 0 10 -20 0 20 − 30 − − 30 − − 30 − − 10 20 − 10 20 − 10 20 0.2 Vp-p input, -3 dB point, NOTE A 60 80 − MHz 5 MHz sin wave input, NOTE A − -70 -60 dB − -70 -60 − -60 -55 − 3.4 − FILPASS = 0, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE A FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A FILPASS = 1, 1 MHz, NOTE A 5 MHz sin wave input, NOTE A Crosstalk Typ. TdhfHmin I/O delay time 2 (CVBS,GCA) Min YCbCr GAIN = -3dB YCbCr GAIN = +3dB Differential 1-2 of delay time among YCbCr outputs Test Conditions BANDWIDTH=min, NOTE A 38 ns MHz ns dB mV 2006-11-13 TB1328FG Synchronization Block (Test condition: A-SYNC = 1 (ON)) Characteristic Symbol 525/60i H/V-sync separation level Test Conditions Min Typ Max Vsep100 HV-SEP = 00, NOTE A, NOTE C 12 18 24 Vsep101 HV-SEP = 01, NOTE A, NOTE C 20 26 32 Vsep110 HV-SEP = 10, NOTE A, NOTE C 26 31 38 Vsep111 HV-SEP = 11, NOTE A, NOTE C 38 43 50 Vsep200 HV-SEP = 00, NOTE A, NOTE C 20 25 30 Vsep201 HV-SEP = 01, NOTE A, NOTE C 27 33 38 Vsep210 HV-SEP = 10, NOTE A, NOTE C 33 38 45 Vsep211 HV-SEP = 11, NOTE A, NOTE C 45 50 55 Vsep300 HV-SEP = 00, NOTE A, NOTE C 14 20 26 Vsep301 HV-SEP = 01, NOTE A, NOTE C 21 27 33 Vsep310 HV-SEP = 10, NOTE A, NOTE C 25 33 39 Vsep311 HV-SEP = 11, NOTE A, NOTE C 37 44 50 1125/60i Unit % % SVGA/60 % Threshold amplitude for HD input VthHD HV OUT = 1 0.8 − − Vp-p Threshold amplitude for VD input VthVDn HV OUT = 1 0.9 − − Vp-p VhdH High level 1.0 1.2 1.4 VhdL Low level − 0.1 0.4 Thdw0 HD WIDTH = 0 - 1.7 - Thdw1 HD WIDTH = 1 - 0.7 - H sync-in to HD-out Thdp1 HV OUT = 0, 1125/60p input, NOTE D - 90 - ns HD-in to HD-out Thdp2 HV OUT = 1, NOTE A - 20 - ns VvdH High level 1.0 1.2 1.4 VvdL Low level − 0.1 0.4 Separated VD-OUT − 290 − − 285 − − 270 − HD-OUT voltage HD-OUT width HD-OUT phase VD-OUT voltage Sync sep Tvdws 1250i ODD Tvdwodd 1250i EVEN Tvdweven When 1250i input VD-OUT width us V us us Tvdwfi Free-run VD-OUT in interlace mode − 4 − Tvdwfp Free-run VD-OUT in progressive mode − 8 − V sync-in to VD-out Tvdp Except 1250/50i input, NOTE D − 0.20 − H H sync-in to VD-out Tvdp1250 1250/50i input, H sync-in to VD-out, NOTE D − 320 − ns HV OUT = 1, NOTE A − 20 − ns Free-run 1 Free-run 2 VD-OUT phase V VD-in to VD-out Tvdphv H NOTE C: 286 mVp-p sync input for 525/60i, 0.3 Vp-p sync input for 1125/60i and SVGA/60. NOTE D: See the following figures. 39 2006-11-13 TB1328FG Characteristic Dummy HD-OUT frequency Symbol Min Typ. Max fh156 HV FREQ2 = 00000, H DMY = 1 − 15.564 − fh157/60i HV FREQ2 = 00001, H DMY = 1 − 15.701 − fh312 HV FREQ2 = 00010, H DMY = 1 − 31.401 − fh315 HV FREQ2 = 00011, H DMY = 1 − 31.401 − fh281/50i HV FREQ2 = 00100, H DMY = 1 − 27.966 − fh337/60i HV FREQ2 = 00101, H DMY = 1 − 33.771 − fh375 HV FREQ2 = 00110, H DMY = 1 − 37.288 − fh450 HV FREQ2 = 00111, H DMY = 1 − 44.746 − fh1250 HV FREQ2 = 01000, H DMY = 1 − 31.401 − fh379 HV FREQ2 = 01001, H DMY = 1 − 37.288 − fh640 HV FREQ2 = 01010, H DMY = 1 − 66.288 − fh750 HV FREQ2 = 01011, H DMY = 1 − 74.577 − fh562 HV FREQ2 = 01100, H DMY = 1 − 55.932 − fh157/30p HV FREQ2 = 10000, H DMY = 1 − 15.700 − HV FREQ2 = 10001, H DMY = 1 − 27.117 − fh281/25p HV FREQ2 = 10010, H DMY = 1 − 27.965 − fh337/30p HV FREQ2 = 10011, H DMY = 1 − 33.769 − fh270/48sf HV FREQ2 = 10100, H DMY = 1 − 27.117 − − 312.5 − fh270 fv625i Dummy VD-OUT frequency Test Conditions HV FREQ2 = 00000, V DMY = 1 fv525i HV FREQ2 = 00001, V DMY = 1 − 262.5 − fv625p HV FREQ2 = 00010, V DMY = 1 − 625 − fv525p HV FREQ2 = 00011, V DMY = 1 − 525 − fv1125i50 HV FREQ2 = 00100, V DMY = 1 − 562.5 − fv1125i60 HV FREQ2 = 00101, V DMY = 1 − 562.5 − fv750p50 HV FREQ2 = 00110, V DMY = 1 − 750 − fv750p60 HV FREQ2 = 00111, V DMY = 1 − 750 − fv1250iO HV FREQ2 = 01000, V DMY = 1, ODD − 624.5 − fv1250iE HV FREQ2 = 01000, V DMY = 1, EVEN − 625.5 − fvsvga HV FREQ2 = 01001, V DMY = 1 − 628 − fvsxga HV FREQ2 = 01010, V DMY = 1 − 1066 − fvuxga HV FREQ2 = 01011, V DMY = 1 − 1250 − fv1125p50 HV FREQ2 = 01100, V DMY = 1 − 1125 − fv525p30 HV FREQ2 = 10000, V DMY = 1 − 525 − fv1125p24 HV FREQ2 = 10001, V DMY = 1 − 1125 − fv1125p25 HV FREQ2 = 10010, V DMY = 1 − 1125 − fv1125p30 HV FREQ2 = 10011, V DMY = 1 − 1125 − fv1125s24 HV FREQ2 = 10100, V DMY = 1 − 562.5 − 40 Unit kHz H 2006-11-13 TB1328FG Other Blocks Characteristic Symbol Test Conditions Min Typ. Max Unit − 0.4 − Vp-p 0.5 1.5 2.0 µs Imnsfil200 SIG DET IMPE = 00, NOTE G 14 20 26 Imnsfil201 SIG DET IMPE = 01, NOTE G 11 15 19 Imnsfil210 SIG DET IMPE = 10, NOTE G 7 10 13 Imnsfil211 SIG DET IMPE = 11, NOTE G 4.2 6.0 7.8 XTAL oscillation amplitude Vosc NOTE A, NOTE E No signal detection filter tnsfil1 SIG LPF = 1, NOTE F, NOTE A Impedance for no signal detection filter No signal detection threshold voltage L⇔M kΩ Vthns00 SIG DET LVL = 00, NOTE H 0.45 0.55 0.65 Vthns01 SIG DET LVL = 01, NOTE H 0.70 0.80 0.90 Vthns10 SIG DET LVL = 10, NOTE H 0.90 1.05 1.15 Vthns11 SIG DET LVL = 11, NOTE H 1.15 1.30 1.40 0.8 1.0 1.2 2.8 3.0 3.2 VdcthLM DC detection threshold (DC) V Pins 1,14,27,29,31,34,49,51,53,55 M⇔H DC detection threshold (S) Input impedance of DC detection pins VdcthMH VdcthS Imdc V Pins 38,44,48,50,56,62 0.8 1.0 1.2 V Pins 1,14,27,29,31,34,49,51,53,55 100 150 - kΩ NOTE E: The amplitude of oscillation wave at the point between the crystal and the series capacitor. NOTE F: Remove the external capacitor connected to SYNC FILTER pin (pin 10), HV SEP1 = 00, SIG DET SW = 1(SYNC-1IN), SIG DET IMPE=11. The delay time from SYNC1-IN input (525/60i) to SYNC FILTER wave form. NOTE G: Remove the external capacitor connected to SYNC FILTER pin (pin 10). Connect 10 kΩ resistor between SYNC FILTER pin and GND. No input into SYNC1-IN. Measure the current (Ir) on the resistor. Imnsfil2xx = 3.3 / Ir - 10kΩ. NOTE H: Remove the external capacitor connected to SYNC FILTER pin (pin 10). Input a 0V - Vthnsxx [V] pulse of 15.7 kHz into SYNC FILTER pin. The pulse voltage when SIG DET status changes. 41 2006-11-13 TB1328FG Vcc 9V Vcc 5V Test circuit 100μF 0.01μF 0.01μF VD IN HD IN SYNC1 IN DC3 AR1 IN AL1 IN DC4 AR2 IN DC5 AL2 IN + + 100μF 470Ω V/S GND Cb1/B1 IN SYNC2 IN 16 AR4 IN AR2 OUT 15 Cr1/R1 IN AU Vcc (9V) DC2(S1) AL2 OUT AR2 OUT #35 1μF 10kΩ 14 5.6kΩ #36 100pF 1μF FB OUT 0.1μF 13 75Ω 100μF 0.01μF SCL 18 SDA 17 Vss 19 470Ω #20 #21 XTAL 20 Vdd (3.3V) 21 SDA SCL 10pF 3.579545MHz 47μF 1/2W 180Ω 0.01μF #22 VD IN 22 #23 HD IN 23 #25 1μF 4.7μF 100Ω 100Ω 0.1μF 100pF AU GND 24 26 AR1 IN SYNC1 IN 25 27 #26 1μF 5.6kΩ 0.1μF 28 AL1 IN DC3 (SW LINE1) #28 100pF 10kΩ 1μF 5.6kΩ #30 DC4(LINE3-1) 29 30 AR2 IN DC5(LINE2-1) 31 33 34 35 AL3 IN 36 Cr1/R1 IN DC6(LINE1-1) 37 AL3 IN 100pF AR3 IN 38 DC6 10kΩ 0.1μF + #33 5.6kΩ 1μF 0.1μF 10kΩ 100pF 1μF 5.6kΩ 0.1μF 5.6kΩ 1μF #32 32 AL2 IN 100pF AR3 IN + 100pF 10kΩ 75Ω AL2 OUT 11 8 10 9 HD OUT HD OUT #7 10Ω 510Ω AR1 OUT Cb1/B1 OUT AR6 IN 10Ω 4 #4 CVBS3 IN AL1 OUT 510Ω AL1 OUT #2 64 MONITOR OUT 63 AL8 IN 62 SC2 IN CVBS/Y1/G1 OUT 2 1 10kΩ DC1 510Ω 0.1μF #63 #62 10Ω MONITOR OUT 100pF 100pF 5.6kΩ 1μF 75Ω SC2 IN AL8 IN 100pF #61 61 AR8 IN 60 SY2 IN #60 SY2 IN AR8 IN AL7 IN Y3/G3 IN AR7 IN Cr2/R2 IN 75Ω 1μF #59 100pF 5.6kΩ 1μF 5.6kΩ 1μF 59 AL7 IN 58 Y3/G3 IN #58 #57 1μF 100pF 75Ω 5.6kΩ 1μF 1μF 0.1μF 75Ω 10kΩ DC10 DC9 Cr2/R2 IN 10kΩ Y2/G2 IN 75Ω 1μF #54 0.1μF 1μF 75Ω #52 10kΩ 0.1μF DC8 75Ω Cb2/B2 IN DC7 10kΩ 0.1μF #50 1μF #56 57 AR7 IN 56 Cb3/B3 IN 55 DC10(LINE1-2) 1μF 54 Cr3/R3 IN #48 75Ω DC1(S2) Cr2/r2 IN 53 DC9(LINE2-2) #47 CVBS/Y1/G1 OUT 52 Y2/G2 IN 100pF 5.6kΩ 1μF AL6 IN 51 DC8(LINE3-2) 1μF 50 Cb2/B2 IN 47 #46 75Ω Cr1/R1 OUT Cb1/B1 OUT 3 46 1μF Main out AR1 OUT #45 5.6kΩ 0.01μF 6 47μF 47μF #6 Cr1/R1 OUT 100pF 45 0.01μF 7 V/S Vcc (5V) 75Ω VD OUT 5 SC1 IN #43 49 DC7(SW LINE2) Cr2/R2 IN AL5 IN TB1328FG 1μF 100pF 5.6kΩ 1μF 75Ω VD OUT SYNC2 IN 180pF + AL6 IN SY1 IN #42 100pF CVBS3 IN 39 75Ω #44 AR6 IN AR5 IN #41 1μF SC1 IN Y1/G1 IN #40 5.6kΩ SY1 IN AL5 IN SYNC FILTER AL4 IN 40 1μF 75Ω 100pF 1μF 0.1μF #10 41 5.6kΩ #39 42 100pF #11 43 AR5 IN #38 1μF 44 Y1/G1 IN 1μF 75Ω 48 AL4 IN 5.6kΩ + Cb1/B1 IN 12 #37 AR4 IN Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure. 42 2006-11-13 7 6 5 4 3 2 1 14 13 12 11 10 9 8 9 1.5kΩ D-pin 13 3 8 12 2 7 11 6 1.5kΩ 43 H-SYNC Audio 7 R AL8 IN AR8 IN SC2 IN AR7 IN AL7 IN SY2 IN 1 Audio 8 4 Z31 14 Z2.0V 10 Z30 5 Z2.0V 15 G B 75Ω 75Ω 1μF 100pF 5.6kΩ 100pF 0;1μF 5.6kΩ 1μF MONITOR OUT 100pF 100pF 1μF 5.6kΩ 1μF 75Ω 100pF 1μF 5.6kΩ 1μF 75Ω 10kΩ 1μF Y3/G3 IN Cb3/B3 IN DC10 #55 2kΩ #63 #1 #62 #61 #60 #59 #58 #57 #56 #48 1μF 10kΩ #47 0;1μF 1μF 100pF 75Ω 5.6kΩ 1μF D-SUB15 Cr2/r2 IN #54 AL6 IN 10kΩ 1μF 0;1μF 54 Cr3/R3 IN 1kΩ 64 MONITOR OUT 63 AL8 IN 62 SC2 IN 61 AR8 IN 60 SY2 IN 59 AL7 IN 58 Y3/G3 IN 57 AR7 IN 56 Cb3/B3 IN CVBS AR1 OUT Cb1/B1 OUT AL1 OUT CVBS/Y1/G1 OUT DC1(S2) 9 10 #10 HD OUT #6 10Ω 47μF #4 #2 0.01μF VD OUT 8 11 12 13 30 AR2 IN 14 16 26 AR1 IN 15 27 DC3 (SW LINE1) 100μF 0.01μF SDA 17 SCL 18 Vss 19 XTAL 20 Vdd (3.3V) 21 VD IN 22 HD IN 23 AU GND 24 SYNC1 IN 25 28 AL1 IN DC4(LINE3-1) 29 31 DC5(LINE2-1) DC2(S1) 47μF 7 CVBS 32 AL2 IN AR2 OUT 10Ω 510Ω 10Ω 470Ω 470Ω #20 #22 #23 #25 #26 #27 #28 #29 #30 #31 #32 5.6kΩ 100Ω 100Ω 3.579545MHz 10pF 0.01μF SDA SCL 47μF 0.1μF 1/2W 180Ω 4.7μF 1μF 100pF 1μF 5.6kΩ 100pF 1μF 5.6kΩ 1μF 5.6kΩ 100pF 100pF 1μF AL2 IN AR2 IN AL1 IN AR1 IN V-SYNC H-SYNC SYNC1 IN 0;1μF 10kΩ 0;1μF 10kΩ 0;1μF 10kΩ Vcc 9V Vcc 5V DC3(SW LINE1) Audio 1 DC4(LINE3-1) DC5(LINE2-1) Audio 2 100μF 100μF 0.01μF 0.01μF Cr1/R1 OUT AL1 OUT Cb1/B1 OUT Main out Cr1/R1 OUT 6 V/S Vcc (5V) 5 SYNC FILTER 4 C SYNC2 IN 3 changed by CbCrPIN1=”1" V/S GND 2 Y TB1328FG CVBS AL2 OUT 1 Y or CVBS changed by CbCrPin3=”1" CVBS 53 DC9(LINE2-2) C Y or CVBS 55 DC10(LINE1-2) 100pF DC9 Cr3/R3 IN #46 CVBS3 IN 52 Y2/G2 IN #45 AR6 IN 1μF#53 75Ω SC1 IN 75Ω 100pF AU Vcc (9V) + 5.6kΩ AL5 IN Y2/G2 IN SC1 IN #44 SY1 IN DC(LINE2-2) #43 AR5 IN DC(LINE1-2) 1μF YorCVBS 100pF #42 Y1/G1 IN changed by CbCrPin2=”1" changed by CbCrPin2=”1" 5.6kΩ 75Ω C 75Ω 33 1μF 34 1μF 35 #41 36 #40 37 1μF 38 1μF C 75Ω AL4 IN 51 DC8(LINE3-2) 5.6kΩ #11 39 #39 Cb1/B1 IN 40 1μF AR4 IN #52 #38 41 #37 42 1μF Cr1/R1 IN 10kΩ 100pF 5.6kΩ R41 #36 0;1μF 100pF #14 AL3 IN DC(LINE3-2) Y1/G1 IN #35 AR3 IN DC6(LINE1-1) 43 #33 #51 75Ω #34 44 100pF 75Ω 5.6kΩ Cb2/B2 IN 100pF 1μF 50 Cb2/B2 IN 75Ω 49 DC7(SW LINE2) AR4 IN AL4 IN 1μF #50 1μF Cb1/B1 IN 10kΩ 0;1μF 5.6kΩ 10kΩ 100pF 45 Cr1/R1 IN 46 0;1μF 47 5.6kΩ 1μF 48 SY1 IN DC(LINE2-1) + CVBS3 IN Cb #49 Y + DC(SW LINE2) 1 1μF 8 75Ω 2 Cr2/R2 IN 9 DC6(LINE1-1) 3 D-pin 10 DC(LINE1-1) 4 Audio 3 11 Audio 4 5 Audio 5 12 AR5 IN AL5 IN DC(LINE3-1) + 6 AR3 IN AL3 IN Cr + DC(SW LINE1) + 13 AL6 IN 7 AR6 IN 14 Audio 6 TB1328FG Application circuit 1 (Typical values) 0;1μF AR2 OUT AL2 OUT 10kΩ 180pF 0.1μF VD OUT 0.01μF HD OUT 510Ω AR1 OUT 510Ω CVBS/Y1/G1 OUT 2kΩ V-SYNC S-pin 2 Input video signals, which are driven with low impedance. The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits. 2006-11-13 TB1328FG Application circuit 2 (Examples of Connectors) 75Ω 1μF 100pF 100pF 5.6kΩ 1μF 75Ω 1μF 22kΩ 5.6kΩ 1μF 39kΩ 1μF 75Ω 1μF SY1 IN AR2 IN AL2 IN DC3(SW LINE1) Cr1/R1 IN DC4(LINE3-1) Cb1/B1 IN DC5(LINE2-1) Y1/G1 IN DC6(LINE1-1) SCART 8 9 10 11 12 13 14 1 2 3 4 5 6 7 D 11 6 12 7 1 13 14 8 2 9 3 15 D-SUB15 10 4 5 DC3(SW LINE1) 23 22 VD IN 27 100Ω 4.7μF 36 HD IN 29 100Ω 1μF 75Ω 38 Cr1/R1 IN 31 D-pin 1μF 40 DC4(LINE3-1) 34 Cb1/B1 IN 27 1μF 36 DC5(LINE2-1) 29 75Ω 38 Y1/G1 IN 31 1μF 0.1μF 40 DC6(LINE1-1) 34 Z2.0V Z2.0V 5V D-SUB15 The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits. 44 2006-11-13 TB1328FG Application circuit 3 (system configuration) (1) For non-standard signals such as CVBS, YC (S-video), 525i, 625i, etc. Color decoder / IP converter / ... TB1328 Video SW Video-in Video block ADC PLL Sync-in PAL/NTSC/SECAM Color decoder Sync processor Freq counting block Sync block I/P converter Scaler HD/VD-in Sync SW The TB1328FG cannot be used for non-standard signals such as weak strength signals, ghost signals, etc. Therefore, these signals should be dealt with through the use of another device such as a color-decoder which is capable of handling these signals. In such cases, the signal switcher and the video circuits of the TB1328FG can be used. Exceptionally, “the no signal detection” can be also used for those signals. The TB1328FG cannot distinguish between component and RGB video. The different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for RGB video input only or component video input only. (2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD) Color decoder / IP converter / ... TB1328 Video SW Video-in Video block ADC PLL Sync-in Sync block Sync SW PAL/NTSC/SECAM Color decoder Sync processor Freq counting block HD/VD-in I/P converter Scaler The TB1328FG can detect the format type of standard signal inputs. The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights. 45 2006-11-13 TB1328FG Package dimensions LQFP64-P-1010-0.50A Unit: mm Weight: 0.34 g (Typ.) 46 2006-11-13 TB1328FG About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux RESTRICTIONS ON PRODUCT USE 060116EBA • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.021023_C • The products described in this document are subject to the foreign exchange and foreign trade control laws. 021023_E 47 2006-11-13