TC9462F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9462F Digital Servo Single Chip Processor The TC9462F is a single chip processor which incorporates the following function: synchronous separation protection and interpolation, EFM demodulation, Error correction, microcontroller interface, digital equalizer for use in servo LSI and servo control circuit. In addition, the TC9462F incorporates a 1 bit DA converter. In combination with the head amplifier TA2109F, TA2153FN for digital servo, the TC9462F allow simplified, adjustment-free structuring of CD player system. Features Weight: 1.6 g (typ.) · Capable of decode the text data. · Sync pattern detection, sync signal protection and synchronization can be made correctly. · Built in EFM demodulation circuit, subcode demodulation circuit. · Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. · The TC9462F respond to variable playback system. · Jitter absorbing capacity of ±6 frames. · Built in 16 KB RAM. · Built in digital out circuit. · Built in L/R independent digital attenuator. · Audio output responds to bilingual function. · Reed timing free subcode Q data and capable of synchronous output with audio data. · Built in data slicer and analog PLL (free-adjustment VCO). · Capable of automatic adjustment function of focus servo and tracking servo, for loop gain, offset and balance. · Built in RF gain automatic adjustment circuit. · Built in digital equalizer for phase compensation. · Built in RAM for digital equalizer for coefficient, and capable of variable pickup. · Built in focus, tracking servo control circuit. · Search control corresponds to every mode and can realize high speed and stable search. · Lens-kick are using speed controlled form. · Built in AFC circuit and APC circuit for CLV servo of disc motor. · Built in anti-defect and anti-shock circuit. · Built in 8 times oversampling digital filter and 1 bit DA converter. · Built in analog filter for 1 bit DA converter. · Built in zero data detect output circuit. · The TC9462F capable of 4 times speed operation. · Built in microcontroller interface circuit. · CMOS silicon structure and high speed, low power consumption. · 100 pin flat package. 1 2001-11-05 TC9462F VREF TRO FOO TEZI TEI TSIN SBAD FEI RFRP RFZI RFCT AVDD RFI SLCO AVSS VCOF VCOREF PVREF LPFO LPFN Block Diagram (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 RFGC 51 30 TMAX TEBC 52 29 TMAXS FVO 54 27 ZDET VCO Data slicer A/D DMO 55 PWM 2VREF 56 PLL TMAX 28 PDO D/A FMO 53 SEL 57 26 HSSW 25 P2VREF 24 TESIO0 FLGB 59 22 MONIT status 20 SPDA 18 SBSY IO1 65 IO2 66 Sub code decoder IO0 64 RAM ROM VSS 63 21 COFS 19 SPCK Synchronous guarantee EFM decode Servo VDD 62 control FLGD 61 CLV servo FLGC 60 Automatic adjustment circuit 23 VDD Digital equalizer FLGA 58 17 SFSY 16 DATA 15 VSS 14 VDD CKSE 69 DACT 70 12 SBOK 11 IPF 10 MBOV Clock generator TESIN 71 13 CLCK Digital out DMOUT 68 16 KRAM Address circuit IO3 67 TESIO1 72 9 DOUT VSS 73 Correction circuit 8 AOUT 1 bit DAC PXO 75 7 BCK Audio out circuit PXI 74 5 LRCK Micon interface VDD 76 6 VSS XVSS 77 3 UHSO LPF XI 78 4 EMPH XO 79 2 HSO XVDD 80 RO DVDD DVR LO DVSL TEST1 TEST2 TEST3 BUS0 91 92 93 94 95 96 97 98 99 100 RST 90 TSMOD 89 TEST4 88 CCE 87 BUCK 86 VSS 85 VDD 84 BUS3 83 BUS2 82 BUS1 81 DVSR 1 TEST0 2 2001-11-05 TC9462F Pin Function Pin No. Symbol I/O 1 TEST0 I Functional Description Remarks Test mode terminal. Normally, keep at open. With pull-up resistor. Playback speed mode flag output terminal. 2 HSO O UHSO HSO Playback Speed H H Normal H L 2 times L H 4 times L L ¾ ¾ 3 UHSO O 4 EMPH O Subcode Q data emphasis flag output terminal. Emphasis ON at “H” level and OFF at “L” level. The output polarity can invert by command. ¾ 5 LRCK O Channel clock output terminal. (44.1 kHz) L-ch at “L” level and R-ch at “H” level. The output polarity can invert by command. ¾ 6 VSS ¾ Digital GND terminal. ¾ 7 BCK O Bit clock output terminal. (1.4112 MHz) ¾ 8 AOUT O Audio data output terminal. ¾ 9 DOUT O Digital data output terminal. ¾ 10 MBOV O Buffer memory over signal output terminal. Over at “H” level. ¾ 11 IPF O Correction flag output terminal. At “H” level, AOUT output is made to correction impossibility by C2 correction processing. ¾ 12 SBOK O Subcode Q data CRCC check adjusting result output terminal. The adjusting result is OK at “H” level. ¾ 13 CLCK I/O Subcode P~W data readout clock input/output terminal. This terminal can select by command bit. 14 VDD ¾ Digital power supply voltage terminal. ¾ 15 VSS ¾ Digital GND terminal. ¾ 16 DATA O Subcode P~W data output terminal. ¾ 17 SFSY O Play-back frame sync signal output terminal. ¾ 18 SBSY O Subcode block sync signal output terminal. ¾ 19 SPCK O Processor status signal readout clock output terminal. ¾ 20 SPDA O Processor status signal output terminal. ¾ 21 COFS O Correction frame clock output terminal. (7.35 kHz) ¾ 22 MONIT O Internal signal (DSP internal flag and PLL clock) output terminal. Selected by command. This terminal output the text data with serial by command. ¾ 23 VDD ¾ Digital power supply voltage terminal. ¾ 24 TESIO0 I Test input/output terminal. Normally, keep at “L” level. The terminal that inputted the clock for read of text data by command. ¾ 25 P2VREF ¾ PLL double reference voltage supply terminal. ¾ 26 HSSW O This terminal is used to output PVREF or HiZ by command. 27 ZDET O 1 bit DA converter zero detect flag output terminal. 28 PDO O Phase difference signal output terminal of EFM signal and PLCK signal. 3 Schmitt input 2-state output. (PVREF, HiZ) ¾ 3-state output. (P2VREF, PVREF, VSS) 2001-11-05 TC9462F Pin No. Symbol I/O 29 TMAXS O Functional Description Remarks TMAX detection result output terminal. Selected by command bit (TMPS). 3-state output. (P2VREF, PVREF, VSS) TMAX detection result output terminal. Selected by command bit (TMPS). 30 31 TMAX LPFN O TMAX Detection TMAX Output Longer than fixed freq. “P2VREF” Shorter than fixed freq. “VSS” Within the fixed freq. “HiZ” 3-state output. (P2VREF, HiZ, VSS) I LPF amplifier inverting input terminal for PLL. Analog input. Analog output. 32 LPFO O LPF amplifier output terminal for PLL. 33 PVREF ¾ PLL reference voltage supply terminal. ¾ 34 VCOREF I VCO center frequency reference level terminal. Normally, keep at “PVREF” level. ¾ 35 VCOF O VCO filter terminal. 36 AVSS ¾ Analog GND terminal. 37 SLCO O Data slice level output terminal. Analog output. 38 RFI I RF signal input terminal. Analog input. (Zin: selected by command) 39 AVDD ¾ 40 RFCT I RFRP signal center level input terminal. Analog input. (Zin: 50 kW) 41 RFZI I RFRP zero cross input terminal. Analog input. 42 RFRP I RF ripple signal input terminal. Analog input. 43 FEI I Focus error signal input terminal. Analog input. 44 SBAD I Sub-beam adder signal input terminal. Analog input. 45 TSIN I Test input terminal. Normally, keep at “VREF” level. Analog input. 46 TEI I Tracking error signal input terminal. Take in at tracking servo on. Analog input. 47 TEZI I Tracking error zero cross input terminal. Analog input. (Zin: 10 kW) 48 FOO O Focus servo equalizer output terminal. 49 TRO O Tracking servo equalizer output terminal. 50 VREF ¾ Analog reference voltage supply terminal. 51 RFGC O RF amplitude adjustment control signal output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) 52 TEBC O Tracking balance control signal output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) 53 FMO O Feed equalizer output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) 54 FVO O Speed error signal or feed search equalizer output terminal. 3-state PWM signal output. (PWM carrier = 88.2 kHz) 55 DMO O Disc equalizer output terminal. (PWM carrier = 88.2 kHz for DSP, Synchronize to PXO) 56 2VREF ¾ Analog double reference voltage supply terminal. ¾ O APC circuit ON/OFF indication signal output terminal. At the laser on time, “HiZ” level at UHS = L and “H” level at UHS = H. ¾ 57 SEL Analog output. ¾ ¾ Analog power supply voltage terminal. 4 Analog output. (2VREF~AVSS) ¾ 3-state output. (2VREF, VREF, VSS) 2001-11-05 TC9462F Pin No. Symbol I/O Functional Description Remarks 58 FLGA O External flag output terminal for internal signal. Can select signal from TEZC, FOON , FOK and RFZC by ¾ command. 59 FLGB O External flag output terminal for internal signal. Can select signal from DFCT , FOON , FMON and RFZC O External flag output terminal for internal signal. Can select signal from TRON , TRSR , FOK and SRCH ¾ by command. 60 FLGC ¾ by command. External flag output terminal for internal signal. Can select signal from TRON , DMON , HYS and SHC ¾ 61 FLGD O 62 VDD ¾ Digital power supply voltage terminal. ¾ 63 VSS ¾ Digital GND terminal. ¾ 64 IO0 65 IO1 I/O 66 IO2 General I/O terminal be changed over input port or output port by command. At the input port mode, it can readout a state of terminal (H/L) by read command. At the output port mode, it outputs (H/L/HiZ) by command. ¾ 67 IO3 68 DMOUT I “L” active, when this terminal is set “L”, IO 0/1 and 2/3 output feed equalizer signal and disc equalizer signal of 2-state With pull-up resistor. PWM respectively. 69 CKSE I Normally, keep at open. With pull-up resistor. 70 DACT I DAC test mode terminal. Normally, keep at open. With pull-up resistor. 71 TESIN I Test input terminal. Normally, keep at “L” level. Analog input. 72 TESIO1 I Test input/output terminal. Normally, keep at “L” level. ¾ 73 VSS ¾ Digital GND terminal. ¾ 74 PXI I Crystal oscillator connecting input terminal for DSP. Normally, keep at “L” level. 75 PXO O Crystal oscillator connecting output terminal for DSP. 76 VDD ¾ Digital power supply voltage terminal. ¾ 77 XVSS ¾ Oscillator GND terminal for system clock. ¾ 78 XI I Crystal oscillator connecting input terminal for system clock. ¾ 79 XO O Crystal oscillator connecting output terminal for system clock. ¾ 80 XVDD ¾ Oscillator power supply voltage terminal for system clock. ¾ 81 DVSR ¾ Analog GND terminal for DA converter. (R-ch) ¾ 82 RO O R channel data forward output terminal. ¾ 83 DVDD ¾ Analog supply voltage terminal for DA converter. ¾ 84 DVR ¾ Reference voltage terminal for DA converter. ¾ 85 LO O L channel data forward output terminal. ¾ 86 DVSL ¾ Analog GND terminal for DA converter. (L-ch) ¾ 87 TEST1 I Test mode terminal. Normal, keep at open. With pull-up resistor. 88 TEST2 I Test mode terminal. Normal, keep at open. With pull-up resistor. 89 TEST3 I Test mode terminal. Normal, keep at open. With pull-up resistor. 90 BUS0 I/O 91 BUS1 I/O Micon interface data input/output terminal. 92 BUS2 I/O Schmitt input. With pull-up resistor. 93 BUS3 I/O 94 VDD ¾ by command. Digital power supply voltage terminal. 5 ¾ ¾ 2001-11-05 TC9462F Pin No. Symbol I/O Functional Description Remarks 95 VSS ― 96 BUCK I Micon interface clock input terminal. Schmitt input. 97 CCE I Command and data sending/receiving chip enable signal input terminal. The bus line becomes active at “L” level. Schmitt input. 98 TEST4 I Test mode terminal. Normal, keep at open. With pull-up resistor. 99 TSMOD I Local test mode selection terminal. With pull-up resistor. 100 RST I Reset signal input terminal. Reset at “L” level. With pull-up resistor. ¾ Digital GND terminal. Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Power supply voltage VDD -0.3~6.0 V Input voltage VIN -0.3~VDD + 0.3 V Power dissipation PD 1420 mW Operating temperature Topr -40~85 °C Storage temperature Tstg -55~150 °C 6 2001-11-05 TC9462F Electrical Characteristics (unless otherwise specified, VDD = AVDD = DVDD = XVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V, Ta = 25°C) DC Characteristics Characteristics Assured supply voltage Assured supply current Symbol Test Circuit VDD ¾ IDD ¾ Test Condition Min Typ. Max Unit Ta = -40~85°C 4.5 5.0 5.5 V Normal speed 45 50 60 50 55 65 CMOS input terminal (except analog input) 3.5 ¾ ¾ ¾ ¾ 1.5 ¾ ¾ 1.0 -1.0 ¾ ¾ ¾ ¾ 0.1 -0.1 ¾ ¾ 4 times speed XI = 16.9344 MHz mA “H” Level VIH ¾ “L” Level VIL ¾ “H” Level IIH ¾ VIH = 5 V “L” Level IIL ¾ VIL = 0 V “H” Level ITLH ¾ VIH = 5 V “L” Level ITLL ¾ VIL = 0 V “H” Level IOH (1) ¾ ¾ ¾ -1.0 “L” Level IOL (1) ¾ VOH = 4.6 V following (1) (except TMAXS, VOL = 0.4 V TMAX) 2.0 ¾ ¾ “H” Level IOH (2) ¾ VOH = 4.6 V ¾ ¾ -1.0 “L” Level IOL (2) ¾ VOH = 0.4 V 2.0 ¾ ¾ “H” Level IOH (3) ¾ VOH = 4.6 V -1.4 ¾ -0.6 “L” Level IOL (3) ¾ VOL = 0.4 V 0.6 ¾ 1.4 “H” Level IOH (4) ¾ VOH = 3.8 V ¾ ¾ -1.0 IOL (4) ¾ VOL = 0.4 V 2.0 ¾ ¾ VREF output ON resistor RON ¾ following (4) (except TMAXS, TMAX) ¾ ¾ 500 W Pull-up resistor RUP ¾ following (5) 25.0 50.0 75.0 kW RN ¾ between XI-XO and PXI-PXO terminal 1.0 2.0 3.0 MW Input voltage Input current Tri-state leak current Output current “L” Level Osc. Amp. feedback resistor CMOS Input Terminal (except analog input) following (1) following (2) following (3) following (4) V mA mA mA Terminal Name (1) Terminal HSO , UHSO , EMPH, DOUT, MBOV, IPF, SBOK, CLCK, TESIO1 DATA, SFSY, SBSY, SPCK, MONIT, TESIO0, TMAXS, TMAX, SEL FLGA, FLGB, FLGC, FLGD, IO0, IO1, IO2, IO3 (2) Terminal LRCK, BCK, AOUT, SPDA, COFS, ZDET (3) Terminal BUS0~3 (4) Terminal PDO, TMAXS, TMAX, RFGC, TEBC, FMO, FVO, DMO (5) Terminal DMOUT , CKSE , DACT , TSMOD, RST , TEST0~4 7 2001-11-05 TC9462F AC Characteristics 1. Microcomputer Interface Timing Symbol Test Circuit Test Condition Min Typ. Max CCE “H” clock pulse width tCC ¾ ¾ 120 ¾ ¾ CCE status data access time tCS ¾ CCE falling reference 0 ¾ ¾ Status data disable time tSZ1 ¾ CCE rising reference 0 ¾ ¾ CCE , BUCK delay pulse width tCB ¾ CCE falling reference 0 ¾ ¾ tBLW ¾ Write, SRC mode 120 ¾ ¾ tBLW ¾ QDRC mode 240 ¾ ¾ BUCK “H” clock pulse width (1) tBHW ¾ Write, SRC mode 120 ¾ ¾ BUCK “H” clock pulse width (2) tBHW ¾ QDRC mode (´1) 3000 ¾ ¾ BUCK “H” clock pulse width (3) tBHW ¾ QDRC mode (´2) 1500 ¾ ¾ BUCK “H” clock pulse width (4) tBHW ¾ QDRC mode (´4) 800 ¾ ¾ Write data set-up time tWS ¾ BUCK rising reference 60 ¾ ¾ Write data hold time tWH ¾ BUCK rising reference 20 ¾ ¾ PRTY data access time tBA ¾ BUCK falling reference 0 ¾ ¾ Data disable time tSZ2 ¾ BUCK falling reference 0 ¾ ¾ Read data access time tRD ¾ BUCK falling reference 0 ¾ ¾ Data disable time tSZ3 ¾ BUCK rising reference 0 ¾ ¾ Characteristics BUCK “L” clock pulse width (1) Unit ns Idle mode tCC CCE BUCK BUSi BUSi (output) ST tCS Idol mode 8 tSZ1 2001-11-05 TC9462F (2) Write command mode tCC CCE tBLW tBHW BUCK tCB tWS tWH BUSi (input) CM CL DM tSZ2 tCS BUSi (output) tBA ST tSZ3 PRTY Idol mode (3) DL Write mode BXXXXX, FXXXXX command at tCC CCE tBLW tBHW BUCK tCB tWS tWH BUSi (input) CM tCS DM DL EM EL tSZ2 BUSi (output) (4) CL tBA ST tSZ3 PRTY Read command mode tCC CCE tBLW tBHW BUCK tCB tWS tWH BUSi (input) CM tCS BUSi (output) tSZ2 ST Idol mode tRD tSZ3 tBA RD0 RDn tSZ3 PRTY Write mode 9 2001-11-05 TC9462F 2. AOUT Terminal Output Data Timing Symbol Test Circuit “H” Level tpLH ¾ “L” Level tpHL ¾ Characteristics Transfer time (1) Test Condition BCK ® AOUT Min Typ. Max ¾ ¾ 5 ¾ ¾ 5 Min Typ. Max ¾ 3 ¾ ¾ 3 ¾ Unit ns BCK tpHL tpLH AOUT 3. SPDA Output Timing Symbol Test Circuit “H” Level tpLH ¾ “L” Level tpHL ¾ Characteristics Transfer time Test Condition SPCK ® SPDA Unit ns SPCK SPDA tpHL tpLH 10 2001-11-05 TC9462F 4. DATA, CLCK Input/Output Timing (1) CLCK input mode Symbol Test Circuit “H” Level tHW “L” Level Characteristics Clock pulse width Min Typ. Max ¾ 200 ¾ ¾ tLW ¾ 200 ¾ ¾ tSu ¾ 200 ¾ ¾ “L” Level tpHL1 ¾ ¾ ¾ 5 “H” Level tpLH2 ¾ ¾ ¾ 20 “L” Level tpHL2 ¾ ¾ ¾ 20 Min Typ. Max Input set-up time Transfer time (1) Transfer time (2) Test Condition CLCK input mode Unit ns tpHL2 tpLH2 tpHL1 SFSY/COFS tSU tLW tHW CLCK DATA (2) SUBP SUBQ CLCK output mode (tHW, tLW, tpLH3; 2 times speed = 1/2, 4 times speed = 1/4) Symbol Test Circuit “H” Level tHW ¾ ¾ ¾ 1000 “L” Level tLW ¾ ¾ ¾ 1000 “L” Level tpHL1 ¾ ¾ ¾ 5 “H” Level tpLH2 ¾ ¾ ¾ 20 “L” Level tpHL2 ¾ ¾ ¾ 20 “H” Level tpLH3 ¾ ¾ ¾ 900 Characteristics Clock pulse width Transfer time (1) Transfer time (2) Transfer time (3) Test Condition CLCK output mode Unit ns tpHL2 tpLH2 tpHL1 SFSY/COFS tpLH3 tHW tLW CLCK DATA SUBP SUBQ 11 2001-11-05 TC9462F 5. SBSY, SBOK Input/Output Control Symbol Test Circuit “H” Level tpLH1 ¾ “L” Level tpHL1 ¾ “H” Level tpLH2 ¾ “L” Level tpHL2 ¾ Characteristics Transfer time (1) Transfer time (2) Test Condition Min Typ. Max ¾ ¾ 5 ¾ ¾ 5 ¾ ¾ 15 ¾ ¾ 15 Min Typ. Max ¾ ¾ 20 ¾ ¾ 15 ¾ ¾ 20 ¾ ¾ 15 ¾ ¾ 20 ¾ ¾ 15 VREF ® 2VREF ¾ ¾ 20 VSS ® VREF ¾ ¾ 10 2VREF ® VREF ¾ ¾ 15 VREF ® VSS ¾ ¾ 10 SBSY SBOK Unit ns SFSY/COFS tpLH1 tpHL1 SBSY SBOK tpLH2 tpHL2 6. Output Terminal Timing Symbol Test Circuit Output rising time (1) tor1 ¾ Output falling time (1) tof1 ¾ Output rising time (2) tor2 ¾ Output falling time (2) tof2 ¾ Output rising time (3) tor3 ¾ Output falling time (3) tof3 ¾ Output falling time (4) tor4 ¾ Characteristics Test Condition Terminal (1) Terminal (2) Terminal (3) Terminal (4) Output rising time (4) ¾ tof4 Unit ns Terminal Name (1) Terminal AOUT, BCK, COFS, LRCK (2) Terminal BUS0, BUS1, BUS2, BUS3, CLCK (3) Terminal (4) Terminal DATA, DOUT, EMPH, FLGA, FLGB, FLGC, FLGD, HSO , IO0, IO1, IO2 IO3, IPF, MONIT, MBOV, SBOK, SBSY, SEL, SFSY, SPCK, UHSO PDO, TMAXS, TMAX, RFGC, TEBC, FMO, DMO, FVO VOH VOH/2 VSS tor tof 12 2001-11-05 TC9462F Analog Circuit Characteristics 1. A/D Converter Characteristics Test Condition Min Typ. Max Unit ¾ ¾ 8 ¾ bit ¾ 176.4 ¾ KHz ¾ 176.4 ¾ KHz ¾ 88.2 ¾ KHz ¾ 176.4 ¾ KHz 0.15 ´ 2VREF ¾ 0.85 ´ 2VREF V Test Condition Min Typ. Max Unit Bit number ¾ ¾ 5 ¾ bit Sampling frequency ¾ ¾ 2.8 ¾ MHz Output signal range ¾ AVSS ¾ 2VREF V Test Condition Min Typ. Max Unit ¾ VSS ¾ 2VREF V 2 4 ¾ MHz Min Typ. Max Unit ¾ 34.6 ¾ MHz VCOREF = VREF, VCOGSL = “H” ±40 ±50 ¾ VCOREF = VREF, VCOGSL = “L” ¾ ±40 ¾ ¾ ¾ 1.0 -0.5 ¾ ¾ Test Condition Min Typ. Max Unit Input range ¾ VSS ¾ 2VREF V Input amplitude ¾ 1.0 ¾ 3.5 Vp-p ¾ 100 ¾ mV Resolution FE TE Sampling frequency SBAD XI = 16.9344 MHz RFRP Ex. VSS = 0 V, 2VREF = 4.2 V Conversion input range 2. D/A Converter (focus, tracking equalizer output) Characteristics 3. PLL Filter Amp. Characteristics Input/output signal range Frequency characteristics -3 dB point, RNF = 15 kW 4. VCO (PLL) Characteristics Center oscillation frequency Frequency variation range VCOREF terminal input voltage range Test Condition LPFO = VREF, VCOREF = VREF % upper limit lower limit VREF reference V 5. TEZI Signal Comparator Characteristics Hysteresis voltage VREF reference 13 2001-11-05 TC9462F 6. RFZI Signal Comparator Characteristics Test Condition Min Typ. Max Unit Input range ¾ VSS ¾ 2VREF V Input amplitude ¾ 1.0 ¾ 3.5 Vp-p ¾ 100 ¾ mV Min Typ. Max Unit Hysteresis voltage VREF reference (no external register to RFCT terminal) 7. Data Slicer Circuit Characteristics Test Condition (comparator) Input amplitude VREF reference ¾ 1.2 2.0 Vp-p Response time RFI = 0.6 Vp-p, f = 700 kHz 30 60 90 ns (R-2R DAC) Output conversion range ¾ 1.58 ¾ 2.59 V Output impedance ¾ ¾ 2.5 ¾ kW 8. PWM Converter Output (RFGC, TEBC, FMO, FVO, DMO) Characteristics Test Condition Min Typ. Max Unit PWM accuracy ¾ ¾ 8 ¾ bit Sampling frequency ¾ ¾ 88.2 ¾ kHz Output signal range ¾ AVSS ¾ 2VREF V 14 2001-11-05 TC9462F DAC Characteristics Symbol Test Circuit THD + N 1 S/N ratio S/N Dynamic range Cross talk Characteristics Total harmonic distortion + noise Analog output amplitude Test Condition Min Typ. Max Unit 1 kHz sine wave, full scale input, PXI = “L” ¾ -85 -80 dB 1 PXI = “L” 90 100 ¾ dB DR 1 1 kHz sine wave, -60dB input conversion, PXI = “L” 85 90 ¾ dB CT 1 1 kHz sine wave, full scale input, PXI = “L” ¾ -90 -85 dB DAC out 1 1 kHz sine wave, full scale input, PXI = “L” 1.12 1.20 1.28 Vrms Test Circuit 1: Application Circuit is Used. TC9462F Lout Application circuit 20 kHz ideal LPF Rout Distortion meter LPF: SHIBASOKU 725C (built-in filter) Distortion meter: SHIBASOKU 725C (corresponding) Characteristics Distortion Filter Setting: A-wait THD + N, CT OFF S/N, DR ON A-WAIT: IEC-A (corresponding) Application Circuit TC9462F DVSR 5V 16.9344 MHz XI DVDD XO XVSS DVR PXI DVSL 15 R-ch Analog out 100 mF 0.1 mF LO 3.3 mF 10 k9 270 W 270 W 3.3 mF L-ch Analog out 10 k9 RO 2200 pF XVDD 2200 pF 5V 2001-11-05 TC9462F Package Dimensions Weight: 1.6 g (typ.) 16 2001-11-05 TC9462F RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 17 2001-11-05