STMICROELECTRONICS TDA7303TR

TDA7303
Digital controlled stereo audio processor with loudness
Features
■
Input multiplexer:
– 3 stereo inputs
– Selectable input gain for optimal adaption
to different sources
■
Volume control in 1.25dB steps
■
Loudness function
■
Treble and bass controL
■
Four speaker attenuatorS:
– 4 independent speakers control in 1.25dB
steps for balance and fader facilities
– Independent mute function
■
SO-28
All functions programmable via serial I2C bus
Description
The TDA7303 is a volume, tone (bass and treble)
balance (Left/Right) and fader (front/rear)
processor for quality audio applications in car
radio, Hi-Fi and portable systems.
Selectable input gain and external loudness
function are provided. Control is accomplished by
serial I2C bus microprocessor interface.
The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and Low DC stepping
are obtained.
Order codes
August 2006
Part number
Package
Packing
TDA7303
SO-28
Tray
TDA7303TR
SO-28
Tape and reel
Rev 1
1/21
www.st.com
1
Contents
TDA7303
Contents
1
2
3
4
Block, test & pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3
Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Data bytes (detailed description) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/21
TDA7303
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Audio switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bass and Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/21
List of figures
TDA7303
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
4/21
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Loudness vs Volume Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Loudness vs. Frequency (CLOUD = 100nF) vs. Volume Attenuation . . . . . . . . . . . . . . . . 10
Loudness versus External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Noise versus Volume/Gain Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Signal to Noise Ratio vs. Volume Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Distortion & Noise vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Signal to Noise Ratio vs. Volume Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Distortion vs. Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Channel Separation (L Æ R) vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input Separation (L1 Æ L2, L3) vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply Voltage Rejection vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Clipping Level vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Quiescent Current vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Current vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bass Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Tone Response (with the ext. components indicated in the test circuit). . . . . . . . . 12
Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing diagram of S-bus and I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SO-28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
R3
R2
R1
C4
C5
C6
VS
11
10
2
AGND
3
SUPPLY
R1
R2
OUT(R)
22µF
C7
7
CREF
1
INPUT
SELECTOR
+ GAIN
C8 2.2µF
6
IN(R)
8
21
100nF
C10
100nF
C12
LOUD(R)
VOL
+ LOUD
TREBLE
TREBLE(L)
5.6K
R1
BOUT(R)
20
RB
BASS
100nF
C13
BIN(R)
5
2.7nF
C16
TREBLE(R)
TREBLE
SERIAL BUS DECODER + LATCHES
BASS
4
SPKR
ATT
MUTE
D98AU888
SPKR
ATT
MUTE
SPKR
ATT
MUTE
MUTE
SPKR
ATT
22
24
26
27
28
23
25
OUT RIGHT
REAR
OUT RIGHT
FRONT
DIGGND
SDA
SCL
OUT LEFT
REAR
OUT LEFT
FRONT
BUS
Block diagram
R3
L3
VOL
+ LOUD
18
RB
BOUT(L)
19
1.1
3x
2.2µF
13
L3
C3
L2
12
IN(L)
100nF
C15
BIN(L)
C17
2.7nF
Block, test & pins diagrams
9
14
L2
C2
L1
16
R2
1
RIGHT
INPUTS
LEFT
INPUTS
15
3x
2.2µF
C1
L1
17
5.6K
C11
100nF
100nF
C14
LOUD(L)
Figure 1.
OUT(L)
C9 2.2µF
TDA7303
Block, test & pins diagrams
Block diagram
5/21
Block, test & pins diagrams
1.2
Test circuit
Figure 2.
1.3
Pins connection
Figure 3.
6/21
Test Circuit
Pin Connection (Top view)
TDA7303
TDA7303
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Symbol
VS
2.2
Parameter
Unit
10.0
V
-40 to 85
°C
-55 to +150
°C
Min.
Typ.
Max.
Unit
9
10
V
Operating Supply Voltage
Tamb
Ambient Temperature
Tstg
Storage Temperature Range
Quick reference data
Table 2.
Quick reference data
Symbol
Parameter
VS
Supply Voltage
6
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
%
S/N
Signal to Noise Ratio
106
dB
SC
Channel Separation f = 1KHz
103
dB
Volume Control 1.25dB step
Bass and Treble Control 2dB step
Fader and Balance Control 1.25dB step
Input gain 3.75db step1.25dB step
Mute Attenuation
2.3
Value
Vrms
-78.75
0
dB
-14
+14
dB
-38.75
0
dB
0
11.25
dB
100
dB
Thermal data
Table 3.
Thermal data
Symbol
Parameter
Rth j-pins
Thermal Resistance Junction-pins
Value
Unit
max 85
°C/W
7/21
Electrical specifications
TDA7303
2.4
Electrical characteristics
Table 4.
Electrical Characteristcs
(Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all control flat (G=0), f = 1KHz unless
otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
6
9
10
V
8
11
mA
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
Ripple Rejection
60
80
dB
50
KΩ
INPUT SELECTORS
RII
Input Resistance
VCL
Clipping Level
2
2.5
Vrms
SIN
Input Separation (2)
80
100
dB
RL
Output Load resistance
Input 1, 2, 3, 4
pin 7, 17
2
KΩ
GINmin
Min. Input Gain
GINmax
Max. Input Gain
11.25
dB
GSTEP
Step Resolution
3.75
dB
2
µV
33
kΩ
eIN
Input Noise
-1
G = 11.25dB
0
1
dB
VOLUME CONTROL
RIN
Input Resistance
CRANGE Control Range
70
75
80
dB
AVMIN
Min. Attenuation
-1
0
1
dB
AVMAX
Max. Attenuation
70
75
80
dB
ASTEP
Step Resolution
0.5
1.25
1.75
dB
-1.25
0
1.25
dB
2
dB
2
dB
EA
Attenuation Set Error
ET
Tracking Error
AV = 0 to -20dB
AV = -20 to -60dB
-3
SPEAKER ATTENUATORS
Crange
Control Range
35
37.5
40
dB
SSTEP
Step Resolution
0.5
1.25
1.75
dB
1.5
dB
EA
AMUTE
Attenuation set error
Output Mute Attenuation
80
100
dB
±12
±14
±16
dB
1
2
3
dB
BASS CONTROL(1)
Gb
BSTEP
8/21
Control Range
Step Resolution
Max. Boost/cut
TDA7303
Electrical specifications
Table 4.
Electrical Characteristcs (continued)
(Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all control flat (G=0), f = 1KHz unless
otherwise specified)
Symbol
RB
Parameter
Test Condition
Min.
Internal Feedback Resistance
Typ.
Max.
44
Unit
KΩ
TREBLE CONTROL (1)
Gt
TSTEP
Control Range
Max. Boost/cut
Step Resolution
±13
±14
±15
dB
1
2
3
dB
2
2.5
AUDIO OUTPUTS
VOCL
Clipping Level
RL
Output Load Resistance
CL
Output Load Capacitance
ROUT
Output resistance
VOUT
DC Voltage Level
d = 0.3%
Vrms
2
KΩ
10
75
4.2
4.5
nF
W
4.8
V
GENERAL
eNO
Output Noise(2)
BW = 20-20KHz, flat
output muted
all gains = 0dB
2.5
5
µV
µV
3
µV
all gains = 0dB; VO = 1Vrms
106
dB
AV = 0; VIN = 1Vrms
0.01
%
AV = 20dB, VIN = 1Vrms
0.09
AV = 20dB, VIN = 1Vrms
0.04
%
103
dB
A curve all gains = 0dB
S/N
d
Sc
Signal to Noise Ratio
Distortion
Channel Separation left/right
Total Tracking error
80
0.3
%
AV = 0 to -20dB
0
1
dB
-20 to -60 dB
0
2
dB
1
V
BUS INPUTS
VIL
Input Low Voltage
VIH
Input High Voltage
3
IIN
Input Current
-5
VO
Output Voltage SDA Acknowledge IO = 1.6mA
V
+5
µA
0.4
V
1. Bass and Treble response see attached diagram (fig.22). The center frequency and quality of the resonance behaviour can
be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network
2. The selected input is grounded thru the 2.2µF capacitor.
9/21
Electrical specifications
TDA7303
2.5
Electrical characteristics curves
Figure 4.
Loudness vs Volume Attenuation
Figure 5.
Loudness vs. Frequency (CLOUD =
100nF) vs. Volume Attenuation
Figure 6.
Loudness versus External
Capacitors
Figure 7.
Noise versus Volume/Gain Setting
Figure 8.
Signal to Noise Ratio vs. Volume
Setting
Figure 9.
Distortion & Noise vs. Frequency
10/21
TDA7303
Electrical specifications
Figure 10. Signal to Noise Ratio vs. Volume
Setting
Figure 11. Distortion vs. Load Resistance
Figure 12. Channel Separation (L → R) vs.
Frequency
Figure 13. Input Separation (L1 → L2, L3) vs.
Frequency
Figure 14. Supply Voltage Rejection vs.
Frequency
Figure 15. Output Clipping Level vs. Supply
Voltage
11/21
Electrical specifications
TDA7303
Figure 16. Quiescent Current vs. Supply
Voltage
Figure 17. Supply Current vs. Temperature
Figure 18. Bass Resistance vs. Temperature
Figure 19. Typical Tone Response (with the
ext. components indicated in the
test circuit)
12/21
TDA7303
3
I2C bus interface
I2C bus interface
Data transmission from microprocessor to the TDA7303 and viceversa takes place thru the
2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be connected).
3.1
Data validity
As shown in Figure 20, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
3.2
Start and stop conditions
As shown in Figure 21 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
3.3
Byte format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by
an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 22). The peripheral (audioprocessor) that acknowledges has to pull-down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
3.5
Transmission without acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data.
This approach of course is less protected from misworking and decreases the noise
immunity.
13/21
I2C bus interface
TDA7303
Figure 20. Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 21. Timing diagram of S-bus and I2C bus
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 22. Acknowledge on the I2C bus
SCL
1
2
3
7
8
9
SDA
MSB
START
Patent note:
14/21
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
Purchase of I2C Components of STMicrolectronics,
conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the
system conforms to the I2C Standard Specifications as
defined by Philips.
TDA7303
Software specification
4
Software specification
4.1
Interface Protocol
The interface protocol comprises:
●
A start condition (s)
●
A chip address byte, containing the TDA7303 address (the 8th bit of the byte must be
0).
The TDA7303 must always acknowledge at the end of each transmitted byte.
●
A sequence of data (N-bytes + acknowledge)
●
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
4.2
Subaddress (receive mode)
Table 5.
Chip address
1
MSB
Table 6.
0
0
0
1
0
0
0
LSB
Data bytes
MSB
LSB
FUNCTION
0
0
B2
B1
B0
A2
A1
A0
Volume control
1
1
0
B1
B0
A2
A1
A0
Speaker ATT LR
1
1
1
B1
B0
A2
A1
A0
Speaker ATT RR
1
0
0
B1
B0
A2
A1
A0
Speaker ATT LF
1
0
1
B1
B0
A2
A1
A0
Speaker ATT RF
0
1
0
G1
G0
S2
S1
S0
Audio switch
0
1
1
0
C3
C2
C1
C0
Bass control
0
1
1
1
C3
C2
C1
C0
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dB steps
15/21
Software specification
4.3
TDA7303
Data bytes (detailed description)
Table 7.
Volume
MSB
0
0
B2
B1
B0
0
0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
A2
0
0
0
0
1
1
1
1
A2
A1
0
0
1
1
0
0
1
1
A1
LSB
FUNCTION
A0
0
1
0
1
0
1
0
1
A0
Volume 1.25dB steps
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
Volume 10dB steps
0
-10
-20
-30
-40
-50
-60
-70
For example a volume of -45dB is given by:
00100100
Table 8.
Speaker attenuators
MSB
1
1
1
1
0
0
1
1
0
1
0
1
B1
B1
B1
B1
B0
B0
B0
B0
0
0
1
1
1
0
1
0
1
1
LSB
FUNCTION
Speaker LF
Speaker RF
Speaker LR
Speaker RR
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
-10
-20
-30
Mute
A2
A2
A2
A2
0
0
0
0
1
1
1
1
A1
A1
A1
A1
0
0
1
1
0
0
1
1
A0
A0
A0
A0
0
1
0
1
0
1
0
1
1
1
1
For example attenuation of 25dB on speaker RF is given by: 1 0 1 1 0 1 0 0
16/21
TDA7303
Software specification
Table 9.
Audio switch
MSB
0
1
0
G1
G0
S2
LSB
FUNCTION
S1
S0
Audio Switch
0
0
Stereo 1
0
1
Stereo 2
1
0
Stereo 3
1
1
Not allowed
0
Loudness ON
1
Loudness OFF
0
0
+11.25dB
0
1
+7.5dB
1
0
+3.75dB
1
1
0dB
For example to select the stereo 2 input with a gain of +7.5dB LOUDNESS ON the 8bit
string is: 0 1 0 0 1 0 0 1
Table 10.
Bass and Treble
MSB
LSB
FUNCTION
0
1
1
0
C3
C2
C1
C0
Bass
0
1
1
1
C3
C2
C1
C0
Treble
0
0
0
0
-14
0
0
0
1
-12
0
0
1
0
-10
0
0
1
1
-8
0
1
0
0
-6
0
1
0
1
-4
0
1
1
0
-2
0
1
1
1
0
1
1
1
1
0
1
1
1
0
2
1
1
0
1
4
1
1
0
0
6
1
0
1
1
8
1
0
1
0
10
1
0
0
1
12
1
0
0
0
14
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0
17/21
Package information
5
TDA7303
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 23. SO-28 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
2.65
MAX.
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
OUTLINE AND
MECHANICAL DATA
0.104
a1
C
18/21
inch
8 ° (max.)
SO-28
TDA7303
6
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
04-Aug-2006
1
Changes
Initial release.
19/21
TDA7303
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