STMICROELECTRONICS TDA7439_08

TDA7439
Three-band digitally-controlled audio processor
Features
!
Input multiplexer
– four stereo inputs
– selectable input gain for optimal adaptation
to different sources
!
Single stereo output
!
Treble, mid-range and bass control in 2-dB
steps
!
Volume control in 1-dB steps
!
Two speaker attenuators:
– two independent speaker controls in 1-dB
steps for balance facility
– independent mute function
!
SDIP30
high-quality audio applications in car-radio and
Hi-Fi systems. Selectable input gain is provided.
All the functions are controlled by serial bus.
All functions are programmable via serial bus.
The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers.
The TDA7439 employs BIPOLAR/CMOS
technology to provide low distortion, low noise
and DC stepping.
Description
The TDA7439 is a volume, tone (bass, mid-range
and treble) and balance (left/right) processor for
Table 1. Device summary
Order code
TDA7439
March 2008
Package
SDIP30
Packaging
Tube
Rev 11
1/23
www.st.com
23
Contents
TDA7439
Contents
1
Block diagram and pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Application suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
4
5
6
Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1
Bass, mid-range stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2
Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Pin CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C bus transmission examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
No address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
Address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C bus addresses and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Chip address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Sub-address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Chip input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
TDA7439
1
Block diagram and pin out
Block diagram and pin out
Figure 1.
Block diagram
MUXOUTL
L-IN1
11
INL
15
MIN(L) MOUT(L) BIN(L)
TREBLE(L)
16
27
26
100K
L-IN2
25
BOUT(L)
23
RM
24
RB
12
100K
L-IN3
G
13
VOLUME
TREBLE
MIDDLE
SPKR ATT
LEFT
BASS
6
LOUT
100K
L-IN4
14
100K
R-IN1
30
0/30dB
2dB STEP
10
2
1
I CBUS DECODER + LATCHES
29
100K
R-IN2
SDA
DIG_GND
9
100K
R-IN3
SCL
VOLUME
G
TREBLE
MIDDLE
SPKR ATT
RIGHT
BASS
5
ROUT
8
VREF
100K
R-IN4
3
7
100K
SUPPLY
INPUT MULTIPLEXER
+ GAIN
RM
17
MUXOUTR
Figure 2.
18
INR
28
TREBLE(R)
19
RB
20
21
MIN(R) MOUT(R) BIN(R)
22
4
VS
AGND
2
BOUT(R) CREF
D95AU342B
Pin connections
SDA
1
30
SCL
CREF
2
29
DIG_GND
VS
3
28
TREBLE(R)
AGND
4
27
TREBLE(L)
ROUT
5
26
MIN(L)
LOUT
6
25
MOUT(L)
R-IN4
7
24
BOUT(L)
R-IN3
8
23
BIN(L)
R-IN2
9
22
BOUT(R)
R-IN1
10
21
BIN(R)
L-IN1
11
20
MOUT(R)
L-IN2
12
19
MIN(R)
L-IN3
13
18
INR
L-IN4
14
17
MUXOUTR
MUXOUTL
15
16
INL
D95AU340A
3/23
Electrical specifications
2
TDA7439
Electrical specifications
Table 2.
Absolute maximum ratings
Symbol
Parameter
VS
Operating supply voltage
Tamb
Operating ambient temperature
Tstg
Storage temperature range
Table 3.
Table 4.
Unit
10.5
V
0 to 70
°C
-55 to 150
°C
Value
Unit
85
°C/W
Thermal data
Symbol
Rth j-pin
Value
Parameter
Thermal resistance junction-pins
Quick reference data
Symbol
Parameter
Min
Typ
Max
Unit
9
10.2
V
VS
Supply voltage
6
VCL
Max. input signal handling
2
THD
Total harmonic distortion V = 1 V RMS, f = 1 kHz
0.01
S/N
Signal to noise ratio Vout = 1 V RMS (mode = OFF)
106
dB
SC
Channel separation f = 1 kHz
90
dB
Input gain (in 2-dB steps)
V
RMS
0.1
%
0
30
dB
Volume control (in 1-dB steps)
-47
0
dB
Treble control (in 2-dB steps)
-14
+14
dB
Middle control (in 2-dB steps)
-14
+14
dB
Bass control (in 2-dB steps)
-14
+14
dB
Balance control (in 1-dB steps)
-79
0
dB
Mute attenuation
100
dB
Table 5. shows the electrical characteristics. Refer to the test circuit in Figure 3, Tamb =
25° C, VS = 9 V, RL= 10 kΩ, generator resistance Rg = 600 Ω, all controls flat (G = 0 dB),
unless otherwise specified.
Table 5.
Symbol
Electrical characteristics
Parameter
Test condition
Min
Typ
Max
Unit
Supply
4/23
VS
Supply voltage
6
9
10.2
V
IS
Supply current
4
7
10
mA
SVR
Ripple rejection
60
90
dB
TDA7439
Electrical specifications
Table 5.
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
70
100
130
kΩ
Input stage
RIN
Input resistance
VCL
Clipping level
THD = 0.3%
2
2.5
V
RMS
SIN
Input separation
The selected input is
grounded through a 2.2 µF
capacitor
80
100
dB
Minimum input gain
-1
0
1
dB
Gin_max Maximum input gain
29
30
31
dB
1.5
2
2.5
dB
Volume control input resistance
20
33
50
kΩ
Crange
Volume control range
45
47
49
dB
Av_max
Max. attenuation
45
47
49
dB
Step resolution
0.5
1
1.5
dB
AV = 0 to -24 dB
-1.0
0
1.0
dB
AV = -24 to -47 dB
-1.5
0
1.5
dB
AV = 0 to -24 dB
0
1
dB
AV = -24 to -47 dB
0
2
dB
0
0.5
3
mV
mV
Gin_min
Gstep
Step resolution
Volume control
Ri
Astep
EA
Attenuation set error
EΤ
Tracking error
VDC
Amute
Mute attenuation
Bass control
Gb
Bstep
RB
Tstep
Control range
Mstep
RM
100
dB
Max. boost/cut
±12.0 ±14.0 ±16.0
dB
Step resolution
1
2
3
dB
Internal feedback resistance
33
44
55
kΩ
(1)
Control range
Max. boost/cut
Step resolution
Mid-range control
Gm
80
(1)
Treble control
Gt
adjacent attenuation steps
from 0 dB to Av_max
DC step
±13.0 ±14.0 ±15.0
1
2
3
dB
dB
(1)
Control range
Step resolution
Internal feedback resistance
Max. boost/cut
±12.0 ±14.0 ±16.0
dB
1
2
3
dB
18.75
25
31.25
kΩ
5/23
Electrical specifications
Table 5.
TDA7439
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Speaker attenuators
Crange
Control range
70
76
82
dB
Sstep
Step resolution
0.5
1
1.5
dB
-1.5
0
1.5
dB
-2
0
2
dB
0
3
mV
E
A
Attenuation set error
AV = 0 to -20 dB
AV = -20 to -56 dB
VDC
Amute
DC step
Adjacent attenuation steps
Mute attenuation
80
100
dB
2.1
2.6
Vrms
Audio outputs
VCLIP
Clipping level
d = 0.3%
RL
Output load resistance
2
RO
Output impedance
10
40
70
Ω
3.5
3.8
4.1
V
All gains = 0 dB;
BW = 20 Hz to 20 kHz flat
5
15
µV
AV = 0 to -24 dB
0
1
dB
AV = -24 to -47 dB
0
2
dB
VOUTDC DC voltage level
kΩ
General
ENO
Output noise
Et
Total tracking error
S/N
Signal to noise ratio
SC
Channel separation, left/right
d
Distortion
All gains 0 dB,
VO = 1 V RMS
95
106
dB
80
100
dB
AV = 0, VI = 1 V RMS
0.01
0.08
%
1
V
Bus input
VIL
Input low voltage
VIH
Input high voltage
IIN
Input current
VIN = 0.4 V
VO
Output voltage SDA
acknowledge
IO = 1.6 mA
3
-5
V
0
5
µA
0.4
0.8
V
1. For bass, mid-range and treble response: the center frequency and the response quality can be set by the
external circuitry.
6/23
TDA7439
Electrical specifications
Test circuit
2.7K
5.6nF
0.47µF
L-IN2
0.47µF
BOUT(L)
23
24
RM
G
RB
VOLUME
TREBLE
MIDDLE
SPKR ATT
LEFT
BASS
100K
6
30
0/30dB
2dB STEP
10
2
1
I CBUS DECODER + LATCHES
29
100K
LOUT
SCL
SDA
DIGGND
9
100K
VOLUME
G
TREBLE
MIDDLE
5
SPKR ATT
RIGHT
BASS
ROUT
8
0.47µF
R-IN4
BIN(L)
14
0.47µF
R-IN3
25
100K
0.47µF
R-IN2
MOUT(L)
26
100K
13
0.47µF
R-IN1
27
100nF
12
0.47µF
L-IN4
TREBLE(L)
16
22nF 100nF
100K
0.47µF
L-IN3
INL
15
11
MIN(L)
MUXOUTL
L-IN1
5.6K
18nF
2.2µF
VREF
100K
7
3
100K
INPUT MULTIPLEXER
+ GAIN
RM
4
SUPPLY
RB
VS
AGND
17
MUXOUTR
INR
18
28
TREBLE(R)
2.2µF
5.6nF
19
MIN(R)
Figure 3.
20
MOUT(R)
18nF
2.7K
21
22
BIN(R)
BOUT(R)
22nF 100nF
5.6K
100nF
2
CREF
10µF
D95AU339B
7/23
Application suggestions
3
TDA7439
Application suggestions
The first and the last stages are volume control blocks. The control range is 0 to -47 dB and
mute for the first stage and 0 to -79 dB and mute for the last one. Both control blocks have a
step resolution of 1 dB.
This very high resolution allows the implementation of systems free from any noisy
acoustical effect.
The TDA7439 audio processor provides 3 bands of tone control (bass, mid-range and
treble).
3.1
Tone control
3.1.1
Bass, mid-range stages
The bass and the mid-range cells have the same structure.
However, the bass cell has an internal resistor RB of typically 44 kΩ whilst the mid-range cell
has an internal resistor RM of typically 25 kΩ.
Several filter types can be implemented by connecting external components to the bass/mid
IN and OUT pins.
Typical responses are shown in Figure 8, Figure 9 and Figure 11.
Figure 4.
Bass/mid-range filter implementation
Ri internal
IN
OUT
C1
C2
R2
D95AU313
Figure 4. refers to the basic T-type band-pass filter. Starting from the filter component values
(R1 (internal) and R2, C1, C2 (external)) then the centre frequency fC, the gain Av at
maximum boost and the filter Q factor are computed as follows:
1
f C = ---------------------------------------------------------------2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C1 ⋅ C2
+ R2C1 + RiC1A V = R2C2
----------------------------------------------------------R2C1 + R2C2
R1 ⋅ R2 ⋅ C1 ⋅ C2
Q = ------------------------------------------------R2C1 + R2C2
8/23
TDA7439
Application suggestions
Transposing and solving for the external component values we get:
AV – 1
C1 = ----------------------------------------2 ⋅ π ⋅ Fc ⋅ Ri ⋅ Q
2
Q ⋅ C1 C2 = ----------------------------2
AV – 1 – Q
2
AV – 1 – Q
R2 = --------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ Fc ⋅ ( A V – 1 ) ⋅ Q
3.1.2
Treble stage
The treble stage is a high-pass filter whose time constant is fixed by an internal resistor
(25 kΩ typically) and an external capacitor connected between treble pins and ground.
Typical responses are shown in Figure 10 and Figure 11.
3.2
Pin CREF
The suggested value of 10 µF for the reference capacitor (CREF), connected to pin CREF,
can be reduced to 4.7 µF if the application requires faster power-on.
3.3
Electrical characteristics
Figure 5.
THD vs frequency
Figure 6.
THD vs RLOAD
9/23
Application suggestions
Figure 7.
Channel separation vs
frequency
Figure 8.
Figure 9.
Mid-range filter response
Figure 10. Treble filter response
Figure 11. Typical tone response
10/23
TDA7439
Bass filter response
I2C bus interface
TDA7439
4
I2C bus interface
Data transmission from the microprocessor to the TDA7439 and vice versa takes place
through the 2-wire I2C bus interface. This consists of the data and clock lines, SDA and SCL.
Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups).
4.1
Data validity
The data on the SDA line must be stable during the high period of the clock as shown in
Figure 12. SDA is allowed to change only when SCL is low.
4.2
Start and stop conditions
As shown in Figure 13 a start condition is a high to low transition of SDA while SCL is high.
The stop condition is a low to high transition of SDA while SCL is high.
4.3
Byte format
Every byte transferred on the SDA line must contain 8 bits. The MSB is transferred first.
There is also provision for an acknowledge bit to follow each byte to indicate that the data
has been received.
4.4
Acknowledge
The master (µP) puts a resistive high level on SDA during the acknowledge clock pulse (see
Figure 14). The peripheral (audio processor) that acknowledges has to pull down (low) the
SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the high level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
4.5
Transmission without acknowledge
Suppressing the audio processor acknowledge detection enables the µP to use a simpler
transmission: it simply waits for one clock, without checking the slave acknowledging, and
then sends the new data.
This approach has, of course, less protection from transmission errors.
11/23
I2C bus interface
TDA7439
Figure 12. Timing diagram of the data on the I2C bus
SCL
SDA
Data stable
Data can change
when clock high when clock low
Figure 13. Timing diagram of the start/stop
SCL
SDA
Start
Stop
Figure 14. Timing diagram of the acknowledge
SCL
1
SDA
MSB
2
7
6
8
9
Acknowledge
from receiver
Start
4.6
Interface protocol
The interface protocol comprises:
"
a start condition (S)
"
a chip-address byte, containing the TDA7439 address
"
a sub-address byte including an auto address-increment bit
"
a sequence of data bytes (N bytes + acknowledge)
"
a stop condition (P).
Figure 15. SDA addressing and data
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
B
DATA
D96AU420
S = Start, ACK = Acknowledge, B = Auto increment, P = Stop
12/23
MSB
ACK
LSB
DATA
ACK
P
I2C bus transmission examples
TDA7439
5
I2C bus transmission examples
5.1
No address incrementing
The TDA7439 receives a start condition followed by the correct chip address, then a sub
address with the bit B = 0 (for no address increment), then the data bytes to be sent to the
sub address and finally a stop condition.
Figure 16. SDA addressing and data for B = 0
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
DATA
MSB
ACK
LSB
MSB
0 D3 D2 D1 D0 ACK
X
X
X
LSB
DATA
ACK
P
D96AU421
5.2
Address incrementing
The TDA7439 receives a start condition followed by the correct chip address, then a sub
address with the B = 1 for address incrementing; now it is in a loop condition with an
automatic increase of the sub address up to D[3:0] = 0x7. That is, the data for sub
addresses from D[3:0] = 1000 (binary) to 1111 are ignored.
In Figure 17 below, DATA1 is directed to the sub address sent (that is, D[3:0]), DATA2 is
directed to the sub address incremented by 1 (that is, 1 + D[3:0]) and so forth until a stop
condition is received to terminate the transmission.
Figure 17. SDA addressing and data for B = 1
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
1 D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D96AU422
Table 6.
Power-on-reset conditions
Parameter
POR value
Input selection
IN2
Input gain
28 dB
Volume
MUTE
Bass
0 dB
Mid-range
2 dB
Treble
2 dB
Speaker
MUTE
13/23
I2C bus addresses and data
TDA7439
6
I2C bus addresses and data
6.1
Chip address byte
The TDA7439 chip address is 0x88.
6.2
Sub-address byte
The function is selected by the 4-bit sub address as given in Table 7. The three MSBs are
not used and bit D4 selects address incrementing (B = 1) or single data byte (B = 0).
Table 7.
Function selection: sub-address byte
MSB
LSB
Function
6.3
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
Input selector
X
X
X
B
0
0
0
1
Input gain
X
X
X
B
0
0
1
0
Volume
X
X
X
B
0
0
1
1
Bass gain
X
X
X
B
0
1
0
0
Mid-range gain
X
X
X
B
0
1
0
1
Treble gain
X
X
X
B
0
1
1
0
Speaker attenuation, R
X
X
X
B
0
1
1
1
Speaker attenuation, L
Data bytes
The function value is changed by the data byte as given in the following tables, Table 8 to
Table 14.
In the tables of input gain, volume and attenuation, not all values are shown. A desired
intermediate value is obtained by setting the three LSBs to the appropriate value.
Table 8.
Input selector value (sub address 0x0)
MSB
LSB
Input multiplexer
14/23
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
IN4
X
X
X
X
X
X
0
1
IN3
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
I2C bus addresses and data
TDA7439
Table 9.
Input gain value (sub address 0x1)
MSB
LSB
Input gain
D7
D6
D5
D4
D3
D2
D1
D0
2-dB steps
X
X
X
X
0
0
0
0
0 dB
X
X
X
X
0
0
0
1
2 dB
X
X
X
X
0
0
1
0
4 dB
X
X
X
X
0
0
1
1
6 dB
X
X
X
X
0
1
0
0
8 dB
X
X
X
X
0
1
0
1
10 dB
X
X
X
X
0
1
1
0
12 dB
X
X
X
X
0
1
1
1
14 dB
X
X
X
X
1
0
0
0
16 dB
X
X
X
X
1
0
0
1
18 dB
X
X
X
X
1
0
1
0
20 dB
X
X
X
X
1
0
1
1
22 dB
X
X
X
X
1
1
0
0
24 dB
X
X
X
X
1
1
0
1
26 dB
X
X
X
X
1
1
1
0
28 dB
X
X
X
X
1
1
1
1
30 dB
Table 10.
Volume value (sub address 0x2)
MSB
LSB
Volume
D7
D6
D5
D4
D3
D2
D1
D0
1-dB steps
X
0
0
0
0
0
0
0
0 dB
X
0
0
0
0
0
0
1
-1 dB
X
0
0
0
0
0
1
0
-2 dB
X
0
0
0
0
0
1
1
-3 dB
X
0
0
0
0
1
0
0
-4 dB
X
0
0
0
0
1
0
1
-5 dB
X
0
0
0
0
1
1
0
-6 dB
X
0
0
0
0
1
1
1
-7 dB
X
0
0
0
1
0
0
0
-8 dB
X
0
0
1
0
0
0
0
-16 dB
X
0
0
1
1
0
0
0
-24 dB
X
0
1
0
0
0
0
0
-32 dB
X
0
1
0
1
0
0
0
-40 dB
X
X
1
1
1
X
X
X
MUTE
15/23
I2C bus addresses and data
Table 11.
TDA7439
Bass gain value (sub address 0x3)
MSB
Bass gain
D7
D6
D5
D4
D3
D2
D1
D0
2-dB steps
X
X
X
X
0
0
0
0
-14 dB
X
X
X
X
0
0
0
1
-12 dB
X
X
X
X
0
0
1
0
-10 dB
X
X
X
X
0
0
1
1
-8 dB
X
X
X
X
0
1
0
0
-6 dB
X
X
X
X
0
1
0
1
-4 dB
X
X
X
X
0
1
1
0
-2 dB
X
X
X
X
X
1
1
1
0 dB
X
X
X
X
1
1
1
0
2 dB
X
X
X
X
1
1
0
1
4 dB
X
X
X
X
1
1
0
0
6 dB
X
X
X
X
1
0
1
1
8 dB
X
X
X
X
1
0
1
0
10 dB
X
X
X
X
1
0
0
1
12 dB
X
X
X
X
1
0
0
0
14 dB
LSB
Mid-range gain
Table 12.
Mid-range gain value (sub address 0x4)
MSB
16/23
LSB
D7
D6
D5
D4
D3
D2
D1
D0
2-dB steps
X
X
X
X
0
0
0
0
-14 dB
X
X
X
X
0
0
0
1
-12 dB
X
X
X
X
0
0
1
0
-10 dB
X
X
X
X
0
0
1
1
-8 dB
X
X
X
X
0
1
0
0
-6 dB
X
X
X
X
0
1
0
1
-4 dB
X
X
X
X
0
1
1
0
-2 dB
X
X
X
X
X
1
1
1
0 dB
X
X
X
X
1
1
1
0
2 dB
X
X
X
X
1
1
0
1
4 dB
X
X
X
X
1
1
0
0
6 dB
X
X
X
X
1
0
1
1
8 dB
X
X
X
X
1
0
1
0
10 dB
X
X
X
X
1
0
0
1
12 dB
X
X
X
X
1
0
0
0
14 dB
I2C bus addresses and data
TDA7439
Table 13.
Treble gain value (sub address 0x5)
MSB
LSB
Treble gain
D7
D6
D5
D4
D3
D2
D1
D0
2-dB steps
X
X
X
X
0
0
0
0
-14 dB
X
X
X
X
0
0
0
1
-12 dB
X
X
X
X
0
0
1
0
-10 dB
X
X
X
X
0
0
1
1
-8 dB
X
X
X
X
0
1
0
0
-6 dB
X
X
X
X
0
1
0
1
-4 dB
X
X
X
X
0
1
1
0
-2d B
X
X
X
X
X
1
1
1
0 dB
X
X
X
X
1
1
1
0
2 dB
X
X
X
X
1
1
0
1
4 dB
X
X
X
X
1
1
0
0
6 dB
X
X
X
X
1
0
1
1
8 dB
X
X
X
X
1
0
1
0
10 dB
X
X
X
X
1
0
0
1
12 dB
X
X
X
X
1
0
0
0
14 dB
Table 14.
Speaker attenuation value (sub address 0x6, 0x7)
MSB
LSB
Speaker attenuation
D7
D6
D5
D4
D3
D2
D1
D0
1-dB steps
X
0
0
0
0
0
0
0
0 dB
X
0
0
0
0
0
0
1
1 dB
X
0
0
0
0
0
1
0
2 dB
X
0
0
0
0
0
1
1
3 dB
X
0
0
0
0
1
0
0
4 dB
X
0
0
0
0
1
0
1
5 dB
X
0
0
0
0
1
1
0
6 dB
X
0
0
0
0
1
1
1
7 dB
X
0
0
0
1
0
0
0
8 dB
X
0
0
1
0
0
0
0
16 dB
X
0
0
1
1
0
0
0
24 dB
X
0
1
0
0
0
0
0
32 dB
X
0
1
0
1
0
0
0
40 dB
X
0
1
1
0
0
0
0
48 dB
X
0
1
1
1
0
0
0
56 dB
17/23
I2C bus addresses and data
Table 14.
TDA7439
Speaker attenuation value (sub address 0x6, 0x7) (continued)
MSB
18/23
LSB
Speaker attenuation
D7
D6
D5
D4
D3
D2
D1
D0
1-dB steps
X
1
0
0
0
0
0
0
64 dB
X
1
0
0
1
0
0
0
72 dB
X
1
1
1
1
X
X
X
MUTE
TDA7439
7
Chip input/output circuits
Chip input/output circuits
Figure 18. Pin 2
Figure 19. Pins 5, 6
VS
VS
VS
24
ROUT
20K
LOUT
CREF
20K
20µA
D96AU430
D96AU434
Figure 20. Pins 7, 8, 9, 10, 11, 12, 13, 14 Figure 21. Pins 15, 17
VS
VS
VS
20µA
20µA
MIXOUT
IN
100K
GND
VREF
D96AU425
Figure 22. Pins 20, 25
D96AU426
Figure 23. Pins 19, 26
VS
VS
20µA
20µA
25K
25K
MIN(L)
MOUT(L)
MOUT(R)
D96AU431
MIN(R)
D96AU431
19/23
Chip input/output circuits
TDA7439
Figure 24. Pins 21, 23
Figure 25. Pins 22, 24
VS
VS
20µA
20µA
44K
44K
BOUT(L)
BIN(L)
BOUT(R)
BIN(R)
D96AU429
D96AU428
Figure 26. Pins 27, 28
Figure 27. Pin 30
VS
20µA
20µA
TREBLE(L)
SCL
TREBLE(R)
50K
D96AU433
Figure 28. Pin 1
D96AU424
Figure 29. Pins 16, 18
VS
20µA
20µA
INL
SDA
INR
33K
D96AU427
D96AU423
VREF
20/23
TDA7439
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
mm
DIM.
MIN.
inch
TYP.
MAX.
A
A1
MIN.
TYP.
5.08
0.51
MAX.
0.020
3.05
3.81
4.57
0.12
0.15
0.18
B
0.36
0.46
0.56
0.014
0.018
0.022
B1
0.76
0.99
1.40
0.030
0.039
0.055
C
0.20
0.25
0.36
0.008
0.01
0.014
D
27.43
27.94
28.45
1.08
1.10
1.12
E
10.16
10.41
11.05
0.400
0.410
0.435
E1
8.38
8.64
9.40
0.330
0.340
0.370
1.778
e1
L
M
S
0.070
10.16
2.54
3.30
0.400
3.81
0.10
0°(min.), 15°(max.)
0.31
MECHANICAL DATA
0.20
A2
e
OUTLINE
AND data
Outline and
mechanical
0.13
0.15
SDIP30
in.)
SDIP30(0.400
(0.400")
0.012
21/23
Revision history
9
TDA7439
Revision history
Table 15.
22/23
Document revision history
Date
Revision
Changes
Jan-2004
9
Initial release in EDOCS DMS
Jun-2004
10
Modified presentation
21-Mar-2008
11
Updated titles to Figure 9 and Figure 10
Minor updates to presentation
TDA7439
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23/23