TDA7437N Digitally controlled audio processor Features ■ Input multiplexer – Four stereo, one mono input, and one differential input – Selectable input gain for optimal adaptation to different sources ■ Fully programmable loudness function ■ Volume control in 1dB steps including gain up to 16dB ■ Zero crossing mute, soft mute and direct mute ■ Bass and treble control ■ Four speaker attenuators- four independent speakers control in 1dB steps for balance and fader facilities ■ Pause detector programmable threshold ■ All functions programmable via serial I2C bus Description The audioprocessor TDA7437N is an upgrade of the TDA731X audioprocessor family. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very LQFP44 low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways either via the serial bus (Mute byte, bit D0), or directly on pin 28 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology. Order codes Part numbers Package Packing E-TDA7437N LQFP44 (10x 10x 1.4mm) Tray E-TDA7437NTR LQFP44 (10x 10x 1.4mm) Tape and reel December 2006 Rev 2 1/34 www.st.com 1 TDA7437N Contents 1 PIN descriptions and electrical specifications . . . . . . . . . . . . . . . . . . . . 6 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 5 2/34 3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Transmission without acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mute and pause features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Direct mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 Speakers mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 Zero crossing mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 Pause function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 No symmetrical bass cut response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.7 Transmitted data (send mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.8 TDA7437N I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9 I2C bus read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 Loudness stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.11 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.12 IN-OUT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.13 Bass & mid filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TDA7437N 5.14 Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 Curves of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3/34 TDA7437N List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. 4/34 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input stage gain middle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TDA7437N List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CLD and CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing diagram of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge on the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power on time constant vs CREF capacitor CREF = 4.7mF . . . . . . . . . . . . . . . . . . . . . . . 28 Power on time constant vs CREF capacitor CREF = 10mF . . . . . . . . . . . . . . . . . . . . . . . . 28 Power on time constant vs CREF capacitor CREF = 22mF . . . . . . . . . . . . . . . . . . . . . . . . 28 SVRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft mute ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft mute OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Zero crossing mute ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Zero crossing mute OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Symmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 unsymmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test board diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LQFP44 (10x10) Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . 32 5/34 PIN descriptions and electrical specifications PIN descriptions and electrical specifications OUT_LF PAUSE DGND SDA SCL ADDR CREF DVDD AVDD Pin description TREB-L Figure 1. AGND 1 TDA7437N 44 43 42 41 40 39 38 37 36 35 34 TREB_R 1 33 OUT_RF IN_R 2 32 OUT_LR MUXOUT_R 3 31 MID_LI LOUD_R 4 30 MID_LO DIFFGND_R 5 29 OUT_RR DIFF_R 6 28 SMEXT STEREO4_R 7 27 BASS_RO STEREO1_R 8 26 BASS_RI STEREO2_R 9 25 BASS_LO STEREO3_R 10 24 BASS_LI MONO 11 23 MID_RO MID_RI MUXOUT_L IN_L CSM STEREO3_L STEREO2_L STEREO1_L STEREO4_L DIFF_L LOUD_L Table 1. DIFFGND_L 12 13 14 15 16 17 18 19 20 21 22 D96AU435B Absolute maximum ratings Symbol Parameter AVDD, DVDD Operating supply voltage Unit 10.5 V Tamb Operating ambient temperature -40 to 85 °C Tstg Storage temperature range -55 to 150 °C Value Unit 150 °C/W Table 2. Thermal data Symbol Rth j-amb Table 3. 6/34 Value Parameter Thermal resistance junction to pins Max. Quick reference data Symbol Parameter Min. Typ. Max. Unit AVDD, DVDD Supply voltage (AVDD and DVDD must be at the same potential) 6 9 10.2 V 2.1 2.6 VCL Max. input signal handling THD Total harmonic distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to noise ratio 111 dB SC Channel separation f = 1KHz 95 dB Vrms 0.8 % TDA7437N PIN descriptions and electrical specifications Table 3. Quick reference data (continued) Symbol Parameter Max. Unit 0 15 dB Volume control 1dB step -63 16 dB Treble control 2dB step -14 +14 dB Bass control 2dB step -14 +14 dB Middle control 2dB step -14 +14 dB Fader and balance control 1dB step -79 0 dB 0 20 dB Input gain 1dB step Loudness control 1dB step Mute attenuation Min. Typ. 100 dB 7/34 2 x 4.7μF 5 x 470nF 2 x 4.7μF 5 DIFFGND_R AVDD 22μF 39 CREF 43 SUPPLY LOUD_L 2.2μF 3 2 47nF LOUD_R 4 1 5.6nF 22nF 2.7K BASS 26 100nF BASS_RI 27 BASS 47nF 28 35 19 47nF CSM SPKR ATT SPKR ATT S-MUTE MUTE CONTROL SOFT, ZERO SPKR ATT SPKR ATT S-MUTE BASS_LI 24 25 18nF 100nF 5.6K 22 MID_RI 23 MIDDLE MID_RO TREBLE VOLUME + LOUDN MIDDLE 31 100nF BASS_LO 5.6K 18nF 100nF MID_LI 2.7K 22nF I2C BUS DECODER + LATCHES 30 MID_LO 44 INGAIN 12 TREBLE 20 VOLUME + LOUDN 21 INGAIN MUXOUT_L AGND 42 41 6 DIFF_R DVDD 7 STEREO4_R 11 MONO 10 13 DIFFGND_L STEREO3_R 14 DIFF_L 9 15 STEREO4_L STEREO2_R 18 STEREO3_L 8 17 STEREO2_L STEREO1_R 16 MUXOUT_R STEREO1_L IN_R 4 x 470nF TREBL_L TREB_R MULTIPLEXER IN_L 5.6nF BASS_RO) 8/34 SMEXT D95AU249B 32 29 36 37 38 40 33 34 OUT_RF OUT_RR DIGGND SDA SCL ADDR OUT_LR OUT_LF Figure 2. PAUSE 2.2μF 47nF PIN descriptions and electrical specifications TDA7437N Block diagram TDA7437N 2 Electrical characteristics Electrical characteristics (AVDD, DVDD = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 130 KΩ Input selector (mono and stereo inputs) RI VCL Input resistance pin 7 to 11 and 15 to 18 70 100 Clipping level d ≤ 0.3% 2.1 2.6 VRMS 95 dB SI Input separation 80 RL Output load resistance 2 KΩ GI MIN Minimum input gain -0.75 0 +0.75 dB GI MAX Maximum input gain 14 15 16 dB Step resolution 0.5 1.0 1.5 dB Ea Set error -1.0 0 1.0 dB 0.5 10 mV VDC DC steps Gstep Adjacent gain steps GIMIN to GIMAX 3 mV Differential input (Pin 5, 6, 13, 14) RI CMRR d eIN GDIFF Input selector BIT D4 = 0 (0dB) 10 15 20 KΩ Input selector BIT D4 = 1(6dB) 14 20 26 KΩ Common mode rejection ratio VCM = 1VRMS ; f = 1KHz 45 70 Distortion VI = 1VRMS Input noise 20Hz to 20KHz; Flat; D6 = 0 Input resistance 0.01 dB 0.08 % μV 5 D4 = 0 -1 0 1 dB D4 = 1 -7 -6 -5 dB Pin 2 and 20 31 44 57 KΩ Differential gain Volume control RI Input resistance GMAX Maximum gain 15 16 17 dB AMAX Maximum attenuation 61 63.75 66.5 dB 0.5 1.0 1.5 dB G = 16 to -20dB -1.0 0 1.0 dB G = -20 to -63dB -2.75 2.75 dB 2 dB ASTEPC Step resolution coarse atten. EA Attenuation set error Et Tracking error 9/34 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol VDC TDA7437N Parameter DC steps Test condition Min. Typ. Max. Unit Adjacent gain steps -5 +5 mV Adjacent attenuation steps -3 +3 mV 0.5 5 mV 35 50 65 KΩ From 0dB to AMAX Loudness control (Pin 4, 12) RI Internal resistor Loud = On AMAX Maximum attenuation 19 20 21 dB Astep Step resolution 0.5 1 1.5 dB Zero crossing mute VTH AMUTE VDC Zero crossing threshold (1) WIN = 11 35 mV WIN = 10 70 mV WIN = 01 140 mV WIN = 00 280 mV 100 dB Mute attenuation DC step 80 0dB to Mute 0.1 3 mV Soft mute AMUTE TDON TDOFF Mute attenuation ON delay time OFF current 50 65 CCSM = 22nF; 0 to -20dB; I = IMAX 0.8 1.5 2.0 ms CCSM = 22nF; 0 to -20dB; I = IMIN 25 45 60 ms VCSM = 0V; I = IMAX 20 40 60 mA VCSM = 0V; I = IMIN RINT Pullup resistor (pin 28) VSMH (pin 28) Level high VSML (pin 28) Level low (2) dB 2 μA 100 KΩ 3.5 V Soft mute active 1 V Bass control ±11.5 ±14 ±16 dB Step resolution 1 2 3 dB Internal feedback resistance 31 44 57 KΩ ±11.5 ±14 ±16 dB 1 2 3 dB 17.5 25 32.5 KΩ Crange Control range Astep Rg Middle control Crange Control range Astep Step resolution Rg 10/34 Internal feedback resistance TDA7437N Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit ±13 ±14 ±15 dB 1 2 3 dB Treble control CRANGE Control range Astep Step resolution Speaker attenuators CRANGE Control range Astep 79 Step resolution AV = 0 to -40dB 0.5 1 Output mute attenuation Data word = 1111XXXX 80 100 EA Attenuation set error AV = 0 to -40dB VDC DC steps Adjacent attenuation steps AMUTE 0.1 dB 1.5 dB dB 1.5 dB 3 mV Audio output Vclip Clipping level d = 0.3% 2.1 2.6 Vrms RL Output load resistance 2 RO Output impedance 50 90 140 W VDC DC voltage level 3.5 3.8 4.1 V KΩ Pause detector VTH WIN = 11 35 mV WIN = 10 70 mV WIN = 01 140 mV WIN = 00 280 mV Pause threshold IDELAY Pull-up current VTHP Pause threshold 15 25 35 3.0 μA V General VCC Supply voltage 6 9 10.2 V ICC Supply current 7 10 13 mA 70 90 dB μV PSRR Power supply rejection ratio f = 1KHz Output noise Output muted (B = 20 to 20kHz flat) 4 All gains 0dB (B = 200 to 20kHz flat) 6 15 μV AV = 0 to -20dB 0 1 dB AV = -20 to -60dB 0 2 dB eNO Et Total tracking error S/N Signal to noise ratio SC Channel separation L - R All Gains = 0dB; VO = 2.1Vrms 80 111 dB 95 dB 11/34 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol d TDA7437N Parameter Test condition Distortion Min. VIN =1V all gain = 0dB Typ. Max. Unit 0.01 0.08 % 1 V Bus inputs VIL Input low voltage VlN Input high voltage IlN Input current VIN = 0.4V VO Output voltage SDA acknowledge IO = 1.6mA 3 V -5 0.1 5 μA 0.4 V 1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold 2. Internal pullup resistor to Vs/2; "LOW" = softmute active Note: The ANGND and DIGGND layout wires must be kept separated. A 50Ω resistor is recommended to be put as far as possible from the device. The CLD - and CDR - can be short-circuited in applications providing 3 wires CD signal Figure 3. CLD and CDR CD L+ L+ ∼RL- = LR- R+ R+ D02AU1384 CLD - = DIFFINLGND CDR - = DIFFINRGND 12/34 TDA7437N TDA7437N 3 I2C bus interface I2C bus interface Data transmission from the microprocessor to the TDA7437N, and vice versa, takes place through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pullup resistors to positive supply voltage must be externally connected). 3.1 Data validity As shown in Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. 3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 6). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledgment after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without acknowledgment To avoid detection of the acknowledge clock pulse of the audioprocessor, the microprocessor can use a simpler transmission: it simply waits one clock pulse, and sends the new data. This is less protected from any errors and will decrease the immunity to noise. 13/34 I2C bus interface Figure 4. TDA7437N Data validity SDA SCL DATA LINE STABLE, DATA VALID Figure 5. CHANGE DATA ALLOWED D99AU1031 Timing diagram of I2C Bus SCL I2CBUS SDA D99AU1032 START Figure 6. STOP Acknowledge on the I2C Bus SCL 1 2 3 7 8 9 SDA MSB START 14/34 D99AU1033 ACKNOWLEDGMENT FROM RECEIVER TDA7437N Software specification 4 Software specification 4.1 Interface protocol The interface protocol comprises of: ● A start condition (s) ● A chip address byte, (the LSB bit determines read (=1)/write (=0) transmission) ● A subaddress byte. ● A sequence of data (N-bytes + acknowledge) ● A stop condition (P) CHIP ADDRESS MSB S 1 0 SUBADDRESS MSB LSB 0 0 1 0 A R/W DATA 1 to DATA n ACK LSB X X X I A3 A2 A1 A0 MSB ACK LSB DATA ACK P ACK = Acknowledge; S = Start; P = Stop; I = Auto increment; X = Not used Max clock speed 500kbits/s ADDRpin open A = 0 ADDRpin close to Vs A = 1 4.2 Auto increment If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled. 4.3 Subaddress (receive mode) Table 5. Subaddress (receive mode) MSB X LSB X X I FUNCTION A3 A2 A1 A0 0 0 0 0 Input selector 0 0 0 1 Loudness 0 0 1 0 Volume 0 0 1 1 Bass, Treble 0 1 0 0 Speaker attenuator LF 0 1 0 1 Speaker attenuator LR 0 1 1 0 Speaker attenuator RF 0 1 1 1 Speaker Attenuator RR 1 0 0 0 Input gain middle 1 0 0 1 Mute 15/34 Software specification 4.4 TDA7437N Transmitted data Table 6. Send mode MSB LSB X X X X X SM ZM P P = Pause (Active low) ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress. 4.5 Data byte specification Table 7. Data byte specification MSB LSB Function D7 X D6 X D5 D4 D3 D2 D1 D0 1 0 0 0 Differential 1 0 0 1 Stereo 1 1 0 1 0 Stereo 2 1 0 1 1 Stereo 3 1 1 0 0 Stereo 4 1 1 0 1 Mono 0 X X X DC connect (1) X X 0 0 Half-diff 0dB (2) 0 1 Half-diff -6dB (2) 1 0 Full-diff 0dB (3) 1 1 Full-diff -6dB (3) 1. Selected when using a 3 wire differential source (pins 5 and 13 shorted) 2. Selected when using a 4 wire differential source 3. OUTR-INR (OUTL-INR) short circuited internally (no need for external connection Table 8. Loudness MSB D7 16/34 D6 LSB Function D5 D4 D3 D2 D1 D0 Loudness step 0 0 0 0 0 0 0dB 0 0 0 0 0 1 1dB 0 0 0 0 1 0 2dB 0 0 0 0 1 1 3dB TDA7437N Software specification Table 8. Loudness (continued) MSB D7 D6 LSB Function D5 D4 D3 D2 D1 D0 Loudness step 0 0 0 1 0 0 4dB 0 0 0 1 0 1 5dB 0 0 0 1 1 0 6dB 0 0 0 1 1 1 7dB 0 0 1 0 0 0 8dB 0 0 1 0 0 1 9dB 0 0 1 0 1 0 10dB 0 0 1 0 1 1 11dB 0 0 1 1 0 0 12dB 0 0 1 1 0 1 13dB 0 0 1 1 1 0 14dB 0 0 1 1 1 1 15dB 0 1 0 0 0 0 16dB 0 1 0 0 0 1 17dB 0 1 0 0 1 0 18dB 0 1 0 0 1 1 19dB 0 1 0 1 0 0 20dB 1 Loudness off Fine volume 0 0 0dB 0 1 -0.25dB 1 0 -0.5dB 1 1 -0.75dB Table 9. Mute MSB LSB Function D7 D6 D5 D4 D3 D2 D1 0 0 1 Soft mute on 0 0 1 soft mute with fast slope 0 1 1 Soft mute with slow slope 0 1 1 D0 1 Zero mute Direct mute Reset 17/34 Software specification Table 9. TDA7437N Mute (continued) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Zero cross window (280mV) 0 1 0 Zero cross window (140mV) 1 0 0 Zerocross window (70mV) 1 1 0 Zerocross window (35mV) 0 Non symmetrical bass 1 Symmetrical bass Table 10. Volume MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0dB 1 0 0 1 -1dB 1 0 1 0 -2dB 1 0 1 1 -3dB 1 1 0 0 -4dB 1 1 0 1 -5dB 1 1 1 0 -6dB 1 1 1 1 -7dB 1 18/34 1 0 0 0 0 16dB 1 0 0 0 1 8dB 1 0 0 1 0 0dB 1 0 0 1 1 -8dB 1 0 1 0 0 -16dB 1 0 1 0 1 -24dB 1 0 1 1 0 -32dB 1 0 1 1 1 -40dB 1 1 0 0 0 -48dB 1 1 0 0 1 -56dB 0 X X X X X X X Mute TDA7437N Software specification Table 11. Speaker MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 1.25dB step Table 12. 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 1 1 1 X X X Mute Bass treble MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 Treble step 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 19/34 Software specification Table 12. TDA7437N Bass treble (continued) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB Bass steps 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 0 2dB 1 0 1 4dB 1 0 0 6dB 0 1 1 8dB 0 1 0 10dB 1 0 0 1 126B 1 0 0 0 14dB 1 1 Table 13. Input stage gain middle MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 In-gain step 20/34 0 0 0 0 0dB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB TDA7437N Software specification Table 13. Input stage gain middle (continued) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1 7dB 1 0 0 0 8dB 1 0 0 1 9dB 1 0 1 0 10dB 1 0 1 1 11dB 1 1 0 0 12dB 1 1 0 1 13dB 1 1 1 0 14dB 1 1 1 1 15dB Middle step 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 126B 1 0 0 0 14dB 21/34 Mute and pause features 5 TDA7437N Mute and pause features The TDA7437N provides three types of mute, controlled via I2C bus (see Table 9 Mute byte register). 5.1 Soft mute Bit D0 = 1 → Soft mute ON Bit D0 = 0 → Soft mute OFF It allows an automatic soft muting and unmuting of the signal. The time constant is fixed by an external capacitor Csm inserted between pin Csm and ground. Once the external capacitor is fixed, two different slopes (time constant) are selectable by programming of bit D1. Bit D1 = 0 → fast slope (I=Imax) Bit D1 = 1 → slow slope (I=Imin) The soft mute generates a gradually decreasing signal, avoiding big click noise of an immediate high attenuation, without necessity to program a sequence of decreasing volume levels. A response example is reported in Figure 11 (mute), and Figure 12 (unmute). The final attenuation obtained with soft mute ON is 60dB typical. The used reference parameter is the delay time taken to reach 20dB attenuation (no matter what the signal level is). Using a capacitor Csm = 22nF this delay is: d = 1. 8mswhen selected Fast slope mode (bit D1=0) d = 25 ms when selected Slow slope mode (bit D1=1 In the application, the soft mute ON programming should be followed by programming of direct mute on (see 5.2), in order to achieve a final 100dB attenuation. In addition to the I2C bus programming, the Soft Mute ON can be generated in a fast way by forcing a LOW level at pin SMEXT (TTL Level compatible). This approach is recommended for fast RDS AF switching. The Soft Mute status can be detected via I2C bus, reading the Transmitted Byte, bit SM (see Table 6). read bit SM = 1 soft mute status ON read bit SM = 0 soft mute status OFF 5.2 Direct mute bit D3 = 1 Direct mute ON bit D3 = 0 Direct mute OFF The direct mute bit forces an internal immediate signal connection to ground. It is located just before the Volume/Loudness stage, and gives a typical 100dB attenuation. 22/34 TDA7437N 5.3 Mute and pause features Speakers mute An additional direct mute function is included in the speakers attenuators stage. The four output LF, RF, LR, RR can be separately muted by setting the speaker attenuator byte to the value 01111111 binary. Typical attenuation level 100dB. This mute is useful for fader and balance functions. It should not be applied for system mute/unmute, because it can generate noise due to the offset of previous stages (bass / treble). 5.4 Zero crossing mute bit D2 = 1 D4 = 0 zero crossing mute ON bit D2 = 0 D4 = 0 zero crossing mute OFF The mute activation/deactivation is delayed until the signal waveform crosses the DC zero level (Vref level). The detection works separately for left and right channels (see Figure 13 and Figure 14). Four different window thresholds are software selectable by two dedicated bits. bit D6 bit D5 Window 0 0 Vref DC +/-280mV 0 1 Vref DC +/-140mV 1 0 Vref DC +/-70mV 1 1 Vref DC +/-35mV The zero crossing mute activation/deactivation starts when the AC signal level falls inside the selected window (internal comparator). The zero crossing mute (and pause) detector is always active. It can be disabled, if the feature is not used, by forcing the bit D4 = 1 Zero crossing and pause detector reset. In this way the internal comparator logic is stopped, eliminating its switching noise. The zero cross mute status is detected reading the transmitted byte bit ZM. bit ZM = 1 zero cross mute status ON bit ZM = 0 zero cross mute status OFF 5.5 Pause function On chip is implemented by a pause detector block. It uses the same 4 windows threshold selectable for the zero crossing mute, bit D6,D5 byte MUTE (see above). The detector can be put into OFF by forcing bit D4 = 1, otherwise it is active. Pause detector information is available at the PAUSE pin. A capacitor must be connected between the PAUSE pin and ground. 23/34 Mute and pause features TDA7437N When the incoming signal is detected to be outside the selected window, the external capacitor is discharged. When the signal is inside the window, the capacitor is integrating up (see Figure 15 and Figure 16). a) by reading directly the Pause pin level.The ON/OFF voltage threshold is 3.0V typical. Pause OFF = level low (< 3.0V) Pause ON = level high ( ; 3.0V) b) by reading via I2C bus the transmitted byte, bit PP = 0 pause active. P = 1 no pause detected. The external capacitor value fixes the time constant. The pull up current is 25uV typical, with input signal Vin = 1Vrm --; Vdc pin pause = 15mV Vin = 0Vrms --; Vdc pin pause = 5.62V For example choosing Cpause = 100nF the charge up constant is about 22ms. Instead with Cpause = 15nF the charge up constant is about 360μs. The pause detection is useful in applications like RDS, to perform noiseless tuning frequency jumps, avoiding the use of the mute. 5.6 No symmetrical bass cut response bit D7 = 0 No symmetrical bit D7 = 1 Symmetrical The bass stage has the option to generate an unsymmetrical response, for cut mode settings (bass level from -2db to - 14dB) For example using a T-type band pass external The feature is useful for human ear equalization in a noisy environment, like a car. See examples in Figure 17 (symmetrical response) and Figure 18 (unsymmetrical response). 5.7 Transmitted data (send mode) bitP = 0Pause active bitP = 1No pause detected bitZM = 1Zero cross mute ON bitZM = 0Zero cross mute OFF bitSM = 1Soft mute ON bitSM = 0Soft mute OFF bitST = 1Stereo signal detected (input MPX) bitST = 0Mono signal detected (input MPX) The TDA7437N allows the reading of four info bits. 24/34 TDA7437N Mute and pause features The type (stereo/mono) of received broadcasting signal is easily checked and displayed by using the ST bit. The P bit check is useful in tuning jumps without signal muting. The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON, MUTE byte) and not when the signal level has reached the 60 dB final attenuation. 5.8 TDA7437N I2C bus protocol The protocol is standard I2C, using subaddress byte plus data bytes (as shown within Chapter 4). The optional autoincrement mode allows to refresh all the bytes registers with transmission of a single subaddress, reducing drastically the total transmission time. Without autoincrement, subaddress bit I = 0, to refresh all the bytes registers (10), it is necessary to transmit 10 times the chip address, the subaddress and the data byte. Working with a 100Kb/s clock speed the total time would be : [(9*3+2)*10]bits*10us=2.9ms Instead using autoincrement mode, subaddress bit I=1, the total time will be: (9*12+2)*10us=1.1ms. The autoincrement mode is useful also to refresh partially the data. For example to refresh the 4 speakers attenuators it is possible to program the subaddress Spkr LF (code XX010100), followed by the data byte of SPKR LF, LR, RF, RR in sequence. Note: that the autoincrement mode has a module 16 counter, whereas the total used register bytes are 10. It is not correct to refresh all the 10 bytes starting from a subaddress different than XX010000. For example; using subaddress XX010010 (volume), the registers from Volume to Mute (see Table 5) are correctly updated, but the next two transmitted bytes, refer instead to the wanted Input selector, and Loudness are discharged. (the solution in this case is to send two separate patterns in autoincrement mode, the first composed by address, subaddress XX010010, 8 data bytes, and the second composed by address, subaddress XX010000, 2 data bytes). With autoincrement disabled, the protocol allows the transmission in sequence of N data bytes of a specific register, without the necessity to resend the address and subaddress bytes, each time. This feature can be implemented, for example, if a gradual volume change has to be performed (the MCU does not send the STOP condition, but keeps the TDA7437N communication active). Warning: The TDA7437N always needs to receive a STOP condition, before beginning a new START condition. The device doesn't recognize a START condition if a previously active communication was not ended by a STOP condition. 25/34 Mute and pause features 5.9 TDA7437N I2C bus read mode The TDA7437N sends the master a 1 byte "transmitted info" via I2C bus in read mode. The read mode is master activated by sending the chip address with LSB set to 1, followed by an acknowledge bit. The TDA7437N recognizes the request. At the following master generated clock bits, the TDA7437N issues the transmitted inFO byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: 5.10 ● acknowledge the reception, starting in this way the transmission of another byte from the TDA7437N. ● no acknowledge, stopping the read mode communication. Loudness stage The previous SGS-THOMSON audioprocessors implemented a fixed loudness response, only ON/OFF sw programmable. No possibility to change the loud boost rate at a certain volume level. The TDA7437N implements a fully programmable loudness control in 20 steps of 1dB. It allows a customized loudness response for each application. The external network connected to the loudness pins LOUD_L and LOUD_R fixes the type of loudness response. 5.11 1. Simple capacitor. The loudness effect is only a boost of low frequencies. (see Figure 19) 2. Second order loudness (boost of low and high frequencies). 3. Second order decreased type loudness (lower boost of low and high frequencies). 4. Second order modified type loudness (higher boost of low and high frequencies). Treble stage The treble stage is a simple high pass filter, it’s time constant is fixed by internal resistor (typically 50Kohm), and an external capacitor, connected between pins TREB_R/TREB_L and ground. 5.12 IN-OUT pins The multiplexer output is available at OUT_R and OUT_L pins for the optional connection of an external graphic equalizer (TDA7316/TDA7317), surround chip (TDA7346) etc. The signal is fed in again at pins IN_L and IN-R. In the case of an application without any external devices, the pins OUT_L/OUT_R and IN_L/IN_R can be left unconnected, if bit D3 byte input selector is forced = 0 (DC connect). Instead if bit D3 is kept = 1 an external decoupling capacitor must be provided between OUTR/INR and OUTL/INR to avoid signal DC jumps, generating "clicking" output noise. The input impedance of the next volume stage is 44Kohm typical (minimum 31Kohm). A capacitor no lower than 1mF should be used. 26/34 TDA7437N 5.13 Mute and pause features Bass & mid filters Several bass filter types can be implemented. Normally it is the basic T-type bandpass filter that is used. Starting from the filter component values (R1 internal and R2, C1, C2 external), the centre frequency Fc, the gain Av at max bass boost and the filter Q factor are computed as follows: 1 F c = ----------------------------------------------------------------2 ⋅ Π ⋅ R1 ⋅ R2 ⋅ C1 ⋅ C2 R2 ⋅ C2 + R2 ⋅ C1 + R1 ⋅ C1 A v = -------------------------------------------------------------------------R2 ⋅ C1 + R2 ⋅ C2 Vice versa fixed Fc, Av, and R1 (internal typ.±30%), the external component values are Av – 1 C1 = --------------------------------2 ⋅ Π ⋅ R1 ⋅ Q Q ⋅ Q ⋅ C1 C2 = ----------------------------------Av – 1 – Q ⋅ Q ( R1 ⋅ R2 ⋅ C1 ⋅ C2 ) Q = -----------------------------------------------------R2 ⋅ C1 + R2 ⋅ C2 Av – 1 – Q ⋅ Q R2 = --------------------------------------------------------------------2 ⋅ Π ⋅ C1 ⋅ F c ⋅ ( A v – 1 ) ⋅ Q 5.14 Input selector The multiplexer selector can choose one of the following inputs: ● a differential CD stereo input. ● a mono input. ● four stereo input The signal fed to the input pins must be decoupled via series capacitors. The minimum allowed value depends on the correspondent input impedance. For the CD diff input (Zi = 10Kohm worst case) a Cin = 4.7uF is recommended. For the other inputs (70Kohm worst case, a Cin=1uF is recommended. 27/34 Curves of electrical characteristics TDA7437N 6 Curves of electrical characteristics Figure 7. Power on time constant vs CREF capacitor CREF = 4.7μF V (1V/div) 2 BWL 2 1 CREF BWL 0.5s/DIV TIME Power on time constant vs CREF capacitor CREF = 22μF 0.5s/DIV TIME Figure 10. SVRR vs. frequency D95AU382 V (1V) D95AU381 OUT LF 1 CREF Power on time constant vs CREF capacitor CREF = 10μF V (1V/div) D95AU380 OUT LF Figure 9. Figure 8. D95AU383 SVRR (dB) -40 -50 μF 22 4.7μF -60 μF 10 47μF -70 2 OUT LF -80 1 CREF VS=8V Ripple=0.2VRMS AV=-15dB -90 -100 BWL 1s/DIV 10 TIME Figure 11. Soft mute ON (a) 100 1K 10K Freq(Hz) (b) V SOFT MUTE=ON SLOPE=FAST Vout=500mVrms V D95AU384 Main Menu Chan 2 1ms 0.2V Vout Pin Csm Chan 3 1ms 2V CH1 9V DC SOFT MUTE 28/34 x TIME CH1 0.5V 10 ~ CH2 20mV10x ~ CH3 0.2V10x = x CH4 20mV 10 = T/div 1ms TDA7437N Curves of electrical characteristics Figure 12. Soft mute OFF (a) (b) V V Main Menu Vout Chan 2 1ms 0.2V SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms Chan 1 1ms 2V D95AU387 Pin Csm CH1 9V DC TIME SOFT MUTE Figure 13. Zero crossing mute ON Figure 14. Zero crossing mute OFF ZERO CROSSING MUTE = ON Panel STATUS Memory ZERO CROSSING MUTE = OFF D95AU389 V x Chan 1 0.5ms 0.2V LEFT D95AU390 V LEFT Main Menu x Chan 2 0.2ms 1V RIGHT x Chan 2 0.5ms 0.2V Save PANEL Recall Auxiliary Setups Memory Card x Chan 1 0.2ms 0.5V Multi Zoom off X-Y mode Persistance mode RIGHT Return CH2 528mV DC TIME Figure 15. Pause detector 2ms TIME CH1 2.7V DC Figure 16. Pause detector US PAUSE DETECTOR ZCW=140mV Cpause=100nF D02AU1385 V Vout C O C 0 Cpause 00 D02AU1386 Vout Main Menu Main Menu Chan 1 20ms 0.2V Chan 2 20ms 2V CH2 4.12V DC TIME Chan 2 20ms 2V Chan 3 20ms 0.2V CH2 4.08V DC CH1 20mV10x ~ x BWL CH2 0.2V 10x= CH3 20mV 10 ~ x CH4 5mV 10 ~ T/div 20ms 29/34 Curves of electrical characteristics TDA7437N Figure 17. Symmetrical bass Figure 18. unsymmetrical bass D95AU393 (dB) ATT (dB) D95AU394 10 10 5 5 0 0 -5 -10 -5 -15 -10 -20 -15 -25 10 100 1K 10K Freq(Hz) Figure 19. Loudness ATT (dB) D98AU887 18 16 14 12 10 8 6 4 2 0 10 30/34 100 1K 10K Freq(Hz) 10 100 1K 10K Freq(Hz) TDA7437N Curves of electrical characteristics Figure 20. Test board diagram GND VCC CON1 C17 22μF C18 100nF R4 2.7K TRR IN_R C21 2.2μF C22 4.7nF CON4 O_R LOUDR 44 43 42 ADDR DVDD AGND TRL C20 5.6nF AVDD JP2 JP1 C19 5.6nF 41 C11 18nF C10 22nF MIDRI 40 R3 5.6K C8 100nF MIDRO 31 C7 100nF BASSRO CREF BASSRI 27 30 C16 22μF 39 26 1 2 24 3 23 4 22 C23 4.7μF DIFG_R C24 4.7μF DIFF_R C25 470nF ST4_R C26 470nF ST1_R C27 470nF ST2_R C28 470nF ST3_R C29 470nF MONO 20 DIFG_R DIFF_R ST4_R ST1_R ST2_R ST3_R MONO LOUDR BASSLO BASSLI MIDLO MIDLI 21 6 38 7 28 37 8 36 9 C5 100nF C4 22nF O_L SCL 11 33 12 13 14 DIFF_R 15 ST4_R 16 ST1_R 17 ST2_R 18 ST3_R 35 19 CSM PAUSE 29 32 SCL JP3 SMEX SMEX SDA SDA DGND DGND R5 50 OUTLF RF LR OUTRR LF RF C12 LR C9 RR GND C31 4.7μF C32 4.7μF CON3 C13 DIFG_L DIFF_L R1 2.7K CON2 C14 34 R2 5.6K C3 18nF C2 2.2μF 10 DIFG_R C6 100nF I_L 5 C30 4.7nF CON5 25 C1 2.2nF C15 10μF ST4_L C33 470nF ST1_L C34 470nF ST2_L C35 470nF D98AU882 ST3_L C36 470nF 31/34 Package information 7 TDA7437N Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. LQFP44 (10x10) Mechanical data and package dimensions DIM. mm MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.60 0.0630 0.15 0.0020 0.0059 A1 0.05 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 D 11.80 12.00 12.20 0.4646 0.4724 0.4803 D1 9.80 10.00 10.20 0.3858 0.3937 0.4016 D2 2.00 D3 0.20 0.0035 0.0079 0.0787 8.00 0.3150 E 11.80 12.00 12.20 0.4646 0.4724 0.4803 E1 9.80 10.00 10.20 0.3858 0.3937 0.4016 E2 2.00 0.0787 E3 8.00 e 0.80 L L1 K ccc 0.45 OUTLINE AND MECHANICAL DATA 0.60 0.3150 0.0315 0.75 0.0177 1.00 0.0295 0.0394 3.5˚(min.),7˚(max.) 0.10 0.0039 Note: 1. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D2” and “E2” dimensions for each device application. LQFP44 (10 x 10 x 1.40mm) Exposed Pad Down 7278839 C 32/34 TDA7437N 8 Revision history Revision history Table 14. Document revision history Date Revision Changes 24-Jan-06 1 Initial release. 01-Dec-06 2 Package changed, layout change, text modifications. 33/34 TDA7437N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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