TDA7502 In-car remote amplifier DSP Features ■ 24-Bit fixed-point dsp core delivering up to 50 MIPS ■ 2 x 1024 x 24 Bit of RAM for X and Y data memory. ■ 3072 x 24 Bit of RAM for program also usable for delay ■ Serial audio interface. ■ Debug port. ■ Control interface for external GPIOs, interrupts, and reset. ■ SPI and I2C for communication between external micro and DSP. Both master and slave operating modes. ■ PLL clock oscillator ■ 5V-tolerant 3.3V I/O interface LQFP44 (10x 10x 1.4mm) Description This device is a high-performance, fully programmable DSP, suitable for a wide range of applications and particularly for audio and sound processing. It contains a 24-bit 50 MIPS DSP core, several interfaces for control and data, plus a configurable PLL. The computational power and the memory configuration make this device particularly suitable for in car equalisation. This device will offer the best trade-off between performance and cost when coupled with the TDA7535, or other devices of the same family. A library of sound processing functions is available for this device; some of these functions are: parametric equaliser, cross over filters, acoustic delay, dynamic compression, vol/bass/treble/fader, active equalisation, Stereo spatial enhancement and more. Order codes Part numbers Package Packing TDA7502 LQFP44 (10x 10x 1.4mm) Tube TDA7502013TR LQFP44 (10x 10x 1.4mm) Tape and Reel November 2006 Rev 11 1/25 www.st.com 1 Contents TDA7502 Contents 1 Block diagram and PIN description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 SAI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 24-BIT DSP core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Data and program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 1024 x 24-Bit X-RAM (XRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 1024 x 24 Bit Y-RAM (YRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 3072 X 24-Bit Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 512 x 24-Bit Bootstrap ROM (Boot ROM) . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.5 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.6 Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.7 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.8 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.9 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 TDA7502 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Low voltage TTL interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Casper IC boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3/25 List of figures TDA7502 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. 4/25 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum DSP clock frequency (Fdsp) versus junction temperature (Tj). . . . . . . . . . . . . . 10 SAI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port acknowledge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port data I/O to status timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 15 Definition of timing for the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic for TDA7502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block diagram of car amplifier audio sub-system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TQFP44 (10x10) mechanical data & package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 23 TDA7502 Block diagram and PIN description Figure 1. Block diagram SDI0 SDI1 SDI2 SDO0 SDO1 SDO2 VDD3 GND3 SCANEN TESTEN VDD4 GND4 LRCLKT SCKT LRCLKR XAB SERIAL AUDIO INTERFACE 1024 x 24 X-RAM XDB YAB SCL SDA VDD5 GND5 SCKR 1024 x 24 Y-RAM YDB I2C INTERFACE VDD6 GND6 PAB SS SCK PDB SPI INTERFACE 3072 x 24 P/DELAY-RAM MISO 128 x 24 BOOT-ROM MOSI GPIO3 GPIO4 GPIO RESET ORPHEUS 24bit DSP CORE GPIO5 DBRQN/GPIO3 VDD1 GND1 INT PLL OSCILLATOR VDD2 GND2 XTO PVCC PGND XTI CLKOUT D99AU1034 MOSI SS SCK SDA SCL 42 MISO 43 GND6 GPIO3 44 VDD6 GPIO4 Pin connection (Top view) 41 40 39 38 37 36 35 34 4 30 VDD5 TESTEN 5 29 SDO2 DBRQN 6 28 SDO1 DBOUT 7 27 SDO0 VDD2 8 26 GND4 GND2 9 25 VDD4 DBCK 10 24 SCKR DBIN 11 23 LRCKR 12 13 14 15 16 17 18 19 20 21 22 SDI2 GND5 SCANEN SDI1 31 SDI0 3 GND3 LRCKT INT VDD3 32 RESET SCKT GND1 XTI 33 2 XTO VDD1 1 PVCC Figure 2. DBRQ GPIO5 DBIN/GPIO2 DEBUG INTERFACE PGND DBCK/GPIO1 CLKOUT 1 Block diagram and PIN description D99AU1035 5/25 Block diagram and PIN description Table 1. Pin description N. Name Type Reset status 1 VDD1 P – 3.3V core supply. 2 GND1 G – Core ground. 3 INT I/O – External interrupt line (Input/Output). When this line is asserted low, the DSP may be interrupted. Acts as IRQA line of DSP core. 4 SCANEN I – SCAN enable when active with TESTEN also active, controls theshifting of the internal scan chains. 5 TESTEN I – Test enable when active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting 6 DBRQN I – Debug port request Input. A means of entering the Debug mode of operation. 7 DBOUT/GPIO2 I/O I The serial data output for the Debug port. Can also be used as a GPIO. 8 VDD2 I – 3.3V core supply. 9 GND2 I – Core ground. I Debug port Bit Clock/Chip status 1. The serial clock for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO 10 6/25 TDA7502 DBCK/GPIO0 I/O Function 11 DBIN/GPIO1 I/O I Debug port Serial Input/Chip status 0. The serial data input for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO. 12 CLKOUT O – Output clock. 13 PGND G – PLL clock ground Input. Ground connection for oscillator circuit. 14 PVCC P – PLL clock power supply. Positive supply for PLL clock oscillator. 15 XTO (1) O High Crystal oscillator output. Crystal oscillator output drive. 16 XTI (1) I – Crystal oscillator input. External clock input or crystal connection. 17 RESET I/O I System reset. A logic low level applied to RESET input initializes DSPs. During debug mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset. 18 VDD3 P – 3.3V supply. 19 GND3 G – Ground. 20 SDI0 I – SDI0 is a stereo digital audio data input pin channel 0. 21 SDI1 I – SDI1 is a stereo digital audio data input pin channel 1. 22 SDI2 I – SDI2 is a stereo digital audio data input pin channel 2. TDA7502 Block diagram and PIN description Table 1. Pin description (continued) N. Name Type Reset status 23 LRCKR I/O – Left-right clock for SAI Receiver. Master or slave. 24 SCKR I/O – SAI receive bit clock. Master or slave. 25 VDD4 P – 3.3V supply. 26 GND4 G – Ground. 27 SDO0 O High SDO0 is a stereo digital audio data output pin channel 0. 28 SDO1 O High SDO1 is a stereo digital audio data output pin channel 1. 29 SDO2 O High SDO2 is a stereo digital audio data pin channel 2. 30 VDD5 P – 3.3V supply. 31 GND5 G – Ground. 32 LRCKT I/O – SAI transmit left/right clock. Master or slave. 33 SCKT I/O – SAI transmit bit clock. Master or slave. 34 SCL I/O – Clock line for I2C bus. Schmitt trigger input. 35 SDA I/O – Data line for I2C bus. Schmitt trigger input. 36 SCK I – Bit clock for SPI control interface. 37 SS I – Slave select input pin for SPI control interface. 38 MOSI I/O – Serial data output for SPI type serial port when in SPI master mode and serial data input when in SPI slave mode. 39 MISO I/O – Serial data input for SPI style serial port when in SPI master mode and serial data output when in SPI slave mode. 40 VDD6 P – 3.3V supply. 41 GND6 G – Ground. 42 GPIO3 I/O – This pin is dedicated as general I/O. 43 GPIO4 I/O – This pin is dedicated as general I/O. 44 GPIO5 I/O – This pin is dedicated as general I/O. Function 1. XTI and XTO are not 5V tolerant 7/25 Electrical specifications 2 TDA7502 Electrical specifications Table 2. Absolute maximum ratings Symbol Parameter Vdd DC supply voltage Vin Digital input voltage (XTI and XTO only) Value Unit -0.5 to 4.6 V -0.5 to (VDD +0.5) V 6.5 V (1) Vin Digital input voltage Tj Operating junction temperature range -40 to 125 °C Storage temperature -55 to 150 °C Tstg 1. When the IC is powered. Warning: Table 3. Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Thermal data Symbol Parameter Value Unit 68 °C/W Rth j-amb (1) Thermal resistance junction to ambient 1. In still air. Table 4. Recommended DC operating conditions Symbol Vdd Table 5. Parameter 3.3V power supply voltage Parameter Maximum current Note: 50MHz internal DSP clock Table 6. Pll characteristics Symbol Parameter Lock time Fvco (1) VCO frequency (2) 1. Depending on VCO output frequency. 2. Fdsp = Fvco/2 when PLL is running 8/25 Min. Typ. Max. Unit 3.15 3.3 3.45 V Min. Typ. Max. Unit 250 mA Max. Unit 3 ms 140 MHz Current consumption Symbol Idd Test condition Test condition @3.3V and Tj =125°C Test condition Min. @3.3V and Tj = 125°C 70 Typ. TDA7502 Table 7. Electrical specifications Oscillator characteristics Symbol Fosc Table 8. Parameter Max oscillator frequency (XTI) Test condition Min. @ 3.3V and Tj = 125°C 8 Typ. Max. Unit 12.5 MHz Max. Unit General interface electrical characteristics Symbol Parameter Test Condition Min. Typ. lil Low level input current without pullup device Vi = 0V (1) 1 μA lih High level input current without pullup device Vi = Vdd (1) 1 μA Ioz Tri-state output leakage without pull up/down device Vo = 0V or Vdd (1) 1 μA 5V tolerant tri-state output leakage without pull up/down device Vo = 0V or Vdd (1) 1 μA 3 μA I/O latch-up current V < 0V, V > Vdd IozFT Ilatchup Vesd Electrostatic protection Vo = 5.5V Leakage , 1μA 1 (2) 200 mA 1500 V 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, ia amaximum that can occur after an electrostatic stress on the pin. 2. Human body model. Table 9. Symbol Low voltage TTL interface DC electrical characteristics Parameter Test condition Min. Typ. Max. Unit 0.8 V Vil Low level input voltage (1) Vih High level input voltage (1) 2 Low level threshold input falling (1) 0.9 1.35 V Low level threshold input falling (1) 1.3 1.9 V Vhyst Schmitt trigger hysteresis (1) 0.4 0.7 V Vol Low level output voltage 0.4 V Voh High level output voltage Vilhyst Vihhyst Iol = XmA (1) (2) (3) V 2.4 V 1. TTL specifications only apply to the supply voltage range Vdd = 3.0V to 3.6V. 2. Takes into account 200mV voltage drop in both supply lines. 3. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Table 10. Symbol Fdsp DSP core Parameter Maximum DSP clock frequency Test condition @3.15V and Tj = 125°C Min. 50 Typ. Max. Unit MHz 9/25 Electrical specifications Figure 3. TDA7502 Maximum DSP clock frequency (Fdsp) versus junction temperature (Tj) MHz 92 Vdd = 3.3V 80 67 50 -40 25 125 Temp MHz 88 Vdd = 3.15V 78 65 50 -40 25 125 Temp MHz 93 Vdd = 3.45V 83 69 50 -40 10/25 25 125 Temp TDA7502 3 SAI interface SAI interface Figure 4. SAI timings SDI0-3 VALID LRCKR VALID tlrh SCKR (RCKP=0) tsckpl tsckph tlrs tdt tsdih tsdis tsckr Table 11. Cycles Timing tsckr D02AU1357 Description Minimum Clock Cycle Value Unit 4TDSP ns tdt SCKR active edge to data out valid 10 ns tlrs LRCK setup time 5 ns tlrh LRCK hold time 5 ns tsdid SDI setup time 15 ns tsdih SDI hold time 15 ns tsckph Minimum SCK high time 0.35 tsckr ns tsckpl Minimum SCK low time 0.35 tsckr ns Note: TDSP = dsp master clock cycle time = 1/FDSP Figure 5. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 LRCKR (#23) RIGHT LEFT SCKR (#24) SDI0,1,2 (#20, #21, #22) LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) D02AU1358 11/25 SAI interface TDA7502 Figure 6. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. LEFT LRCKR (#23) RIGHT SCKR (#24) SDI0,1,2 (#20, #21, #22) MSB(n-1) LSB(word n) LSB+1 (n) LSB+2 (n) D02AU1359 Figure 7. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. LEFT LRCKR (#23) RIGHT SCKR (#24) SDI0,1,2 (#20, #21, #22) LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) D02AU1360 Figure 8. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. LRCKR (#23) RIGHT LEFT SCKR (#24) SDI0,1,2 (#20, #21, #22) LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) D02AU1361 12/25 TDA7502 4 SPI interfaces SPI interfaces Table 12. SPI interfaces Symbol Description Min Value Unit 12TDSP ns 40 ns 16 ns Master tsclk Clock cycle tdtr Sclk edge to MOSI valid tmisosetup MISO setup time tmisohold MISO hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns tsclk Clock cycle 12TDSP ns tdtr Sclk edge to MOSI valid 40 ns tmosisetup MOSI setup time 16 ns tmosihold MOSI hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns Slave Figure 9. SPI clocking scheme. SS (#37) SCK (#36) (CPOL=0, CPHA=0) SCK (#36) (CPOL=0, CPHA=1) SCK (#36) (CPOL=1, CPHA=0) SCK (#36) (CPOL=1, CPHA=1) MSB 6 5 4 3 2 1 LSB MISO, MOSI (#38, #39) In master mode it is only supported CPHA = 0. INTERNAL STROBE FOR INTERNAL CAPTURE D02AU1362 13/25 SPI interfaces TDA7502 Table 13. Debug port interface dclk = 40MHz No. Characteristics Unit Min. Max. 1 DBCK rise time -- 3 ns 2 DBCK fall time -- 3 ns 3 DBCK low 40 -- ns 4 DBCK high 40 -- ns 5 DBCK cycle time 200 -- ns 6 DBRQN asserted to DBOUT (ACK) asserted 5 TDSP -- ns 7 DBCK high to DBOUT valid -- 42 ns 8 DBCK high to DBOUT invalid 3 -- ns 9 DBIN valid to DBCK low (set-up) 15 -- ns 10 DBCK low to DBIN invalid (hold) 3 -- ns 2 Tc -- ns DBOUT (ACK) assertion width 4.5 TDSP - 3 5 TDSP + 7 ns 11 Last DBCK low of read register to first DBCK high of next command 7 TDSP + 10 -- ns 12 Last DBCK low to DBOUT invalid (Hold) 3 -- ns DBOUT (ACK) asserted to first DBCK high DBSEL setup to DBCK TDSP ns Figure 10. Debug port serial clock timing. (1) (2) (3) DBCK (input) (4) (5) D02AU1363 Figure 11. Debug port acknowledge timing. DBRQN (input) (6) DBOUT (output) 14/25 D02AU1364 (ACK) TDA7502 SPI interfaces Figure 12. Debug port data I/O to status timing. DBCK (input) (Last) DBOUT (output) (9) (10) DBIN (input) (Note 1) D02AU1365 Note: 1 High Impedance, external pull-down resistor Figure 13. Debug port read timing. DBCK (input) (Last) (Note 1) (7) (8) (12) DBOUT (output) Note: 1 High Impedance, external pull-down resistor D02AU1369 Figure 14. Debug port DBCK next command after read register timing. DBCK (input) (NEXT COMMAND) (11) D02AU1370 15/25 I2C timing TDA7502 I2C timing 5 Figure 15. Definition of timing for the I2C bus. SDA tBUF tSU:STA tLOW tF SCL tR tHD:STA tHD:DAT tHIGH tSU:DAT tHD:STA tSU:STO D02AU1371 Table 14. Symbol Definitions Parameter Test condition Standard mode I2C bus Fast mode I2C bus Unit Min. Max. Min. Max. 0 100 0 400 kHz 4.7 – 1.3 – μs Hold time (repeated) START condition. tHD:STA After this period, the first clock pulse is generated 4.0 – 0.6 – μs tLOW LOW period of the SCL clock 4.7 – 1.3 – μs tHIGH HIGH period of the SCL clock 4.0 – 0.6 – μs Set-up time for a repeated start condition 4.7 – 0.6 – μs 0 – 0 0.9 μs FSCL SCLl clock frequency tBUF Bus free between a STOP and Start Condition tSU:STA tHD:DAT DATA hold time tR Rise time of both SDA and SCL signals Cb in pF – 1000 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals Cb in pF – 300 20+0.1Cb 300 ns 4 – 0.6 – μs 250 -- -- 100 ns – 400 – 400 pF tSU;STO Set-up time for STOP condition tSU:DAT Cb 16/25 Data set-up time Capacitive load for each bus line TDA7502 6 Functional description Functional description The TDA7502 contains one DSP core and associated peripherals. 6.1 24-BIT DSP core. The DSP core is used to process the converted analog audio data coming from the CODEC chip via the SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP. Some capabilities of the DSPs are listed below: Single cycle multiply and accumulate with convergent rounding and condition code generation ● 2 x 56-bit accumulators. ● Double precision multiply. ● Scaling and saturation arithmetic. ● 48-bit or 2 x 24-bit parallel moves. ● 64 interrupt vector locations. ● Fast or long interrupts possible. ● Programmable interrupt priorities and masking. ● 8 each of address registers, address offset registers and address modulo registers. ● linear, reverse carry, multiple buffer modulo, multiple wrap-around modulo address arithmetic. ● Post-increment or decrement by 1 or by offset, index by offset, predecrement address. ● Repeat instruction and zero overhead DO loops. ● Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines. ● Bit manipulation instructions possible on all registers and memory locations. Also jump on bit test.. ● 4 pin serial debug interface. ● Debug access to all internal registers, buses and memory locations. ● 5 word deep program address history FIFO. ● Hardware and software breakpoints for both program and data memory accesses. ● Debug single stepping, Instruction injection and disassembly of program memory. 17/25 Functional description 6.2 TDA7502 DSP peripherals There are a number of peripherals that are tightly coupled to the DSP Core. Each of the peripherals are listed below and described in the following sections. 6.3 ● 1024 x 24-Bit X-RAM. ● 1024 x 24-Bit Y-RAM. ● 3072 x 24-Bit program RAM. ● 512 x 24-Bit Boot ROM. ● Serial audio interface (SAI). ● Programmable control interface (SPI/I2C). ● GPIO. ● PLL clock oscillator. Data and program memory Each of the memories are described below. 6.3.1 1024 x 24-Bit X-RAM (XRAM) This is a 1024 x 24-Bit single port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the address generation unit of the DSP core. The 24Bit XRAM Data, XDBx(23:0), may be written to and read from the data ALU of the DSP core. The XDBx Bus is also connected to the internal bus switch so that it can be routed to and from all peripheral blocks. 6.3.2 1024 x 24 Bit Y-RAM (YRAM) This is a 1024 x 24-Bit single port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the address generation unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. The YDBx Bus is also connected to the internal bus switch so that it can be routed to and from other blocks. 6.3.3 3072 X 24-Bit Program RAM This is a 3072 x 24-Bit single port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the program address generator of the DSP core for instruction fetching, and by the AGU in the case of the move program memory (MOVEM) instruction. The 24-Bit PRAM Data (program code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx bus is routed to the program decode controller of the DSP core for instruction decoding. Spare space in the program area may be used as data memory to implement delay lines for example. 6.3.4 512 x 24-Bit Bootstrap ROM (Boot ROM) This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the DSP. 18/25 TDA7502 Functional description Essentially this consists of a routine that is called when the DSP comes out of reset. There are four different boot modes supported by the boot ROM. The first mode loads the application program via SPI interface where Casper’s SPI is in master mode. The second boot mode enables the debug port and waits. The third and fourth modes load the application program via the I2C interface, one with Casper’s I2C Interface configured in slave mode and the other in master mode. Which boot mode to enter is configured by sampling the states of the GPIO4 and GPIO3 pins at reset as shown in the table below. Table 15. Casper IC boot modes Modes 0-SPI Master 1-Debug 2-I 2C 3-I 6.3.5 Master 2C Slave Description GPIO3 GPIO4 load PRAM, XRAM and YRAM from SPI 0 0 enable Debug Port 0 1 load PRAM, XRAM and YRAM from I2C 1 0 oad PRAM, XRAM and YRAM from I2C 1 1 Serial audio interface (SAI) The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface. The features of the SAI are listed below. 6.3.6 ● Three synchronized stereo data transmission lines ● Three synchronized stereo data reception lines ● Master/Slave operating modes ● Transmit and receive interrupt logic triggers on left/right data pairs ● Receive and transmit data registers have two locations to hold left and right data. Serial peripheral interface A serial interface allows to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. Both master and slave modes are supported. In master mode the SPI supports combination of CPOL =0/1 and CPHA =0 only, while in slave mode all the 4 possible combinations of CPOL and CPHA are supported. See Figure 9. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin.The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. 6.3.7 I2C interface The inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. 19/25 Functional description TDA7502 Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. 6.3.8 General purpose input/output The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP's peripherals. 6.3.9 PLL clock oscillator The PLL clock oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 2 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the phase detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0). 20/25 15pF DEBUG INTERFACE 10K 3V3_3 μP PGND DGND_3 1 10K GND3 VDD3 RESET XTI XTO PVCC PGND CLKOUT GND2 DBIN DBCK DBOUT DBRON 19 18 17 16 15 14 13 12 9 11 10 7 6 20 NOT USED PINS TO BE CONNECTED TO GROUND PGND 2.2M 15pF 24M576Hz 3V3_P CLK-OUT FROM PLL 2 DGND_2 GPI/O 10K SDI0 10K 21 SDI1 8 22 SDI2 3V3_2 3 4 23 2 24 SCKR VDD2 LRCKR GND1 25 5 1 26 28 VDD1 SAI INTERFACE MASTER/SLAVE 3V3_4 DGND_4 27 TDA7502 TESTEN GND4 SCANEN SDO0 INT VDD4 10K SDO1 3V3_1 29 SDO2 DGND_1 41 30 GND6 31 3V3_4 DGND_4 40 32 VDD6 DGND_6 3V3_6 VDD5 μP CONFIGURING THE PINS TO J1 OF THE CONNECTOR AS DESCRIBED IN THE FIGURE YOU CAN USE THE PC_INTERFACE AND THEN DOWNLOAD DSP SW PROGRAM INTO EEPROM OR DIRECTLY INTO THE CHIP MEMORY. GND5 THE HW INSIDE DASHED LINE BOX IS A POSSIBLE SOLUTION TO BOOT STRAP AND TO INTERFACE TP A PC. LRCKT 33 34 35 37 36 38 39 44 42 43 BOOT MODE SELECTION SCL SDA SS SCK MOSI MISO 3 D02AU1383 I2C/SPI INTERFACE 10K GPIO3 GPIO5 10K 2 GPIO4 1 1 WC SDA SCL 47R 2 3 6 8 10 5 7 9 SDA READY 8 4 5 32 x 8 I2C 1,2,3 6 7 VSS VCC 1 DGND_6 DGND_6 3V3_6 0.1μF DGND_6 N.C. 4 3 SCK/EN M24256-WMW6 2 1 10K J1 1 I2C-SLAVE 3V3_6 1 I2C-MASTER 10K 1 0 DEBUG-MODE 0 0 0 SPI-MASTER GPIO3 GPIO4 BOOT MODE SELECTION 5V 47R GPI/0 3V3_6 DGND_6 3V3_6 DGND_6 7 SCKT TDA7502 Application scheme Application scheme Figure 16. Application schematic for TDA7502 21/25 Application scheme TDA7502 Figure 17. Block diagram of car amplifier audio sub-system. EPROM (64Kx8) To Microprocessor Control Bus POWER AMPLIFIER DIGITAL AUDIO TDA7502 TDA7535 D99AU1036 22/25 TDA7502 8 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. TQFP44 (10x10) mechanical data & package dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.60 0.05 A2 1.35 1.40 1.45 0.053 0.055 B 0.30 0.37 0.45 0.012 0.015 C 0.09 0.20 0.004 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 0.002 8.00 0.006 11.80 12.00 12.20 0.464 E1 9.80 10.00 0.472 0.480 0.394 0.401 10.20 0.386 0.472 0.480 0.394 0.401 8.00 0.315 e 0.80 0.031 k ccc 0.45 0.60 0.018 0.008 E3 L 0.057 0.315 E L1 OUTLINE AND MECHANICAL DATA 0.063 A1 D3 0.15 MAX. 0.75 1.00 0.018 0.024 0.030 0.039 LQFP44 (10 x 10 x 1.4mm) 0˚(min.), 3.5˚(typ.), 7˚(max.) 0.10 0.0039 0076922 E 23/25 Revision history 9 TDA7502 Revision history Table 16. 24/25 Revision history Date Revision Description of changes January 2004 8 First Issue in EDOCS dms. September 2004 9 Changed the style-sheet look. Cancelled the “Package Marking” information. March 2005 10 Changed SPI interface description and Figure 4. 24-Nov-2006 11 Package changed, layout changes, text modifications. TDA7502 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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