STMICROELECTRONICS TDA7505

TDA7505
Car radio DSP for advanced signal processing
Features
■
Full software flexibility with two 24x24 bit DSP
cores
■
FM processing
■
AM processing
■
Dolby B noise reduction
■
MP3 and C3 decoding
■
Echo AND noise cancellation
■
Audio processor
■
Special sound effect processor
■
Dual media processing
■
RDS Filter, Demodulator & Decoder
■
4 + 1 channel ADC, 6 channel DAC CODEC
■
IIC/SPI control busses
■
SAI 6 channel serial audio interface
■
SPDIF interface with sample rate converter
■
Dual core external memory interface
■
Debug interface
■
On-chip PLL
Table 1.
LQFP100
(14x14x1.4mm)
■
5V-tolerant 3V I/O interface
■
Multifunction general purpose I/O ports
Description
The TDA7505 is an MPX-sampling DSP for car
radio applications.
Device summary
Order code
Package
Packing
TDA7505
LQFP100
Tray
October 2007
Rev 1
1/38
www.st.com
1
Contents
TDA7505
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
2/38
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1
Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.2
Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.3
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.4
General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17
4.3.5
High voltage CMOS interface DC electrical characteristics . . . . . . . . . . 17
4.3.6
DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
SAI interface timing - receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5
SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8
SPI interfaces (Buffered SPI, Display SPI, RDS SPI) . . . . . . . . . . . . . . . 20
4.9
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10
DRAM/SRAM interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.11
Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
24-bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1
Data and program memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.4
Sony/Philips digital interface (S/PDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.5
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TDA7505
6
Contents
5.2.6
DRAM/SRAM interface (DEMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.7
Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.8
General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.9
Asynchronous sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.10
SINCOS co-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.11
PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.12
CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.13
Radio data system (RDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.14
Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Software features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
AM/FM base band signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
Generic audio signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3
TAPE signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4
CD signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5
Audiophile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6
Audio decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.7
Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.8
Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of tables
TDA7505
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/38
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DRAM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DRAM refresh period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fractional-N PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz . . . . . . . . . . . . . 25
ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz . . . . . . . . . . . . . 25
ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz . . . . . . . . . . . . 25
Level ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DAC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FM stereo decoder (SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Examples of convenient clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Example of possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TDA7505
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LQFP100 pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Debug port acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Debug port data I/O to status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Debug port read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP100 (14x14x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . 36
5/38
Overview
1
TDA7505
Overview
The TDA7505 integrates two 75 MIPS DSP cores. One core is used for stereo decoding,
noise blanking, weak signal processing, Dolby B, music search and MP3 decoding. The
second core is used for audio and sound processing and Echo & Noise cancellation. All
functions are realized in SW and thus are flexible on customer request.
The device may be controlled by a main micro through either SPI or I2C interface. Through
the same pins, but with separate device address (I2C) respectively separate chip select line
(SPI) the main micro may communicate with the DSP or with the RDS block.
An additional SPI is available allowing a separate communication (e.g. to a display micro).
The DSP cores are integrated with their associated data and program memories.
DSP0 is declared as master. Its associated peripherals and interfaces are: I2C, SPI1
(Master SPI), SPI2 (Display SPI), Serial Audio Interface (SAI), PLL Oscillator, External
Memory Interface (EMI), General Purpose I/O ports (DSP0 GPIO[0..11]), RDS filter and D/A
converters.
DSP1 is declared as Co-DSP. Its associated peripherals and interfaces are: A/D converters,
SPDIF, Sample Rate Converter (SRC) and General Purpose I/O ports (DSP1 GPIO[0..11]).
Both DSP´s are identical (ST Orpheus core, 75 MHz clock). Only the peripherals and
memory configurations are different. The internal communication takes place through a bidirectional 24/10-word exchange interface (XCHG) with complex flag and interrupts
capability.
The Radio Data System (RDS, respectively RBDS) function is realized via dedicated
hardware. It may run fully autonomous without SW intervention. Thus an efficient
background mode as well as a low current standby mode is possible. The RDS input is
connected to the A/D converter to receive the FM multiplex signal (MPX) automatically. Its
output may be configured to I2C or SPI format. The pins are shared with the I2C and SPI1 of
DSP0.
The device is equipped with a debug and test interface. It allows the SW development with a
100% compatible emulation system.
All functions, except RDS, are implemented in SW. Thus, the device may be adapted to
customers´ requirements. This implies the variable implementation of SW modules
developed by the customer, ST and third parties. This flexibility also allows the usage for
applications others than car radios, e.g.: Boosters.
6/38
TDA7505
Block diagram
2
Block diagram
Figure 1.
Block diagram
analog audio in
Navi.
CD
CC
Tel.
2
4
2
Qdiff.
AM/FM Mpx
AM/FMLevel
Mpx RDS
2
3
Diff. Diff.
Qdiff.
analog audio out
Input Source Selector
PLL Clock
Generator
ADC-ref
ΣΔ
ADCVDD
ADCGND
AVDD
AGND
CLK in
8.55MHz
ΣΔ
Decimation
Audio
ΣΔ
ΣΔ
Decimation
FM/Audio
AM/FM
level
ADC
SPDIF audio in
SC
Filter
RDS
Filter
SC
Filter
SC
Filter
DSP1 Orpheus Core
Including 12 GPIO´s
10 word SPI 1
receive stack
AM processing,
FM processing,
CD compression,
Dolby B,
MP3
Debug Interface
2ch sample
rate converter
X Ram 4096
X Rom 4096
Y Ram 40969
P Ram 4096
P Rom 16384
DACVDD
Oversampl.
Filter
Grp & blk
sync., error
correction
Demod.
DAC-ref
DACGND
RDS Int.
SPI/
IIC
RDSCS
4
Crystal
Oscillator
SPDIF 2ch.
Interface
SC
Filter
Noise
Shaper
Oversampl.
Filter
SINCOS
SAI 6ch.
Receiver
SC
Filter
Noise
Shaper
Noise
Shaper
Oversampl.
Filter
6 Ch. Audio Bus
2
receive bit&word clk
digital audio in
SC
Filter
IIC / SPI 1
SPI 2
External Memory Interface
4
SAI Transmitter
3
2
SRAM 4Mx8
DRAM 64Mx4
8+3
17
Xchg
Interface
X Ram 4096
Y Ram 4096
P Ram 4096
P Rom 16384
Audio processing,
Sound processing,
TAM,
Echo & noise cancell.
Debug Interface
Display μP
6 Channel
Audio Bus
INT
DSP0 Orpheus Core
Including 12 GPIO´s
μP control
NRESET
4
4
VDD
GND
Debug/Test
5
7/38
Pin description
TDA7505
3
Pin description
Table 2.
Pin description
N°
Name
Type
1
DAC4
A
Signal output D/A converter (single ended)
2
DAC5
A
Signal output D/A converter (single ended)
N°
Name
Type
Voltage
3
VDD1V8_1
S
1.8V
Digital Supply dedicated to internal logic
4
GND1V8_1
S
0V
Digital Ground dedicated to internal logic
N°
Name
Type
5
NRESET
6
SRCCD
MISOD output
MISOD input
7
SRCMD
MOSID input
MOSID output
DSP0 GPIO0
DSP0 GPIO0
8
SSD input
INT
DSP0 GPIO1
DSP0 GPIO1
9
CLKIN
SCKD input
SCKD output
N°
I/O
Reset
Function
After boot with
I/O
state
SPI
I2C *
EMI
E0
E1
E1
E1
Z
Z
Z
Z
I/O
Z
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Function
Input 5VT
System Reset. A low level
applied to NRESET input
initializes the IC.
Input 5VT
Output 2mA PP/OD
Input 5VT
SPDIF input source 1 (e.g.: CD)
Display SPI SO (slave mode)
Display SPI MI (master mode)
Input 5VT
Input 5VT
Output 2mA PP
Input 5VT
Output 2mA PP
SPDIF input source 2 (e.g.: MD)
Display SPI SI (slave mode)
Display SPI MO (master mode)
GPIO input
GPIO output
Input 5VT
Input 5VT
Input 5VT
Output 2mA PP
Display SPI SS slave select
DSP0 external interrupt (IRQA)
GPIO input
GPIO output
Input 5VT
Input 5VT
Output 2mA PP
External clock input for PLL
Display SPI clock (slave mode)
Display SPI clock (master mode)
Type
Voltage
10 AVDD
S
3.3V
11 XTI
A
AC
Crystal oscillator input
12 XTO
A
AC
Crystal oscillator output
13 AGND
S
0V
Ground dedicated to the PLL
8/38
Name
I
Function
Function
Supply dedicated to the PLL
TDA7505
Table 2.
N°
Pin description
Pin description (continued)
Name
RDSCS
14
DSP0 GPIO2
DSP0 GPIO2
INT
15 RDSINT
DSP0 GPIO3
DSP0 GPIO3
N°
Name
Type
I/O
Reset
State
Z
After boot with
I2C *
SPI
Z
Z
I/O
Z
I/O
Z
Z
Z
Function
EMI
Z
Input 5VT
Output 2mA OD
Input 5VT
Output 2mA PP
RDS SPI CS chip select in
RDS bit data
GPIO input
GPIO output
Input 5VT
Output 2mA OD
Output 2mA PP
Input 5VT
Output 2mA PP
DSP0 external interrupt (IRQA)
RDS bit clock
RDS Interrupt Output
GPIO input
GPIO output
Type
Voltage
16 VDD3V3_1
S
3.3V
Digital supply dedicated to I/O structures
17 GND3V3_1
S
0V
Digital ground dedicated to I/O structures
SCKM input
SCKM output
18 SCL bi-direct
DSP0 GPIO4
DSP0 GPIO4
N°
Name
MISOM output
MISOM input
19 ADDR select
DSP0 GPIO5
DSP0 GPIO5
I/O
0/1
Z
Z
Type
Reset
state
I/O
Z
SPI
0/1
I/O
SSM input
21 DSP0 GPIO7
DSP0 GPIO7
I/O
Z
22
DSRA<0>
DSRA<0>
I/O
0
23
DSRA<1>
DSRA<1>
I/O
24
DSRA<2>
DSRA<2>
I/O
Input 5VT
Output 2mA PP
In 5VT/Out 2mA OD
Input 5VT
Output 2mA PP
Master/RDS SPI clock (slave m.)
Master SPI clock (master mode)
I2C clock
GPIO input
GPIO output
I/O
Function
After boot with
I2C *
EMI
Z
Z
MOSIM input
MOSIM output
20 SDA bi-direct
DSP0 GPIO6
DSP0 GPIO6
Function
Z
0/1
Z
Z
Z
Z
Output 2mA PP/OD
Input 5VT
Input 5VT
Input 5VT
Output 2mA PP
Master/RDS SPI SO (slave m.)
Master SPI MI (master mode)
I2C Address select line
GPIO input
GPIO output
Input 5VT
Output 2mA PP
In 5VT/Out 2mA OD
Input 5VT
Output 2mA PP
Master/RDS SPI SI (slave m.)
Master SPI MO (master mode)
I2C data
GPIO input
GPIO output
Z
Z
Input 5VT
Input 5VT
Output 2mA PP
Master SPI SS slave select
GPIO input
GPIO output
1
1
Z
In/Out 2mA PP
In/Out 2mA PP
EMI SRAM Data 0
EMI DRAM Data 0
0
1
1
Z
In/Out 2mA PP
In/Out 2mA PP
EMI SRAM Data 1
EMI DRAM Data 1
0
1
1
Z
In/Out 2mA PP
In/Out 2mA PP
EMI SRAM Data 2
EMI DRAM Data 2
9/38
Pin description
Table 2.
N°
TDA7505
Pin description (continued)
Name
Type
Reset
After boot with
I/O
state
SPI
I2C *
EMI
Function
DSRA<3>
DSRA<3>
I/O
0
1
1
Z
In/Out 2mA PP
In/Out 2mA PP
EMI SRAM Data 3
EMI DRAM Data 3
26 DSRA<4>
I/O
0
1
1
Z
In/Out 2mA PP
EMI SRAM Data 4
27 DSRA<5>
I/O
0
1
1
Z
In/Out 2mA PP
EMI SRAM Data 5
28 DSRA<6>
I/O
0
1
1
Z
In/Out 2mA PP
EMI SRAM Data 6
29 DSRA<7>
I/O
0
1
1
Z
In/Out 2mA PP
EMI SRAM Data 7
25
30
SRA<0>
SRA<0>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 0
EMI DRAM Address 0
31
SRA<1>
SRA<1>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 1
EMI DRAM Address 1
N°
Name
Type
Voltage
32 VDD3V3_2
S
3.3V
Digital Supply dedicated to I/O structures
33 GND3V3_2
S
0V
Digital Ground dedicated to I/O structures
N°
Name
Type
Reset
Function
After boot with
I/O
state
SPI
I2C *
EMI
Function
34
SRA<2>
SRA<2>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 2
EMI DRAM Address 2
35
SRA<3>
SRA<3>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 3
EMI DRAM Address 3
36
SRA<4>
SRA<4>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 4
EMI DRAM Address 4
37
SRA<5>
SRA<5>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 5
EMI DRAM Address 5
38
SRA<6>
SRA<6>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 6
EMI DRAM Address 6
39
SRA<7>
SRA<7>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 7
EMI DRAM Address 7
40
SRA<8>
SRA<8>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 8
EMI DRAM Address 8
N°
Name
Type
Reset
After boot with
I/O
state
SPI
I2C *
EMI
Function
41
SRA<9>
SRA<9>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 9
EMI DRAM Address 9
42
SRA<10>
SRA<10>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 10
EMI DRAM Address 10
10/38
TDA7505
Table 2.
N°
Pin description
Pin description (continued)
Name
Type
Reset
After boot with
I/O
state
SPI
I2C *
EMI
Function
43
SRA<11>
SRA<11>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 11
EMI DRAM Address 11
44
SRA<12>
SRA<12>
O
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI SRAM Address 12
EMI DRAM Address 12
N°
Name
45 VDD1V8_2
46
GND1V8_2 &
GND3V3_3
47 VDD3V3_3
N°
Name
Type
Voltage
S
1.8V
S
0V
S
3.3V
Type
Reset
Function
Digital Supply dedicated to internal logic
Digital Ground dedicated to internal logic and I/O
structures
Digital Supply dedicated to I/O structures
After boot with
I/O
state
SPI
I2C *
EMI
Function
48 DRD
O
1
1
1
1
Output 2mA PP
EMI data read strobe
49 DWR
O
1
1
1
1
Output 2mA PP
EMI data write strobe
0
1
1
0/1
Output 2mA PP
Output 2mA PP
EMI DRAM CAS
EMI SRAM Address 13
CAS
SRA<13>
O
51 SRA<14>
O
0
1
1
0/1
Output 2mA PP
EMI SRAM Address 14
SRA<15>
52 DSP0 GPIO8
DSP0 GPIO8
I/O
Z
Z
Z
0/1
Output 2mA PP
Input 5VT
Output 2mA PP
EMI SRAM Address 15
GPIO input
GPIO output
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 16
GPIO input
GPIO output
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 17
GPIO input
GPIO output
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 18
GPIO input
GPIO output
50
INOUTA
SRA<16>
53
DSP1 GPIO0
DSP1 GPIO0
INOUTB
SRA<17>
54
DSP1 GPIO1
DSP1 GPIO1
INOUTC
SRA<18>
55
DSP1 GPIO2
DSP1 GPIO2
N°
Name
INOUTD
SRA<19>
56
DSP1 GPIO3
DSP1 GPIO3
I/O
I/O
I/O
Type
I/O
Z
Z
Z
Reset
state
Z
Z
Z
Z
Z
Z
0/1
0/1
0/1
After boot with
SPI
I2C *
I/O
0/1
Z
Z
Z
Function
EMI
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 19
GPIO input
GPIO output
11/38
Pin description
Table 2.
N°
TDA7505
Pin description (continued)
Name
INOUTE
SRA<20>
57
DSP1 GPIO4
DSP1 GPIO4
Type
I/O
I/O
INOUTG
59 DSP1 GPIO6
DSP1 GPIO6
INOUTH
60 DSP1 GPIO7
DSP1 GPIO7
I2C *
SPI
I/O
0/1
Z
Function
EMI
Z
0/1
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 20
GPIO input
GPIO output
In 5VT/Out 2mA PP
Output 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 21
EMI DRAM RAS
GPIO input
GPIO output
Z
Z
Z
I/O
Z
Z
Z
Z
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
GPIO input
GPIO output
I/O
Z
Z
Z
Z
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
GPIO input
GPIO output
Type
Voltage
61 VDD3V3_4
S
3.3V
Digital Supply dedicated to I/O structures
62 GND3V3_4
S
0V
Digital Ground dedicated to I/O structures
N°
Name
state
After boot with
Z
INOUTF
SRA<21>
58 RAS
DSP1 GPIO5
DSP1 GPIO5
N°
Reset
Name
Type
Reset
Function
After boot with
I/O
state
SPI
I2C *
EMI
Function
INOUTI
63 DSP1 GPIO8
DSP1 GPIO8
I/O
Z
Z
Z
Z
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
GPIO input
GPIO output
64 INOUTJ
I/O
Z
Z
Z
Z
In 5VT/Out 2mA PP
Multi function I/O
Input 5VT
Out 2mA PP
Input 5VT
Output 2mA PP
Debug clock
Chip status 1
GPIO input
GPIO output
Output 2mA PP
Input 5VT
Output 2mA PP
Debug output
GPIO input
GPIO output
DBCK
OS1
65
DSP0/1 GPIO9
DSP0/1 GPIO9
I/O
DBOUT
66 DSP0/1 GPIO10
DSP0/1 GPIO10
I/O
N°
Name
DBIN
OS0
67
DSP0/1 GPIO11
DSP0/1 GPIO11
12/38
Z
Type
Z
Reset
state
I/O
Z
0
0
0
1
1
1
After boot with
SPI
0
I2C *
0
I/O
Function
EMI
0
Input 5VT
Out 2mA PP
Input 5VT
Output 2mA PP
Debug input
Chip status 0
GPIO input
GPIO output
TDA7505
Pin description
Table 2.
N°
Pin description (continued)
Name
Type
Reset
After boot with
I/O
state
SPI
I2C *
EMI
Function
68 Debug/Test_Sel0
I
E1
E1
E1
E1
Input
Mode select (Debug0/1, Test)
69 Debug/Test_Sel1
I
E1
E1
E1
E1
Input
Mode select (Debug0/1, Test)
I/O
0
0
0
0
In 5VT/Out 2mA PP
Multi function I/O
70 INOUTK
N°
Type
Voltage
71 VDD1V8_3
S
1.8V
72 GNDSUB_D
S
0V
N°
Name
Name
Function
Digital Supply dedicated to internal logic
Digital substrate Ground
Type
Function
73 LEVEL_AM/FM
A
Signal input to level ADC (single ended)
74 MPX_AM+
A
Signal input tuner AM (quasi differential)
75 MPX_AM/FM-
A
Signal input tuner common ground (quasi differential)
76 MPX_FM+
A
Signal input tuner FM (quasi differential)
77 MPX_RDS
A
Signal input background tuner (for RDS) single ended
78 Navi-
A
Signal input from navigation system (differential)
79 Navi+
A
Signal input from navigation system (differential)
80 Phone-
A
Signal input from Telephone (differential)
81 Phone+
A
Signal input from Telephone (differential)
N°
Type
Voltage
82 ADCGND
S
0V
Analog Ground dedicated to the A/D converter
83 ADCVDD
S
3.3V
Analog Supply dedicated to the A/D converter
N°
Name
Name
Function
Type
Function
84 ADCREF3
A
ADC reference voltage decoupling
85 CD_R+
A
Signal right input from CD-changer (differential)
86 CD_R-
A
Signal right input from CD-changer (differential)
87 ADCREF2
A
ADC reference voltage decoupling
88 CD_L-
A
Signal left input from CD-changer (differential)
89 CD_L+
A
Signal left input from CD-changer (differential)
90 ADCREF1
A
ADC reference voltage decoupling
91 CC_R
A
Signal right input from cassette (single ended)
92 CC_L
A
Signal left input from cassette (single ended)
N°
Name
Type
Voltage
93 GNDSUB_A
S
0V
94 DACVDD
S
3.3V
Function
Analog substrate Ground
Analog Supply dedicated to the D/A converter.
13/38
Pin description
Table 2.
N°
Pin description (continued)
Name
95 DACREF
N°
Type
A
Name
96 DACGND
N°
TDA7505
Name
Function
DAC reference voltage decoupling
Type
Voltage
S
0V
Function
Analog Ground dedicated to the D/A converter.
Type
Function
97 DAC0
A
Signal output D/A converter (single ended)
98 DAC1
A
Signal output D/A converter (single ended)
99 DAC2
A
Signal output D/A converter (single ended)
100 DAC3
A
Signal output D/A converter (single ended)
Type:
S: Supply pin
0: logic low output
PP: push-pull
I: Digital Input pin
1: logic high output
OD: open drain
O: Digital Output pin
E0: logic low input
5VT: 5 volt tolerant
A: Analog pin
E1: logic high input
Schmitt-trigger on all inputs
Z: high impedance (Input mode of bi-directional pin)
*) I2C Master boot mode, using multiplexed debug interface (pin15: INT/RDSINT = 1, pin21: SSM = 0, pin52:
SRA15 = 0)
LQFP100 pins connection (top view)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
DAC3
DAC2
DAC1
DAC0
DACGND
DACREF
DACVDD
GNDSUB_A
CC_L
CC_R
ADCREF1
CD_L+
CD_LADCREF2
CD_RCD_R+
ADCREF3
ADCVDD
ADCGND
Phone+
PhoneNavi+
NaviMPX_RDS
MPX_FM+
Figure 2.
DSP0 GPIO0
DSP0 GPIO1
DSP0 GPIO2
DSP0 GPIO3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CODEC
SPDIF
DSPI
Debug/Test
PLL
RDS
Bootsel0
TDA7505
SAI/SPDIF
BSPI/I2C
Bootsel1
Bootsel2
EMI
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DSRA<4>
DSRA<5>
DSRA<6>
DSRA<7>
SRA<0>
SRA<1>
VDD3V3_2
GND3V3_2
SRA<2>
SRA<3>
SRA<4>
SRA<5>
SRA<6>
SRA<7>
SRA<8>
SRA<9>
SRA<10>
SRA<11>
SRA<12>
VDD1V8_2
GND1V8_2/GND3V3_3
VDD3V3_3
DRD
DWR
CAS/SRA<13>
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DSP0 GPIO4
DSP0 GPIO5
DSP0 GPIO6
DSP0 GPIO7
DAC4
DAC5
VDD1V8_1
GND1V8_1
NRESET
SRCCD/MISOD
SRCMD/MOSID
INT/SSD
CLKIN/SCKD
AVDD
XTI
XTO
AGND
RDSCS
INT/RDSINT
VDD3V3_1
GND3V3_1
SCL/SCKM
ADDR/MISOM
SDA/MOSIM
SSM
DSRA<0>
DSRA<1>
DSRA<2>
DSRA<3>
14/38
MPX_AM/FMMPX_AM+
LEVEL_AM/FM
GNDSUB_D
VDD1V8_3
INOUTK
Debug/Test_Sel1
Debug/Test_Sel0
DBIN_OS0
DSP0/1 GPIO11
DBOUT
DSP0/1 GPIO10
DBCK_OS1
DSP0/1 GPIO9
INOUTJ
DSP1 GPIO8
INOUTI
GND3V3_4
VDD3V3_4
DSP1 GPIO7
INOUTH
INOUTG
DSP1 GPIO6
INOUTF/SRA<21>/RAS DSP1 GPIO5
INOUTE/SRA<20>
DSP1 GPIO4
INOUTD/SRA<19>
DSP1 GPIO3
INOUTC/SRA<18>
DSP1 GPIO2
INOUTB/SRA<17>
DSP1 GPIO1
DSP1 GPIO0
INOUTA/SRA<16>
SRA<15>
DSP0 GPIO8
SRA<14>
TDA7505
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
VDD1V8
VDD3V3
AVDD
DACVDD
ADCVDD
Parameter
Power supplies digital
I/O
Analog
DAC
ADC
Analog input or output voltage
(2)
Digital input or output voltage, 5V tolerant
Normal
Fail-safe(3)
Value
Unit
-0.5 to +1.95
-0.5 to +3.6
-0.5 to +3.6(1)
-0.5 to +3.6(1)
-0.5 to +3.6(1)
V
V
V
V
V
-0.5 to (AVDD+0.5) (1)
V
-0.5 to 6.3
-0.5 to 3.8
V
V
Top
Operating temperature range
-40 to 85
°C
Tstg
Storage temperature
-55 to 150
°C
1. The maximum difference in the voltage of AVDD, DACVDD, ADCVDD, analog inputs and analog outputs
must not exceed 0.5V. Warning: Operation at or beyond these limits may result in permanent damage to
the device. Normal operation is not guaranteed at these extremes.
2. During Normal Mode operation VDD3 is always available as specified.
3. During Fail-save Mode operation VDD3 may be not available.
4.2
Thermal data
Table 4.
Symbol
Rth j-amb
Tj
Rth j-case
Thermal data
Parameter
Value
Unit
Thermal resistance junction to ambient (1)
55
°C/W
Operating junction temperature
125
°C
10
°C/W
Thermal junction to case
(2)
1. In still air
2. Measured on top side of the package
15/38
Electrical specifications
TDA7505
4.3
Electrical characteristics
4.3.1
Recommended DC operating conditions
Table 5.
Recommended DC operating conditions
Symbol
Parameter
VDD1V8
Digital supply voltage
1.7
1.8
1.9
V
VDD3V3
I/O supply voltage
3.15
3.3
3.49
V
Analog supply voltage
3.15
3.3
3.49
V
DACVDD
D/A supply voltage
3.15
3.3
3.49
V
ADCVDD
A/D supply voltage
3.15
3.3
3.49
V
Min.
Typ.
Max.
Unit
AVDD
Test condition
4.3.2
Power consumption
Table 6.
Power consumption
Symbol
Parameter
Test condition
Idd
Maximum current
Digital power supply @ 1.8V
Idio
Maximum current
IDAC
IADC
Min.
Typ.
Max.
Unit
195
mA
Digital IO power supply @ 3.3V
6
mA
Maximum current
DAC analog power supply @ 3.3V
22
mA
Maximum current
ADC analog power supply @ 3.3V
43
mA
Note: 75MHz internal DSP clock, all CODEC channels enabled at Tamb = 25 °C
4.3.3
Oscillator characteristics
Table 7.
Oscillator characteristics
Symbol
FOSC
FEXT
FCLKIN
Parameter
Test condition
Min.
Crystal oscillator frequency(1)
External oscillator frequency
External oscillator frequency
Typ.
Max.
8.55
Unit
MHz
connected through pin
XTI(1)
75
MHz
connected through pin
CLKIN(2)
80
MHz
1. RDS works only with 8.55Mhz quartz or alternative with 74.1MHz applied externally on XTI pin.
2. An alternative clock input (pin CLKIN) can be used for PLL to adjust the audio sampling rate. RDS can work in parallel with
the 8.55MHz quartz.
16/38
TDA7505
Electrical specifications
4.3.4
General interface electrical characteristics
Table 8.
General interface electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
lil
Low level input current without pull-up
Vi = 0V(1)
device
1
μA
lih
High level input current without pull-up
Vi = VDD3V3 (1)
device
1
μA
Ioz
Tri-state output leakage without pull
up/down device
Vo = 0V or VDD3V3(1)
1
μA
5V tolerant tri-state output leakage
without pull up/down device
Vo = 0V or VDD3V3(1)
1
μA
IozFT
7
μA
Ilatchup
Vesd
Vo = 5.5V
1
I/O latch-up current
Vi < 0V, Vi > VDD3V3
200
mA
Electrostatic protection
Leakage, 1μA (2)
2000
V
1. The leakage currents are generally very small, <1nA. The value given here, 1 A, is a maximum that can occur after an
electrostatic stress on the pin.
2. Human Body Model.
4.3.5
High voltage CMOS interface DC electrical characteristics
Table 9.
High voltage CMOS interface DC electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.3*VDD3V3
V
Vil
Low Level Input Voltage
3.0V<VDD3V3<3.6V
Vih
High Level Input Voltage
3.0V<VDD3V3<3.6V
0.5*VDD3V3
V
Vhyst
Schmitt trigger hysteresis
3.0V<VDD3V3<3.6V
0.8
V
Vol
Low level output Voltage
Iol = XmA (1),(2)
Voh
High level output Voltage
0.1*VDD3V3
V
0.89*VDD3V3
V
1. Takes into account 200mV voltage drop in both supply lines.
2. X is the source/sink current under worst-case conditions and is depicted for every I/O or output pin in the pin description.
4.3.6
DSP core
Table 10.
DSP core
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Fdsp
DSP clock frequency
75
MHz
Tres
Reset signal low state duration
1
µs
17/38
Electrical specifications
4.4
TDA7505
SAI interface timing - receiver
Figure 3.
SAI interface timing - receiver
Valid
SDI0-2
LRCKR
Valid
SCKR
(RCKP=0)
t lrckrs
t lrckrh
tsdis
tsdih
tsckrl
tsckrh
tsckr
Table 11.
SAI interface timing - receiver
Timing
Description
TDSP(1)
Min
Internal DSP clock period (typical 1/75MHz)
tsckr
Minimum clock cycle
tlrckrs
13.33
Unit
ns
ns
LRCKR setup time
TDSP
ns
tlrckrh
LRCKR hold time
TDSP
ns
tsdid
SDI setup time
TDSP
ns
tsdih
SDI hold time
TDSP
ns
tsckrh
Minimum SCKR high time
0.35 tsckr
ns
tsckrl
Minimum SCKR low time
0.35 tsckr
ns
SAI interface timing - transmitter
Figure 4.
SAI interface timing - transmitter
Valid
SDO0-2
LRCKT
Valid
SCKT
(TCKP=0)
t lrckts
t lrckth
t dt
tscktl
tsckth
tsckt
18/38
Max
6 TDSP
1. TDSP = DSP master clock cycle time = 1/Fdsp
4.5
Typ
TDA7505
Electrical specifications
Table 12.
SAI interface timing - transmitter
Timing
Description
TDSP(1)
Min
Typ
Internal DSP clock period (typical 1/75MHz)
tsckt
Minimum clock cycle
tlrckts
tlrckth
tdt
Max
13.33
Unit
ns
6 TDSP
ns
LRCKT setup time
TDSP
ns
LRCKT hold time
TDSP
ns
SCKT active edge to data out valid
TDSP
ns
tsckth
Minimum SCKT high time
0.35 tsckr
ns
tscktl
Minimum SCKT low time
0.35 tsckr
ns
1. TDSP = DSP master clock cycle time = 1/Fdsp
4.6
SAI protocol
Figure 5.
SAI protocol
LEFT CHANNEL
SCKX
XCKP = 0
SCKX
XCKP = 1
LRCKX
XREL = 0
XLRS = 0
LRCKX
XREL = 0
XLRS = 1
LRCKX
XREL = 1
XLRS = 0
SDY0-2
XDIR = 0
1
SDY0-2
XDIR = 1
14 15 0
30 31
Notes: 1) X = R for receiver
2) Y = I for receiver
4.7
SPDIF receiver
Table 13.
SPDIF receiver
Symbol
fspdif
0
15 14 13 6
31 30 29
1
2
5
4
3
2
RIGHT CHANNEL
1
0
15 14 13 6
31 30 29
9 10 11 12 13 14 15 0
25 26 27 28 29 30 31
1
2
5
4
3
2
1
0
15 14 13
31 30 29
9 10 11 12 13 14 15 0
25 26 27 28 29 30 31
1
2
X = T for transmitter
Y = O for transmitter
Parameter
Max
Unit
96
kHz
Input precision with direct interface to DSP
24
bit
Input precision with interface to ASRC
20
bit
Input sampling rate
Test condition
Fdsp = 75 MHz
Min
32
Typ
19/38
Electrical specifications
4.8
TDA7505
SPI interfaces (Buffered SPI, Display SPI, RDS SPI)
Figure 6.
SPI interfaces
V alid
SS
M ISO
M O SI
V alid
SCK
(CP O L=0,CPH A=0)
t setup
tdtr
tsssetup
t hold
t sshold
tsclkl
tsclkh
tsclk
Table 14.
SPI interfaces
Symbol
TDSP
Description
Min
Internal DSP clock period (typical 1/75MHz)
Typ
13.33
Max Unit
ns
Master mode
tsclk
Clock cycle
tdtr
12 TDSP
ns
SCK edge to MOSI valid
40
ns
tsetup
MISO setup time
16
ns
thold
MISO hold time
9
ns
tsclkh
SCK high time
0.5 tsclk
ns
tsclkl
SCK low time
0.5 tsclk
ns
40
ns
25
ns
12 TDSP
ns
tsssetup SS setup time
tsshold
SS hold time
Slave mode
tsclk
Clock cycle
tdtr
SCK edge to MOSI valid
40
ns
tsetup
MOSI setup time
16
ns
thold
MOSI hold time
9
ns
tsclkh
SCK high time
0.5 tsclk
ns
tsclkl
SCK high low
0.5 tsclk
ns
40
ns
20
ns
tsssetup SS setup time
tsshold
20/38
SS hold time
TDA7505
Electrical specifications
Figure 7.
SPI clocking scheme
SS
SCK
(CPOL=0,CPHA=0)
SCK
(CPOL=0,CPHA=1)
SCK
(CPOL=1,CPHA=0)
SCK
(CPOL=1,CPHA=1)
MISO
MOSI
MSB
6
5
4
3
2
1
0
I2C Timing
4.9
I2C Timing
Figure 8.
Table 15.
Symbol
I2C Timing
Parameter
Test
condition
Standard mode
I2C bus
Fast mode I2C bus
Unit
Min.
Max.
Min.
Max.
0
100
0
400
kHz
FSCL
SCLl clock frequency
tBUF
Bus free between a STOP and
Start Condition
4.7
–
1.3
–
ms
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
4.0
–
0.6
–
ms
tLOW
LOW period of the SCL clock
4.7
–
1.3
–
ms
tHIGH
HIGH period of the SCL clock
4.0
–
0.6
–
ms
tSU:STA
Set-up time for a repeated start
condition
4.7
–
0.6
–
ms
tHD:DAT
DATA hold time
0
–
0
0.9
ms
–
1000
20+0.1Cb
300
ns
tHD:STA
tR
Rise time of both SDA and SCL
signals
Cb in pF
21/38
Electrical specifications
Table 15.
TDA7505
I2C Timing (continued)
Symbol
Test
condition
Parameter
tF
Fall time of both SDA and SCL
signals
tSU;STO
Set-up time for STOP condition
tSU:DAT
Data set-up time
Cb
Standard mode
I2C bus
Max.
Min.
Max.
–
300
20+0.1Cb
300
ns
4
–
0.6
–
ms
250
–
100
–
ns
–
400
–
400
pF
Max.
Unit
Capacitive load for each bus line
DRAM/SRAM interface (EMI)
Table 16.
DRAM timing
Symbol
Parameter
Unit
Min.
Cb in pF
4.10
Fast mode I2C bus
Test condition
Min.
Typ.
Tacc0
Fast DRAM access time
EDTM=0, 16 bit word
17
Tdsp
Tacc0
Fast DRAM access time
EDTM=0, 24 bit word
23
Tdsp
Tacc1
Slow DRAM access time
EDTM=1, 16 bit word
24
Tdsp
Tacc1
Slow DRAM access time
EDTM=1, 24 bit word
32
Tdsp
Table 17.
DRAM refresh period
Symbol
Parameter
Tref
DRAM refresh period
Table 18.
SRAM Timing
Symbol
Tacc
4.11
Parameter
Min.
Typ.
Max.
Unit
782
Tdsp
Max.
Unit
9
Tdsp
469
Test condition
Min.
SRAM access time
Typ.
2
Debug port interface
Table 19.
No.
22/38
Test condition
Debug port interface
Characteristics (Fdsp = 75MHz)
Min.
Max.
Unit
1
DBCK rise time
2
ns
2
DBCK fall time
2
ns
3
DBCK low
40
ns
4
DBCK high
40
ns
5
DBCK cycle time
200
ns
6
DBRQN asserted to DBOUT (ACK) asserted
5*TDSP
ns
7
DBCK high to DBOUT valid
40
ns
TDA7505
Electrical specifications
Table 19.
No.
Debug port interface (continued)
Characteristics (Fdsp = 75MHz)
Min.
Max.
Unit
8
DBCK high to DBOUT invalid
3
ns
9
DBIN valid to DBCK low (set-up)
15
ns
10
DBCK low to DBIN invalid (hold)
3
ns
2*TDSP
ns
DBOUT (ACK) asserted to first DBCK high
DBOUT (ACK) assertion width
5*TDSP - 3
11
Last DBCK low of read register to first DBCK
high of next command
12
Last DBCK low to DBOUT invalid (hold)
DBSEL setup to DBCK
Figure 9.
5*TDSP + 7
ns
7*TDSP + 10
ns
3
ns
TDSP
ns
Debug port serial clock timing
(1)
(2)
(3)
DBCK
(input)
(4)
(5)
D02AU1363
Figure 10. Debug port acknowledge timing
DBRQN
(input)
(6)
DBOUT
(output)
(ACK)
D02AU1364
Figure 11. Debug port data I/O to status timing
DBCK
(input)
(Last)
DBOUT
(output)
(9)
(10)
DBIN
(input)
(Note 1)
Note:
1 High Impedance, external pull-down resistor
D02AU1365
23/38
Electrical specifications
TDA7505
Figure 12. Debug port read timing
DBCK
(input)
(Last)
(Note 1)
(7)
(12)
(8)
DBOUT
(output)
Note:
1 High Impedance, external pull-down resistor
D02AU1369
Figure 13. Debug port DBCK next command after read register timing
DBCK
(input)
(NEXT COMMAND)
(11)
D02AU1370
Table 20.
ASRC
Symbol
Parameters
Total harmonic distortion +
noise, unweighted,
THD+N
Fsin / Fsout = 0.82
(36 kHz → 44.1 kHz)
DR
IPD
Dynamic range,
A-weighted, dithered input,
Fsin / Fsout = 0.82
(36 kHz → 44.1 kHz)
Test conditions
min
typ
max
Unit
20 Hz–20 kHz, full scale, 16 bit inp.
-95
dB
20 Hz–20 kHz, Full scale, 20 bit inp.
-98
dB
1 kHz, full scale, 16 bit inp.
-95
dB
15 kHz, full scale, 16 bit inp.
-95
dB
1 kHz, full scale, 20 bit inp.
-105
dB
15 kHz, full scale, 20 bit inp.
-98
dB
1 kHz, -60 dB, 16 bit inp.
98
dB
1 kHz, -60 dB, 16 bit inp.
120
dB
Interchannel phase deviation
Input sample rate range
No input signal decimation
Input sample rate
Input signal decimation by 2
Output sample rate range
32
0
deg
48
kHz
96
32
kHz
48
kHz
Digital filter
fp
Passband Frequency
Rp
Passband Ripple
fs
Stopband Corner Frequency
Rs
Stopband Attenuation
Table 21.
Symbol
fVCO
24/38
0.4110
0–0.4110 Fsin
-0.01
@ fs
Fsin
+0.01
dB
0.5510
Fsin
-120
dB
Fractional-N PLL
Parameter
VCO output frequency
Test condition
Min.
130
Typ.
Max.
Unit
310
MHz
TDA7505
Table 22.
Symbol
Electrical specifications
ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz
(Tamb = 25°C, ADCVDD = 3.3V, A-weighted filter.)
Parameter
Test condition
Min.
Typ.
Max.
Input voltage dynamic range
Single ended mode
Differential mode
fs
Sampling rate
Audio mode
DR(1)
Dynamic range
-60dB analog input
84
88
dB
SNR
Signal to noise ratio
1kHz; -3dB analog input
84
88
dB
Vin
THD+N
Ri
ICL(2)
0.5
1
Unit
48
Total harmonic distortion + noise 1kHz; -3dB analog input
Input impedance
@ fs = 44.1kHz
Interchannel isolation
Full scale input @ 1kHz
Vrms
-85
45
-80
kHz
dB
80
kΩ
-95
dB
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
2. ICL can be influenced by external anti alias filter
Table 23.
Symbol
Vin
fs
DR
(1)
SNR
THD+N
ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz
(Tamb = 25°C, ADCVDD = 3.3V)
Parameter
Test condition
Input voltage dynamic range
Min.
Typ.
Max.
0.5
Unit
Vrms
Sampling rate
FM-mode
192
Dynamic range
-60dB analog input
80
dB
Signal to noise ratio
1kHz; -3dB analog input
80
dB
Total harmonic distortion + noise 1kHz; -3dB analog input
kHz
-80
dB
Max.
Unit
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
Table 24.
Symbol
Vin
ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz
(Tamb = 25°C, AVDD = 3.3V)
Parameter
Test condition
Input voltage dynamic range
Min.
Typ.
0.5
Vrms
fs
Sampling rate
FM-mode for spike and RDS
DR(1)
384
kHz
Dynamic range
-60dB analog input
60
dB
SNR
Signal to noise ratio
1kHz; -3dB analog input
60
dB
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
Table 25.
Symbol
Vin
THD
THD+N
SNR
Level ADC electrical characteristics
(Tamb = 25°C, AVDD = 3.3V)
Parameter
Input voltage range
Test condition
Min.
Typ.
0
Max.
Unit
2.5
V
Total harmonic distortion
-57
dB
Total harmonic distortion + noise
-46
dB
Signal to noise ratio
46
dB
25/38
Electrical specifications
Table 26.
DAC Performance
(Tamb = 25°C, DACVDD = 3.3V, measurement bandwidth 10Hz to 20kHz)
Symbol
THD+N
TDA7505
Parameter
Test condition
Min.
Typ.
Max.
Unit
Total harmonic distortion + noise 1kHz; -1dBFS, flat
-90
dB
THD
Total harmonic distortion
1kHz; -1dBFS, flat
-90
dB
SNR
Signal to noise ratio
1kHz;IEC61606 A-weighted RMS
100
dB
DR(1)
Dynamic range
1kHz; -60dBFS;
IEC61606 A-weighted RMS
100
dB
NF(2)
Noise floor
IEC61606 A-weighted RMS
-100
dBV
ICL
Interchannel isolation
1kHz; 0dBFS
-90
dB
Xtlk
Crosstalk
1kHz; 0dBFS
-90
dB
IGM
Interchannel gain mismatch
1kHz; 0dBFS
0.1
dB
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
2. With 00h input
Table 27.
Symbol
a_ch
FM stereo decoder (SW)
(Tamb = 25°C, ADCVDD = 3.3V, measurement bandwidth 10Hz to 20kHz, A-Weighted Filter.)
Parameter
Channel separation
(THD+N) Total harmonic distortion
SNR
26/38
Test condition
Signal to noise ratio
Min.
Typ.
Max.
Unit
>40
dB
-3dB analog input
-80
dB
1kHz; -3dB analog input; mono
86
dB
TDA7505
5
Functional description
Functional description
The TDA7505 is broken up into three distinct blocks. One block contains the two DSP Cores
and their associated peripherals. The second contains the analog modules ADC with input
multiplexer and level adjust and the DAC. The third module contains the RDS processing:
filter, demodulator, decoder with error correction and the I2C/SPI interface with data buffer
and interrupts output.
5.1
24-bit DSP core
The two DSP cores are used to process the audio and FM/AM data, coming from the ADC,
or any kind of digital data coming via SPDIF or SAI. After the digital signal processing these
data are sent to the DAC for analog conversion. Functions such as volume, tone, balance,
and fader control, as well as spatial enhancement and general purpose signal processing
may be performed by the DSP0. When FM/AM mode is selected, DSP1 is fully devoted to
AM/FM processing. Nevertheless it can be used for any kind of different application, when a
different input source is selected. Some capabilities of the DSPs are listed below:
●
Single cycle multiply and accumulate with convergent rounding and condition code
generation
●
2 x 56-bit Accumulators
●
Double precision multiply
●
Scaling and saturation arithmetic
●
48-bit or 2 x 24-bit parallel moves
●
64 interrupt vector locations
●
Fast or long interrupts possible
●
Programmable interrupt priorities and masking
●
Repeat instruction and zero overhead DO loops
●
Hardware stack capable of nesting combinations of 7 DO loops or 15
interrupts/subroutines
●
Bit manipulation instructions possible on all registers and memory locations, also Jump
on bit test
●
4 pin serial debug interface
●
Debug access to all internal registers, buses and memory locations
●
5 word deep program address history FIFO
●
Hardware and software breakpoints for both program and data memory accesses
●
Debug Single stepping, Instruction injection and Disassembly of program memory
27/38
Functional description
5.2
TDA7505
DSP peripherals
There are a number of peripherals that are tightly coupled to the two DSP Cores. Some of
the peripherals are connected to DSP 0 others are connected to DSP 1.
5.2.1
●
4k x 24-Bit Program RAM for DSP0
●
16k x 24-Bit mask programmable Program ROM for DSP0
●
4k x 24-Bit X-Data RAM for DSP0
●
4k x 24-Bit Y-Data RAM for DSP0
●
4k x 24-Bit Program RAM for DSP1
●
16k x 24-Bit mask programmable Program ROM for DSP1
●
4k x 24-Bit X-Data RAM for DSP1
●
4k x 24-Bit mask programmable X-Data ROM for DSP1
●
4k x 24-Bit Y-Data RAM for DSP1
●
6 channel Serial Audio Interface (SAI)
●
2 channel SPDIF receiver with sampling rate conversion
●
I2C and SPI interfaces
●
XCHG Interface for DSP to DSP communication
●
External Memory Interface (DRAM/SRAM) for time-delay and traffic information
●
Debug Port for both DSP´s
●
General-purpose Input/Output lines
●
Asynchronous Sample Rate Converter
●
SINCOS co-processor
●
PLL Clock Oscillator
●
ADC´s, ADC input multiplexer and DAC´s (see Section 5.2.12: CODEC on page 32)
Data and program memories
Both DSP0 and DSP1 have data and program memories attached to them. Each memory
type is described below:
X-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address,
XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM
Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core.
X-ROM
This is a 24-Bit Single Port mask programmable ROM used for storing coefficients. The 16Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP
core. The 24-Bit XRAM Data, XDBx(23:0), may be read from the Data ALU of the DSP core.
Y-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address,
YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data,
YDBx(23:0), is written to and read from the Data ALU of the DSP core.
28/38
TDA7505
Functional description
Program RAM
This is a 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit
PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP
core for Instruction Fetching, and by the AGU in the case of the Move Program Memory
(MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be
written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed
to the Program Decode Controller of the DSP core for instruction decoding.
Program ROM
This is a 24-Bit Single Port mask programmable ROM used for storing and executing
program code. Additionally the boot loader SW is placed here. Essentially this consists of
reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM and YRAM. The
16-Bit PROM Address, PABx(15:0) is generated by the Program Address Generator of the
DSP core for Instruction Fetching, and by the AGU in the case of the Move Program
Memory (MOVEM) Instruction. The 24-Bit PROM Data (Program Code), PDBx(23:0), can
only be read but not written. During instruction fetching the PDBx Bus is routed to the
Program Decode Controller of the DSP core for instruction decoding.
5.2.2
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the device from an external source. Once
processed by the device, either it can be returned through this interface or sent to the DAC
for D/A conversion. The features of the SAI are listed below:
5.2.3
●
3 Synchronized Stereo Data Transmission Lines
●
3 Synchronized Stereo Data Reception Lines
●
Master and Slave operating mode: clock lines can be both master and slave.
●
Receive and Transmit Data Registers have two locations to hold left and right data.
Serial peripheral interface (SPI)
The DSP core requires a serial interface to receive commands and data over the LAN.
During an SPI transfer, data are transmitted and received simultaneously. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave
select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out through one data pin while another
8-bit word is simultaneously shifted in through a second data pin. The central elements in
the SPI system are the shift register and the read data buffer. The system is single buffered
in the transfer direction and has a 10 word buffer in the receive direction (only master SPI;
the display SPI is single word buffered only).
5.2.4
Sony/Phillips digital interface (S/PDIF)
The S/PDIF receiver is a serial digital audio interface. It receives and decodes serial audio
data according to one of the following standards: AES/EBU, IEC 958, S/PDIF, and EIAJ CP340 in a frequency range from 32kHz up to 96kHz. The transfer protocol provides two audio
data channels.
There is a direct output connected to Asynchronous Sample Rate Converter. Left and right
20 bit audio-channels and sample clock are provided.
29/38
Functional description
5.2.5
TDA7505
I2C interface
The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter
IC control. The device is compliant with the I2C specification including the highs peed (400
kHz) mode.
Every component hooked up to the I2C bus has its own unique address whether it is a CPU,
memory or some other complex function chip. Each of these chips can act as a receiver and
/or transmitter on its functionality.
The device may act as master or as slave.
XCHG interface (DSP to DSP exchange interface)
The Exchange Interface peripheral provides bidirectional communication between DSP0
and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized
for received data. It minimizes the number of times an Exchange Interrupt Service Routine
would have to be called if multi-word blocks of data were to be received. The Transmit FIFO
is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP.
The features of the XCHG are listed below:
5.2.6
●
10 Word XCHG FIFO on DSP0 to transfer data to DSP1
●
24 Word XCHG FIFO on DSP1 to transfer data to DSP0
●
Four Flags for each XCHG for DSP to DSP signaling
●
Condition flags can optionally trigger interrupts on both DSP´s
DRAM/SRAM interface (DEMI)
The External DRAM/SRAM Interface is viewed as a memory mapped peripheral of both
DSP cores. Data transfers are performed by moving data into/from data registers. The
control is exercised by polling status flags in the control/status register or by servicing
interrupts. This can be done by both DSP cores.
The features of the DEMI (Dual core Extended Memory Interface) are listed below:
30/38
●
Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM
●
Data word length 16 or 24 bits for DRAM
●
Data word length 8 or 16 or 24 bits for SRAM
●
13 DRAM address lines means 226 = 256M bit addressable DRAM
●
Refresh rate for DRAM can be chosen among eight divider factors
●
SRAM relative addressing mode; 222 = 32M bit addressable SRAM
●
Four SRAM Timing choices
●
Two Read Offset Registers
TDA7505
5.2.7
Functional description
Debug interface
A multiplexed Debug Port is available for the DSP Cores. The debug logic is contained in the
core design of the DSP. The features of the Debug Port are listed below:
5.2.8
●
Breakpoint Logic
●
Trace Logic
●
Single stepping
●
Instruction Injection
●
Program Disassembly
General purpose input/output
The DSP requires a set of external general purpose input/output lines, and a reset line.
These signals are used by external devices to signal events to the DSP. The GPIO lines are
implemented as DSP 's peripherals. The GPIO lines are grouped in Port A, connected to
DSP 0, and Port B, connected to DSP1.
5.2.9
Asynchronous sample rate converter
The ASRC, embedded in the device, offers a fully digital stereo asynchronous sample rate
conversion of digital audio sources to the device's internal sample frequency. This solves the
problem of mixing audio sources with different sample rates.
The ASRC is able to do both up- and down-sampling. There is no need to explicitly program
the input and output sample rates, as the ASRC solves this problem with an automatic
Digital Ratio Locked Loop.
In case of down sampling, an internal low pass filter limits the bandwidth. Thus any down
folding products are avoided.
The ASRC is intended for applications up to 20 bit input word width. Digital Audio Sources
can be applied in general Serial Audio Interface format (3 wires) as well as in AES/EBU, IEC
958, S/PDIF and EIAJ CP-340 format (1 wire).
An interface to the DSP core offers the possibility of interrupt controlled sample delivery.
Furthermore, a programmable Control/Status Register inside the ASRC allows a great
variety of adjustments and status information.
The ASRC is intended for applications
5.2.10
–
up to 20 bit input and 24 bit output word width,
–
32kHz to 96kHz sample rate for input signal (SPDIF Receiver features)
–
32kHz to 48kHz sample rate for output signal.
SINCOS co-processor
The SINCOS is a cordic-based co-processor for calculation of sine and cosine without using
DSP resources.
5.2.11
PLL clock oscillator
The PLL Clock Oscillator can accept an external clock at CLKIN or it can be configured to
run with an internal oscillator when a crystal is connected across pins XTI & XTO. There is
an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128)
31/38
Functional description
TDA7505
in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to
generate the internal clock. This allows the internal clock to be within 1 MHz of any desired
frequency even when XTI is much greater than 1 MHz. It is recommended that the input
clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update
rate.
The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be
driven by the XTI pin directly.
The crystal oscillator and the PLL will be gated off when entering the power-down mode (by
setting a register on DSP0).
5.2.12
CODEC
The CODEC is composed of four plus one A/D mono converters and three D/A stereo
converters.
Two channels of the ADC can operate both in audio mode and in FM mode. When in audio
mode, it converts the audio bandwidth from 20Hz to 20KHz. The A to D is a third order
Sigma-Delta converter with 20-bit resolution. When in FM mode, the converted bandwidth is
up to 192KHz.
Additionally a lower resolution A to D converter is implemented. It is used to convert the
level signal of the tuner. Alternatively it may be used to convert voice signals.
The DAC is a second order multi bits Sigma-Delta converter accepting 24 bits input data. All
the reference voltages are generated inside the chip but they have to be decoupled with
external capacitors.
5.2.13
Radio data system (RDS)
The RDS block is a hardware cell able to deliver the RDS frames through a dedicated serial
interface. An RDS quality signal is also available. This block needs to be initialized at reset
by the DSP, after that it works in background and does not need any further DSP support.
RDS is made of 57kHz filter, demodulator, decoder with error correction and an I2C/SPI
programmable interface with data buffer and interrupt output.
Due to its own interface, it may be considered as an independent function. Thus the module
has a separate RDS I2C device address as well as a separate chip select line for the RDS
SPI. Only the pins are shared with the DSP interfaces.
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TDA7505
5.2.14
Functional description
Clock scheme
Due to the programmable PLL oscillator, the clock scheme is very flexible. The customer
may choose the clock frequency according to the application needs. However one should
take into account several constraints:
●
The RDS module needs a crystal frequency of 8.55 MHz or alternative an external
74.1MHz Oscillator. However the PLL may be supplied by an external clock reference
and the crystal in parallel may drive the RDS module.
●
The CODEC (A/D and D/A) module needs a clock of 512 times the audio sample rate
(Fs).
●
The audio sample rate (Fs) should be close to 44.1 kHz. This allows CD quality. Higher
sample rates will reduce the number of DSP clock cycles per Fs and hence will reduce
the available MIPS.
●
The DSP core clock frequency may not exceed 76 MHz
●
In a car radio system the second and third system clock harmonics (DSP clock and
CODEC clock) should be outside the radio frequency bands.
Two examples of convenient clock schemes are shown in the following table:
Table 28.
Examples of convenient clock schemes
Clock scheme
Alternative(1)
Fxtal
8.55 MHz
74.1 MHz
Fcomp
Fxtal / 4
2.14 MHz
Fxtal/21
3.53 MHz
Fvco
Fcomp * 106
226.58 MHz
Fcomp * 64
225.8 MHz
Fdsp
Fvco / 3
75.53 MHz
Fvco / 3
75.28 MHz
Fcodec
Fvco / 10
22.66 MHz
Fvco / 10
22.58 MHz
Fs
44.25 kHz
44.11 kHz
1. External clock oscillator used
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Software features
6
TDA7505
Software features
A great flexibility is guaranteed by the two programmable DSP cores. A list of the main
software functions, which can be implemented in the TDA7505, is enclosed hereafter:
6.1
6.2
6.3
6.4
AM/FM base band signal processing
●
FM weak signal processing
●
Integrated 19 kHz Pilot tone filter
●
De-emphasis
●
Stereo blend
●
Variable high cut
●
Flexible noise cancellation
●
Flexible multipath detector
●
Asynchronous demodulation allows the usage of any sample rate
Generic audio signal processing
●
Loudness
●
Bass, treble, fader control
●
Volume control
●
Distortion Limiting
●
Premium Equalization
●
Soft mute
TAPE signal processing
●
Dolby B Noise Reduction
●
Automatic Music Search
CD signal processing
●
6.5
6.6
Audiophile
●
Parametric Equalization
●
Crossover
●
Channel Delays
●
Center Channel Imaging Output
●
Audio Noise Reduction
Audio decompression
●
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Dynamic Range Compression
MP3 including C3 block decoder
TDA7505
6.7
Software features
Other
6.8
●
Voice compression/decompression for traffic information storage
●
Echo and noise canceling for mobile phone connection
Functional modes
The SW defines the whole functionality of the device, except RDS. Although ST is able to
provide a complete set of SW, the customer may implement his own SW or may use third
party SW. This allows a flexible adaptation to the application needs.
The concept allows the parallel processing of two independent audio sources. For example
one source may go through the loudspeakers, whereas another source may feed a
headphone. Additionally other sources like a phone or a navigation system may be mixed to
the audio source. In case the 150 MIPS available are not sufficient, a co-dsp (e.g.:
TDA7502) may be connected through the serial audio interface (SAI). Finally the device may
be embedded into an audio bus system (e.g.: MOST).
Following table shows an example of possible modes:
Table 29.
Example of possible modes
Source
Comment
AM/FM mode
CD mode
(digital)
CD Changer
mode (analog)
Tape mode
(digital)
Traffic info
play mode
DSP1
Main source
and RDS
Alternative
Rear Source
and RDS
Alternative
Rear Source
and RDS
Alternative
Rear Source
and RDS
Alternative
Rear Source
and RDS
DSP1
Alternative
Rear Source
Alternative
Rear Source
Main source
Alternative
Rear Source
Alternative
Rear Source
DSP0
Summed to
Main source
Summed to
Main source
Summed to
Main source
Summed to
Main source
Summed to
Main source
DSP1
Alternative
Rear Source
through SRC
Main source
through SRC
Alternative
Rear Source
through SRC
Alternative
Rear Source
through SRC
Alternative
Rear Source
through SRC
Tape via ADC
(digital SAI)
Dolby B on
DSP1
Alternative
Rear Source
Alternative
Rear Source
Alternative
Rear Source
Main source
Alternative
Rear Source
DSP co-processor
MDSP: master
Available (1)
CO-dsp: slave
Available(1)
Available(1)
Available(1)
Available(1)
Traffic info
storage
DSP0
Background
recording
Background
recording
Background
recording
Main source
& Background
recording
MOST bus
MDSP: slave
Co-dsp: slave Available(1)
MOST: master
Available(1)
Available(1)
Available(1)
Available(1)
AM/FM MPX
(analog)
CD changer
(analog)
Phone/Navi
(analog)
CD/CD ROM
audio/MP3
(digital SPDIF)
Background
recording
1. The total number of SAI channels is six. They must be split between MOST, Co-DSP and the external ADC for tape. In case
of MOST, the DSP clock must be synchronized to the MOST bus.
Note:
The main source (blue) may run in parallel with one of the alternative rear sources (yellow).
Phone/Navi, DSP Co-processor, traffic info storage and MOST (green) are available in
parallel to all modes.
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Package information
7
TDA7505
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 14. LQFP100 (14x14x1.4mm) mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
MAX.
1.600
0.0630
0.150 0.0020
0.0059
A1
0.050
A2
1.350
1.400
1.450 0.0531 0.0551 0.0571
b
0.170
0.220
0.270 0.0067 0.0087 0.0106
c
0.090
0.200 0.0035
0.0079
D
15.800 16.000 16.200 0.6220 0.6299 0.6378
D1
13.800 14.000 14.200 0.5433 0.5512 0.5591
D3
12.000
0.4724
E
15.800 16.000 16.200 0.6220 0.6299 0.6378
E1
13.800 14.000 14.200 0.5433 0.5512 0.5591
E3
12.000
e
L
0.4724
0.500
0.450
0.600
0.0197
0.750 0.0177 0.0236 0.0295
L1
1.000
K
0˚ (min.), 3.5˚ (typ.), 7˚(max.)
ccc
OUTLINE AND
MECHANICAL DATA
0.0394
0.080
LQFP100 (14x14x1.40mm)
Low profile Quad Flat Package
0.003
0086901 D
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TDA7505
8
Revision history
Revision history
Table 30.
Document revision history
Date
Revision
23-Oct-2007
1
Changes
Initial release.
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TDA7505
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