FAIRCHILD TDC1016J5AX

www.fairchildsemi.com
TDC1016
Video Speed D/A Converter
10-Bit, 20 Msps
Features
Description
•
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•
•
•
•
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The TDC1016 is a bipolar monolithic digital-to-analog
converter which can convert digital data into an analog voltage at rates up to 20 Msps (Megasamples Per Second). The
device includes an input data register and operates without
an external deglitcher or amplifier.
20 Msps conversion rate
8, 9, or 10-bit linearity
Voltage output, no amplifier required
Single supply operation (-5.2V, ECL compatible)
Dual supply operation (±5.0V, TTL compatible)
Internal 10-bit latched data register
Low glitch energy
Disabling controls, forcing full-scale, zero, and inverting
input data
• Binary or two’s complement input data formats
• Differential gain = 1.5%, differential phase = 1.0°
Operating the TDC1016 from a single -5.2V power supply
will bias the digital inputs for ECL levels, while operating
from a dual ±5V power supply will bias the digital inputs for
TTL levels.
All versions of the TDC1016 are 10-bit digital-to-analog
converters, but are available with linearity specifications of
either 8, 9, or 10 bits. The TDC1016 is patented under U.S.
patent number 3283120 with other patents pending.
Applications
• Construction of video signals from digital data 3x or 4x
NTSC or PAL color subcarrier frequency
• CRT graphics displays, RGB, Raster, Vector
• Waveform synthesis
Block Diagram
10 TTL INPUTS
(20 ECL INPUTS)
CLK
(CLK)
TTL/ECL
DIGITAL
INPUT
BUFFERS
DATA
LATCHED
CURRENT
SWITCHES
10
10
10
R–2R
RESISTOR
NETWORK
AOUT
NDIS
(NDIS)
CLK
VREF
NFL
NFH
N2C
VREF
A
65-1016-01
COMP
Rev. 1.0.0
TDC1016
Functional Description
General Information
TTL/ECL buffers are used for all digital inputs to the
TDC1016. Logic family compatibility depends upon the
connection of power supplies. When single power supply
(-5.2V) operation is employed, all data, clock, and disable
inputs are compatible with differential ECL logic levels. All
digital inputs become compatible with TTL levels when dual
power supply (±5.0V) operation is used.
The internal 10-bit register latches data on the rising edge of
the clock (CLK) pulse. Currents from the current sources are
switched accordingly and combined in the resistor network
to give an analog output voltage. The magnitude of the output voltage is directly proportional to the magnitude of the
digital input word.
The NFL and NFH inputs can be used to simplify system
calibration by forcing the analog output voltage to either its
zero-scale or full-scale value. The TDC1016 can be operated
in binary, inverse binary, two’s complement or inverse two’s
complement input data formats.
PRODUCT SPECIFICATION
The internal operational amplifier of the TDC1016 is frequency stabilized by an external 1 mF tantalum capacitor
connected between the COMP pin and VEE. A minimum of
1 mF is adequate for most applications, but 10 microfarads or
more is recommended for optimum performance. The negative side of this capacitor should be connected to VEE.
Controls
The NDIS inputs are used to disable the TDC1016 by
forcing its output to the zero-scale value (current sources
off). The NDIS inputs are asynchronous, active without
regard to the CLK inputs. The other digital control inputs are
synchronous, latched on the rising edge of the CLK pulse.
The rising edge of the CLK pulse transfers data from the
input lines to the internal 10-bit register. In TTL mode, the
inverted inputs for CLK, DATA, and NDIS are inactive and
should be left open.
The Input Coding Table illustrates the function of the digital
control inputs. A two’s complement mode is created by activating N2C with a Logic 0 When NFH and NFL are both
activated with a Logic 0 the input data to the 10-bit register is
inverted.
Power
The TDC1016 can be operated from a single -5.2V power
supply or from a dual ±5.0V power supply. For single power
supply operation, VCC is connected to DGND and all inputs
to the device become ECL compatible. When VCC is tied to
+5.0V, the inputs are TTL compatible.
The return path for the output from the 10 current sources is
AGND. The current return path for the digital section is
DGND. DGND and AGND should be returned to system
power supply ground by way of separate conductive paths to
prevent digital ground noise from disturbing the analog circuitry of the TDC1016. All AGND pins must be connected to
system analog ground.
Reference
The reference input is normally set to -1.0V with respect to
AGND. Adjusting this voltage is equivalent to adjusting system gain The temperature stability of the TDC1016 analog
output (AOUT) depends primarily upon the temperature stability of the applied reference voltage
2
Data Inputs
Data inputs are ECL compatible when single power supply
operation is employed. The J5 and C2 packages allow for
differential ECL inputs while the J7 and B7 packages have
only single-ended inputs. When differential ECL data is
used, any data input can be inverted simply by reversing the
connections to the true and inverted data input pins. All
inverted input pins should be left open if single-ended ECL
or TTL modes are used. All data inputs have an internal
40 KW pullup resistor to VCC.
Analog Output
The analog output voltage is negative with respect to AGND
and varies proportionally with the magnitude of the input
data word. The output resistance at this point is 80W,
nominally.
No Connects
There are several pins labeled no connect (NC) on the
TDC1016 J5 and C2 packages, which have no connections
to the chip. These pins should be left open.
PRODUCT SPECIFICATION
TDC1016
Pin Assignments
40 Lead Ceramic DIP
NC
1
40
NC
VEE
2
39
NC
COMP
3
38
NC
VREF
4
37
D10 (LSB)
AGND
5
36
D10 (LSB)
AGND
6
35
D9
AOUT
7
34
D9
AGND
8
33
D8
VCC
DGND
9
32
D8
24
COMP
31
D7
VREF
AGND
1
10
2
23
VEE
NDIS
11
30
D7
AGND
3
22
D10 (LSB)
CLK
12
29
D6
AOUT
4
21
D9
CLK
13
28
D6
AGND
5
20
D8
NDIS
14
27
D5
VCC
6
19
D7
(MSB) D1
15
26
D5
DGND
7
18
D6
(MSB) D1
16
25
D4
NDIS
8
17
D5
N2C
17
24
D4
CLK
9
16
D4
D2
18
23
D3
(MSB) D1
10
15
D3
D2
19
22
D3
N2C
11
14
NFL
NFH
20
21
NFL
D2
12
13
NFH
24 Lead Ceramic DIP
65-1016-02
Pin Descriptions
Pin Number
Pin Name
40-Lead
24-Lead
Value
Pin Function Description
VCC
9
6
+5.0V
Positive Supply Voltage.
VEE
2
23
-5.0V
Negative Supply Voltage.
AGND
5, 6, 8
2, 3, 5
0.0V
Analog Ground.
DGND
10
7
0.0V
Digital Ground.
VREF
4
1
-1.0V
Reference Voltage In.
COMP
3
24
1mF
11
8
TTL/ECL
Power
Reference
Compensation.
Controls
NDIS
Not Disable.
NDIS
14
—
ECL
CLK
12
9
TTL/ECL
Not Disable (Inv).
CLK
13
—
ECL
N2C
17
11
TTL/ECL
Not Two’s Complement.
NFH
20
13
TTL/ECL
Not Force HIGH.
NFL
21
14
TTL/ECL
Not Force LOW.
16, 19, 23, 25,
27, 29, 31, 33,
35, 37
10, 12, 15–20,
27, 22
TTL/ECL
Data Bits 1–10. D1 is the MSB, D10 is the LSB.
Clock.
Clock (Inv).
Data Inputs
D1–D10
3
TDC1016
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number
Pin Name
D1–D10
40-Lead
24-Lead
Value
15, 18, 22, 24,
26, 28, 30, 32,
34, 36
—
ECL
Pin Function Description
7
4
0V–1V
Analog Output Voltage
1, 38–40
—
Open
No Connection
Data Bits 1–10 (Inv). D1 is the MSB, D10 is the
LSB.
Analog Output
AOUT
No Connection
NC
Absolute Maximum Ratings (beyond which the device wille be damaged)1
Parameter
Min.
Max.
Unit
VCC (measured to DGND)
-0.5
+7.0
V
VEE (measured to AGND)
-7.0
+0.5
V
AGND (measured to DGND)
-0.5
+0.5
V
Digital (measured to DGND)
-7.0
+7.0
V
Reference (measured to AGND)
-1.5
+0.5
V
-2.0
+2.0
V
Supply Voltages
Input Voltages
Output
Applied Voltage (measured to AGND)2
Short-Circuit Duration
Indefinite
Temperature
Operating, Ambient
+125
°C
Operating, Junction
+175
°C
Lead, Soldering (10 seconds)
+300
°C
+150
°C
Storage
-65
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
4
PRODUCT SPECIFICATION
TDC1016
Operating Conditions
Temperature Range
Standard
Symbol
Parameter
VCC
Positive Supply Voltage
Extended
Min.
Nom.
Max.
Min.
Nom.
Max.
Unit
TTL Mode
4.75
5.0
5.25
4.50
5.0
5.50
V
ECL Mode
-0.25
0.0
0.25
-0.25
0.0
0.25
V
VEE
Negative Supply Voltage
-4.5
-5.0
-5.5
-4.5
-5.0
-5.5
V
VAGND
Analog Ground Voltage (Measured to
DGND)
-0.1
0.0
0.1
-0.1
0.0
0.1
V
tPWL
CLK Pulse Width, LOW
15
20
ns
tPWH
CLK Pulse Width, HIGH
15
20
ns
tS
Input Register Set-up Time
TTL Mode
20
22
ns
ECL Mode
25
27
ns
tH
Input Register Hold Time
2
2
ns
VIL
Logic 0
TTL Mode
DGND
0.8
ECL Mode
DGND
-1.67
VIH
Logic 1
TTL Mode
2.0
VREF
Reference Voltage
ECL Mode
-1.0
-0.8
CCOMP
Compensation Capacitor
1.0
TA
Ambient Temperature
TC
Case Temperature
VCC
2.01
0.8
V
-1.67
V
VCC
V
-1.0
-1.0
-1.2
0
-0.8
V
-1.0
1.2
V
mF
1.0
°C
70
-55
125
°C
Note:
1. VIH/NDIS = 2.2 Min.
DC Electrical Characteristics
Temperature Range
Standard
Symbol
Parameter
Test Conditions
Extended
Min. Max. Min. Max. Unit
ICC
Power Supply Current
TTL Mode, VCC = Max, VEE = Max
20
20
mA
IEE
Power Supply Current
TTL Mode, VCC = Max, VEE = Max1
-130
-150
mA
IREF
Reference Input Current
VEE = Max, VREF = -10V
10
10
mA
IIL
Logic 0 Input Current
TTL Mode, VCC = Max, VEE = Max
-1.0
-1.0
mA
ECL Mode, VCC = 0.0, VEE = Max
-300
-300
mA
IIH
Logic 1 Input Current
TTL Mode, VCC = Max, VEE = Max
75
75
mA
ECL Mode, VCC = 0.0, VEE = Max
350
350
mA
COUT
Output Capacitance
AOUT to AGND (Figure 2)
10
10
pF
CIN
Digital Input Capacitance
Any Digital Input to DGND
35
35
pF
ROUT
Output Resistance
AOUT to AGND (Figure 2)
95
W
70
95
70
Note:
1. Return current from VEE flows through AGND.
5
TDC1016
PRODUCT SPECIFICATION
AC Electrical Characteristics
Temperature Range
Standard
Parameter
Test Conditions
FC
Maximum Data Rate
TTL Mode Full-Scale Output Step
20
20
MSPS
ECL Mode Full-Scale Output Step
17.8
17.8
MSPS
tDS
Data Turn on Delay
tSET
Settling Time
tRV
Output 10% to 90%
Risetime
Min.
Extended
Symbol
Max.
RL = 75 Ohms
Min.
Max.
30
30
Unit
ns
TDC1016-8 to 0.2%
30
30
ns
TDC1016-9 to 0.1%
35
35
ns
TDC1016-10 to .05%
40
40
ns
VEE = Nom., RL = 75W,
Full-Scale Step
5.5
5.5
ns
Timing Diagram
tS
tH
DATA
CONTROLS
CLOCK
tPWL
1
tPWH
CLOCK
±1/2 LSB
±1/2 LSB
OUTPUT
tDS
tSET
NOTE: 1. Differential ECL mode only
65-1016-06
Figure 1. Timing Diagram
System Performance Characteristics
Temperature Range
Standard
Parameter
Max.
Unit
RES
Resolution
All TDC1016 Devices
10
10
Bits
ELI, ELD
Linearity Error Integral and
Differential, Independent
Based
TDC1016-8
0.2
0.2
% FS
TDC1016-9
0.1
0.1
% FS
TDC1016-10
0.075
VOFS
Full-Scale Output Voltage
VEE = Nom, RL ³ 10kW,
VREF = -1.000V
VOZS
Zero-Scale Output Voltage
VEE = Nom, RL ³ 10 kW,
VREF = -1.000V
DP
Differential Phase
DG
Test Conditions
Differential Gain
-1.05
Min.
% FS
V
±15
±15
mV
NTSC 4x Subcarrier1
1.0
1.0
Degrees
subcarrier1
1.5
1.5
%
NTSC 4x
-0.95
Max.
-1.05
-0.95
GE
Glitch Energy (Area)
RL = 50W, Midscale
125
125
pV-sec
GV
Glitch Voltage
RL = 50W, Midscale
35
35
mV
Note:
1. In excess of theoretical DP and DG due to quantizing error.
6
Min.
Extended
PRODUCT SPECIFICATION
TDC1016
Equivalent Circuits
AGND
ROUT
80½1
COUT
AOUT
INPUT DATA DEPENDENT
CURRENT SINK
VEE
NOTE: 1. 75½ requires outside trim
65-1016-03
Figure 2. Analog Output Equivalent Circuit, TTL and ECL Mode
VCC
(+5.0V)
VCC
(+5.0V)
40K
50K
40K
50K
35K
DGND
13K
6.7K
DATA
DATA
I=0
DATA
37K
DGND
VEE
I = 75µA
VEE
65-1016-04
Figure 3. Digital Input Equivalent Circuit, TTL Mode
Figure 4. Digital Input Equivalent Circuit, ECL Mode
7
TDC1016
PRODUCT SPECIFICATION
Input Coding Table
NDIS
N2C
NFH
NFL
Data
Output
Description
0
x
x
x
xxxxxxxxxx
0.0
Output Disabled
1
1
1
1
1
1
1
1
1111111111
0000000000
0.0
-1.0
Binary (Default State for TTL Mode
Control) Inputs Open
1
1
1
1
0
0
0
0
1111111111
0000000000
-1.0
0.0
Inverse Binary
1
1
0
0
1
1
1
1
0111111111
1000000000
0.0
-1.0
Two’s Complement
1
1
0
0
0
0
0
0
0111111111
1000000000
-1.0
0.0
Inverse Two’s Complement
1
1
x
x
0
1
1
0
xxxxxxxxxx
xxxxxxxxxx
0.0
-1.0
Force HIGH
Force LOW
Notes:
1. For TTL, 0.0 < VIL < +0.8V is Logic 0.
2. For TTL, +2.0 < VIH < +5.0V is Logic 1.
3. For ECL, -1.85 < VIL < -1.67V is Logic 0.
4. For ECL, -1.0 < VIH < -0.8V is Logic 1.
5. x = don’t care.
Applications Discussion
Calibration
The TDC1016 is calibrated by adjusting the voltage reference to give the desired full-scale output voltage. The current
switches can be turned on either by loading the data register
with full-scale data or by bringing the NFH input to a logic
zero. Note that all 10 current switches are activated by the
NFH input and the resulting full-scale output voltage will be
greater than if the system used only eight or nine bits for
full-scale data.
Typical Application
The Typical Interface Circuit (Figure 5) shows the TDC1016
in a typical application, reconstructing video signals from
digital data. Television timing signals, SYNC and
BLANKING, are added by injecting current from the Wilson
current source into a resistor divider circuit at the output of
the TDC1016.
8
The TDC1016 output and currents from the SYNC and
BLANKING inputs are summed and amplified by the
HA2539 wide-band operational amplifier. Note the careful
power supply decoupling at the power input pins of the
amplifier. The output of the circuit is a composite video signal with SYNC and BLANKING levels coming from external sources. This technique allows the TDC1016 to use its
entire dynamic range for the video information while pulses
are added by other means.
The reference for the TDC1016 is generated by dividing the
output voltage from a two-terminal band-gap voltage reference. System gain is calibrated by adjusting variable resistor
R1. Analog and digital grounds should be routed back to system power supply ground by separate paths.
PRODUCT SPECIFICATION
TDC1016
+12V
+5V
C4
R14
R15
R16 R22
Q4
C1
CLOCK
12
16
19
23
25
TTL DATA
INPUTS
+
27
29
31
33
35
37
9
CLK VCC
D1 MSB
10
R17
Q2
DGND
Q3
D3
D6
BLANKING
+5V
AOUT
C6
D7
U4
R21
7
U1
TDC1016
SYNC
Q5
Q1
D4
D5
R18
R4
D2
U4
R20
CR1
R4
D8
+12V
D9
+5V
D10 LSB
VCC COMP VREF AGND
3 + 4
2
+ 5,6,8
C2
R11
C3
R1 GAIN
R2
OFFSET
R3
U2
R6
R7
R12
C7
L1
14
–
1
C5
U3
+
R13
10
8
R10
3
C8
R12
-5V
R8
C9
COMPOSITE
VIDEO
OUT
L2
C10
R9
-12V
65-1016-05
Figure 5. Typical Interface Circuit
Table 1. Bill of Materials
Resistors
Capacitors
Diodes
R1
5K
1/4W
10-turn
C1
0.01mF
50V
R2
1K
1/4W
10-tum
C2
1.0mF
10V
R3
1K
1/4W
5%
C3
1.0mF
10V
Transistors
R4
43
1/4W
5%
C4
2.2mF
25V
Q1
2N2907
R5
33
1/4W
5%
C5
0.1mF
50V
Q2
2N2907
R6
330
1/4W
5%
C6
2–5pF
50V
Q3
2N2907
R7
750
1/4W
5%
C7
0.1mF
50V
Q4
2N6660
R8, R9
10
1/4W
5%
C8
0.1mF
50V
Q5
2N6660
R10
75
1/4W
2%
C9
0.1mF
50V
R11, R12
10K
1/4W
5%
C10
0.1mF
50V
R13
220
1/4W
5%
R14, R15
100
1/4W
5%
RF Chokes
R16, R22
390
1/4W
5%
L1, L2
R17, R18
2K
1/4W
10-turn
R19
1K
1/4W
5%
R20, R21
1K
1/4W
5%
Ferrite Beads
CR1
1N4001
Integrated Circuits
U1
TDC1016
U2
LM113
U3
HA2539
U4
SN7404
9
TDC1016
PRODUCT SPECIFICATION
Mechanical Dimensions
40 Lead Sidebrazed Ceramic DIP
Inches
Symbol
A
b1
b2
c1
D
E
Min.
Max.
Min.
Max.
.120
.014
.040
.175
.023
.065
3.05
.360
1.02
4.44
.580
1.65
.008
.015
1.970
2.030
.575
.610
.100 BSC
.600 BSC
.125
.200
.025
.060
.005
—
.005
—
e
eA
L
Q
S1
S2
Notes:
Millimeters
.200
.380
50.04
51.56
14.60
15.49
2.54 BSC
15.24 BSC
3.18
5.08
.63
1.52
.13
—
.13
—
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
7
2
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 20, 21, and 40 only.
7
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4, 8
6
3
5
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 40.
5. Applies to all four corners (leads number 1, 20, 21, and 40).
6. "eA" shall be measured at the centerline of the leads.
7. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat when lead finish is applied.
8. Thirty-eight spaces.
D
20
Note 1
1
E
21
S1
40
eA
S2
A
Q
L
b2
10
e
b1
c1
PRODUCT SPECIFICATION
TDC1016
Mechanical Dimensions (continued)
24 Lead Sidebrazed Ceramic DIP
Inches
Symbol
A
b1
b2
c1
D
E
Min.
Max.
Min.
Max.
.120
.014
.040
.175
.023
.065
3.05
.360
1.02
4.44
.580
1.65
.008
.015
1.180
1.220
.575
.610
.100 BSC
.600 BSC
.125
.200
.025
.060
.005
—
.005
—
e
eA
L
Q
S1
S2
Millimeters
.200
.380
29.97
30.99
14.60
15.49
2.54 BSC
15.24 BSC
3.18
5.08
.630
1.52
.13
—
.13
—
Notes:
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
7
2
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 12, 13, and 24 only.
7
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4, 8
7
3
5
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
5. Applies to all four corners (leads number 1, 12, 13, and 24).
6. "eA" shall be measured at the centerline of the leads.
7. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat when lead finish is applied.
8. Twenty-two spaces.
D
12
Note 1
1
E
13
24
S1
eA
S2
A
Q
L
b2
e
b1
c1
11
TDC1016
PRODUCT SPECIFICATION
Ordering Information
Product Number
Temperature Range
TDC1016J5CX
STD – TA = 0°C to 70°C
TDC1016J5AX
EXT – TC = -55°C to 125°C
TDC1016J7CX
STD – TA = 0°C to 70°C
TDC1016J7AX
EXT – TC = -55°C to 125°C
Screening
Package
Package Marking
Commercial
40 Pin Ceramic
1016J5CX
High Reliability
40 Pin Ceramic
1016J5AX
Commercial
24 Pin Ceramic
1016J7CX
High Reliability
24 Pin Ceramic
1016J7AX
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
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Ó 1998 Fairchild Semiconductor Corporation