TI THS4520RGTR

THS4520
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER
WITH RAIL-TO-RAIL OUTPUTS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Fully Differential Architecture With
Rail-to-Rail Outputs
Centered Input Common-mode Range
Minimum Gain of 1 V/V (0 dB)
Bandwidth: 620 MHz
Slew Rate: 570 V/µs
0.1% Settling Time: 7 ns
HD2: –115 dBc at 100 kHz, VOD = 8 VPP
HD3: –123 dBc at 100 kHz, VOD = 8 VPP
Input Voltage Noise: 2 nV/√Hz (f >10 kHz)
Output Common-Mode Control
Power Supply:
– Voltage: 3.3 V (±1.5 V) to 5 V (±2.5 V)
– Current: 14.2 mA
Power-Down Capability: 15 µA
The THS4520 is a wideband, fully differential
operational amplifier designed for 5-V data
acquisition systems. It has very low noise at
2 nV/√Hz, and low harmonic distortion of –115 dBc
HD2 and –123 dBc HD3 at 100 kHz with 8 VPP, and
1-kΩ load. The slew rate is 570 V/µs, and with a
settling time of 7 ns to 0.1% (2-V step), it is ideal for
data acquisition applications. It is designed for unity
gain stability.
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 0.25 mV offset (typical)
from the set voltage. The common-mode set point
defaults to mid-supply by internal circuitry, which
may be over-driven from an external source.
The input and output are optimized for best
performance with their common-mode voltages set to
mid-supply. Along with high performance at low
power supply voltage, this makes for extremely high
performance single supply 5-V and 3.3-V data
acquisition systems.
APPLICATIONS
•
•
•
•
•
5-V and 3.3-V Data Acquisition Systems
High Linearity ADC Amplifier
Wireless Communication
Test and Measurement
Voice Processing Systems
The THS4520 is offered in a Quad 16-pin leadless
QFN package (RGT), and is characterized for
operation over the full industrial temperature range
from –40°C to 85°C.
RELATED PRODUCTS
Device
BW
(MHZ)
Slew Rate
(V/µsec)
THD
(dBc)
VN
(nV/Hz)
THS4509
2000
6600
-102 at 10 MHz
1.9
THS4500
370
2800
-82 at 8 MHz
7
THS4130
150
52
-97 at 250 kHz
1.3
From
50 W
Source
VIN
487 W
499 W
2.5 V
53.6 W
487 W
487 W
0.22 mF
49.9 W
53.6 W
THS4520
CM
487 W
1:1
56.3 W
VOUT
To 50 W
Test
Equipment
Open
−2.5 V
499 W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
THS4520
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
VS– to VS+
Supply voltage
6V
VI
Input voltage
±VS
VID
Differential input voltage
4V
IO
current (1)
Output
200 mA
Continuous power dissipation
TJ
See Dissipation Rating Table
Maximum junction temperature
150°C
Maximum junction temperature, continuous operation, long term reliability
125°C
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings
(1)
300°C
HBM
2000
CDM
1500
MM
100
The THS4520 incorporates a (QFN) exposed thermal pad on the underside of the chip. See TI technical brief SLMA002 and SLMA004
for more information about utilizing the QFN thermally enhanced package.
DISSIPATION RATINGS TABLE PER PACKAGE
(1)
2
PACKAGE (1)
θJC
θJA
RGT (16)
2.4°C/W
39.5°C/W
POWER RATING
TA≤ 25°C
TA = 85°C
2.3 W
225 mW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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THS4520
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
DEVICE INFORMATION
RGT Package
(TOP VIEW)
VS−
16
15
14
13
NC
1
12
PD
VIN−
2
11
VIN+
VOUT+
3
10
VOUT−
CM
4
9
5
7
6
CM
8
VS+
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
NO.
DESCRIPTION
NAME
1
NC
No internal connection
2
VIN–
Inverting amplifier input
3
VOUT+
Non-inverted amplifier output
4, 9
CM
Common-mode voltage input
5, 6, 7, 8
VS+
Positive amplifier power supply input
10
VOUT–
Inverted amplifier output
11
VIN+
Non-inverting amplifier input
12
PD
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation.
If the PD pin is open (unterminated) the device will default to the enabled state.
13, 14, 15, 16
VS–
Negative amplifier power supply input
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
SPECIFICATIONS; VS+– VS– = 5 V:
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 499 Ω,
RL = 200 Ω Differential, TA = 25°C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
Small-Signal Bandwidth
G = 0 dB, VO = 100 mVPP
620
MHz
G = 6 dB, VO = 100 mVPP
450
MHz
G = 10 dB, VO = 100 mVPP
330
MHz
G = 20 dB, VO = 100 mVPP
120
MHz
1200
MHz
Gain-Bandwidth Product
G = 20 dB
Bandwidth for 0.1 dB flatness
G = 10 dB, VO = 2 VPP
30
MHz
Large-Signal Bandwidth
G = 10 dB, VO = 2 VPP
132
MHz
570
V/µs
Slew Rate (Differential)
Rise Time
Fall Time
4
2-V Step
4
Settling Time to 1%
Settling Time to 0.1%
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
ns
6.2
C
7
f = 100 kHz,
RL = 1 kΩ
f = 100 kHz,
RL = 1 kΩ
VOD = 8 VPP
–115
dBc
VOD = 8 VPP
–123
dBc
fC = 100 kHz
–135
dBc
3rd Order Intermodulation Distortion
1-kHz Tone Spacing,
RL = 1 kΩ,
VOD = 4 VPP/Tone
Input Voltage Noise
f > 10 kHz
2
nV/√Hz
Input Current Noise
f > 10 kHz
2
pA/√Hz
TA = 25°C
±0.25
±2.5
mV
TA = –40°C to 85°C
±0.25
±3
mV
TA = 25°C
6.5
10
TA = –40°C to 85°C
6.4
11
TA = 25°C
±0.2
±2.5
TA = –40°C to 85°C
±0.2
±3
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Input Bias Current
Input Offset Current
112
dB
C
A
µA
A
µA
A
INPUT
Common-Mode Input Range High
1.75
Common-Mode Input Range Low
-1.3
Common-Mode Rejection Ratio
(1)
4
84
V
B
dB
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
SPECIFICATIONS; VS+– VS– = 5 V: (continued)
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 0 dB, CM = open, VO = 2 VPP, RF = 499 Ω,
RL = 200 Ω Differential, TA = 25°C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
1.95
2.16
1.9
2.16
MAX
UNIT
TEST
LEVEL (1)
OUTPUT
Maximum Output Voltage High
TA = 25°C
Each output with 100 Ω
to mid-supply
Minimum Output Voltage Low
TA = –40°C to 85°C
V
TA = 25°C
–2.16
–1.95
TA = –40°C to 85°C
–2.16
–1.9
7.8
V
Differential Output Voltage Swing
TA = –40°C to 85°C
8.64
V
Differential Output Current Drive
RL = 10 Ω
105
mA
Output Balance Error
VO = 100 mV, f = 1 MHz
–80
dB
230
MHz
1
V/V
A
C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth
Gain
Output Common-Mode Offset
from CM input
1.25 V < CM < 3.5 V
±0.25
mV
CM Input Bias Current
1.25 V < CM < 3.5 V
0.6
µA
CM Input Voltage
CM Default Voltage
-1.5
CM = 0.5 (VS+ + VS- )
1.5
0
C
V
V
POWER SUPPLY
Specified Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
5
5.25
TA = 25°C
3
14.2
15.3
TA = –40°C to 85°C
14.2
15.5
TA = 25°C
TA = –40°C to 85°C
Power Supply Rejection (±PSRR)
POWERDOWN
Referenced to Vs–
Enable Voltage Threshold
For additional information, see the Application
Information section of this data sheet.
Disable Voltage Threshold
Powerdown Quiescent Current
13.1
14.2
12.75
14.2
C
mA
A
mA
94
dB
>1.5
V
<-1.5
V
TA = 25°C
15
70
TA = –40°C to 85°C
15
75
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V
µA
C
C
A
5
THS4520
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
SPECIFICATIONS; VS+– VS– = 3.3 V:
Test conditions unless otherwise noted: VS+ = +1.65 V, VS– = –1.65 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 499 Ω,
RL = 200 Ω Differential, TA = 25°C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
PARAMETER
TEST CONDITIONS
TYP
UNIT
G = 0 dB, VO = 100 mVPP
600
MHz
G = 6 dB, VO = 100 mV PP
400
MHz
G = 10 dB, VO = 100 mVPP
310
MHz
G = 20 dB, VO = 100 mVPP
120
MHz
1200
MHz
30
MHz
520
V/µs
TEST
LEVEL (1)
AC PERFORMANCE
Small-Signal Bandwidth
Gain-Bandwidth Product
G = 20 dB
Bandwidth for 0.1-dB flatness
G = 6 dB, VO = 1 VPP
Large-Signal Bandwidth
G = 6 dB, VO = 1 VPP
Slew Rate (Differential)
Rise Time
Fall Time
GHz
C
4
2-V Step
Settling Time to 1%
4
6.6
Settling Time to 0.1%
ns
7.1
2nd Order Harmonic Distortion
f = 100 kHz, VOD = 4 VPP, RL = 1 kΩ
–135
dBc
3rd
f = 100 kHz, VOD = 4 VPP, RL = 1 kΩ
–146
dBc
Order Harmonic Distortion
Input Voltage Noise
f > 10 kHz
2
nV/√Hz
Input Current Noise
f > 10 kHz
2
pA/√Hz
104
dB
Input Offset Voltage
TA = 25°C
±0.25
mV
Input Bias Current
TA = 25°C
6.5
µA
Input Offset Current
TA = 25°C
±0.2
µA
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
C
INPUT
Common-Mode Input Range High
1.4
Common-Mode Input Range Low
-0.45
Common-Mode Rejection Ratio
(1)
6
84
V
C
dB
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
SPECIFICATIONS; VS+– VS– = 3.3 V: (continued)
Test conditions unless otherwise noted: VS+ = +1.65 V, VS– = –1.65 V, G = 0 dB, CM = open, VO = 1 VPP, RF = 499 Ω,
RL = 200 Ω Differential, TA = 25°C Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply
PARAMETER
TEST CONDITIONS
TYP
UNIT
TA = 25°C
1.4
V
TA = 25°C
-1.4
V
TEST
LEVEL (1)
OUTPUT
Maximum Output Voltage High
Minimum Output Voltage Low
Each output with 100 Ω to
mid-supply
Differential Output Voltage Swing
Differential Output Current Drive
RL = 10 Ω
Output Balance Error
VO = 100 mV, f = 1 MHz
5.6
V
78
mA
–80
dB
224
MHz
1
V/V
C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth
Gain
Output Common-Mode Offset
from CM input
1.25 V < CM < 3.5 V
±0.25
mV
CM Input Bias Current
1.25 V < CM < 3.5 V
0.6
µA
CM Default Voltage
CM = 0.5 (VS+ + VS- )
0
V
C
POWER SUPPLY
Specified Operating Voltage
Quiescent Current
TA = 25°C
Power Supply Rejection (±PSRR)
POWERDOWN
Referenced to Vs–
Enable Voltage Threshold
For additional information, see the Application Information
section of this data sheet.
Disable Voltage Threshold
Powerdown Quiescent Current
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3.3
V
13
mA
94
dB
>1
V
<-1
V
10
µA
C
C
7
THS4520
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+– VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, CM = open, VO = 2 VPP, RF = 499 Ω, RL = 200 Ω
Differential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequency Response
Figure 1
Large Signal Frequency Response
Figure 2
0.1 dB Flatness
Figure 3
S-Parameters
vs Frequency
Figure 4
Transition Rate
vs Output Voltage
Figure 5
Figure 6
Transient Response
Figure 7
Output Voltage Swing
vs Load Resistance
Input Offset Voltage
vs Input Common-Mode Voltage
Figure 8
Figure 9
Input Bias Current
vs Supply Voltage
Figure 10
Open Loop Gain
vs Frequency
Figure 11
Input Referred Noise
vs Frequency
Figure 12
Quiescent Current
vs Supply Voltage
Figure 13
Power Supply Current
vs Supply Voltage in Powerdown Mode
Figure 14
Output Balance Error
vs Frequency
Figure 15
CM Small-Signal Frequency Response
Figure 16
CM Input Bias Current
vs CM Input Voltage
Figure 17
Differential Output Offset Voltage
vs CM Input Voltage
Figure 18
Output Common-Mode Offset
vs CM Input Voltage
Figure 19
SMALL-SIGNAL
FREQUENCY RESPONSE
22
RF = 499 W
20
18
G = 20 dB
VO = 100 mVPP
VS = ±2.5 V
16
G = 14 dB
10
8
G = 10 dB
6
4
2
G = 6 dB
G = 20 dB
12
10
8
G = 10 dB
6
2
G = 0 dB
RL = 200 W
G = 14 dB
G = 6 dB
G = 0 dB
0
0.1
1
10
f - Frequency - MHz
100
1000
-2
0.1
Figure 1.
8
VO = 2 VPP
VS = ±2.5 V
14
4
0
-2
18
16
14
12
RF = 499 W
20
RL = 200 W
Signal Gain - dB
Signal Gain - dB
LARGE-SIGNAL FREQUENCY RESPONSE
22
1
10
f - Frequency - MHz
Figure 2.
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1000
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
0.1-dB FLATNESS
S-PARAMETERS vs FREQUENCY
10
6.5
Gain
V
= 6 dB
mVPP
O = 100
WV
R
=±
499
VS
1.65
F=
RL = 200 W
VO = 100 mVPP
VS = ±2.5 V
Signal Gain − dB
6.3
6.2
6.1
0
S21
-10
S-Parameters - dB
6.4
6
5.9
-20
-30
-40
S11
-50
5.8
-60
5.7
-70
5.6
-80
S22
Gain = 0 dB
RF = 499 W
S12
RL = 200 W
VO = 100 mVPP
VS = ±2.5 V
-90
5.5
0.1
1
10
100
f − Frequency − MHz
1000
10000
10
1
Figure 3.
TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
2.5
V OD − Differential Output V oltage − V
Rise
550
Fall
Slew Rate - V/ms
500
450
400
350
Gain = 6 dB
RF = 499 W
300
RL = 200 W
VS = ±2.5 V
250
2
1.5
1
VOD = 4 VPP
VS = ±2.5 V
Gain = 6 dB
RL = 200 W
-0.5
0
-0.5
-1
-1.5
-2
-2.5
0
1
3
5
6
7
2
4
VOD - Differential Output Voltage - VPP
8
t − Time − 5 ns/div
Figure 5.
Figure 6.
TRANSIENT RESPONSE
OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
1.5
10
1
VOD = 2 VPP
VS = ±2.5 V
Gain = 6 dB
RL = 200 W
-0.5
0
-0.5
-1
-1.5
t −Time − 5 ns/div
VOD - Differential Output Voltage - V
V OD − Differential Output V oltage − V
1000
Figure 4.
600
200
100
f - Frequency - MHz
9
VS = 5 V
8
7
6
5
4
3
2
1
0
10
Figure 7.
100
RL - Load Resistance - W
1000
Figure 8.
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INPUT BIAS CURRENT
vs
SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE vs
INPUT COMMON-MODE VOLTAGE
7.5
0
o
IIB - Input Bias Voltage - mA
VIO - Input Offset Voltage - mV
-0.05
o
TA = 85 C
-0.1
-0.15
o
TA = 25 C
-0.2
o
TA = -40 C
-0.25
TA = 85 C
TA = 25oC
7
6.5
6
5.5
o
TA = -40 C
5
4.5
4
3.5
-0.3
1.5
1.6
1.7
1.8 1.9
2
2.1 2.2
VS - Supply Voltage - ±V
2.3
2.4
3
1.5
2.5
1.6
1.7
1.8 1.9
2
2.1 2.2
VS - Supply Voltage - ±V
Figure 9.
OPEN LOOP GAIN AND PHASE vs FREQUENCY
-80
40
-120
20
-160
100
1
10 k
100 M
1M
Vn − Voltage Noise − nV/ Hz
-40
I n − Current Noise − pA/ Hz
Phase
Open Loop Phase − degrees
Open Loop Gain − dB
INPUT REFERRED NOISE vs FREQUENCY
0
Gain
60
0
10
In
Vn
-200
10 G
1
10
10 k
100 k
1M
Figure 11.
Figure 12.
QUIESCENT CURRENT vs SUPPLY VOLTAGE
POWER SUPPLY CURRENT vs SUPPLY VOLTAGE IN
POWER-DOWN MODE
15
10
14.5
14
9
o
TA = 85 C
TA = 25oC
Power Supply Current - mA
IQ - Quiescent Current - mA
1k
100
f − Frequency − Hz
f − Frequency − Hz
13.5
13
12.5
12
o
TA = -40 C
11.5
11
10.5
10
1.5
8
TA = 85oC
7
6
5
4
3
TA = 25oC
o
TA = -40 C
2
1
1.75
2
2.25
VS - Supply Voltage - ±V
2.5
0
1.5
Figure 13.
10
2.5
100
40
80
2.4
Figure 10.
120
100
2.3
1.75
2
2.25
VS - Supply Voltage - ±V
Figure 14.
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OUTPUT BALANCE ERROR vs FREQUENCY
CM SMALL SIGNAL FREQUENCY RESPONSE
-20
RF = 499 W
-40
RL = 200 W
VO = 1 VPP
VS = ±2.5 V
Gain = 6 dB
VOCM - Signal Gain - dB
Balance Error - dB
-30
-50
-60
Gain = 0 dB
-70
-80
-90
0.1
1
10
f - Frequency - MHz
100
1000
RF = 499 W
RL = 200 W
Gain = 0 dB
VO = 100 mVPP
VS = ±2.5 V
0.1
1
10
1000
100
f - Frequency - MHz
Figure 15.
Figure 16.
CM INPUT BIAS CURRENT vs CM INPUT VOLTAGE
DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs
CM INPUT VOLTAGE
4
Differential Output Offset Voltage - mV
200
150
100
50
0
-50
-100
-150
-2.5
-2
-1.5 -1 -0.5 0
0.5
1
1.5
VICR - Common-Mode Input Voltage - V
2
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-2.5
2.5
-2
-1.5 -1 -0.5 0
0.5
1
1.5
VICR - Common-Mode Input Voltage - V
Figure 17.
2
2.5
Figure 18.
OUTPUT COMMON-MODE OFFSET vs
CM INPUT VOLTAGE
50
Output Common-Mode Offset - mV
Common-Mode Input Bias Current - mA
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
40
30
20
10
0
-10
-20
-30
-40
-50
-2.5
-2
-1.5 -1 -0.5 0
0.5
1
1.5
VICR - Common-Mode Input Voltage - V
2
2.5
Figure 19.
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SLOS503A – SEPTEMBER 2006 – REVISED OCTOBER 2006
TYPICAL AC PERFORMANCE: VS+– VS– = 3.3 V
Test conditions unless otherwise noted: VS+ = 1.65 V, VS– = –1.65 V, CM = open, VOD = 1 VPP, RF = 499 Ω, RL = 200 Ω
Differential, G = 0 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequency Response
Figure 20
Large Signal Frequency Response
Figure 21
0.1 dB Flatness
Figure 22
S-Parameters
vs Frequency
Figure 23
Transition Rate
vs Output Voltage
Figure 24
Figure 25
Transient Response
Figure 26
Output Balance Error
vs Frequency
Figure 27
CM Input Impedance
vs Frequency
Figure 28
SMALL-SIGNAL FREQUENCY RESPONSE
22
RF = 499 W
20
G = 20 dB
18
Signal Gain - dB
G = 14 dB
10
G = 10 dB
8
6
G = 6 dB
4
2
G = 14 dB
12
10
G = 10 dB
8
6
G = 6 dB
2
G = 0 dB
G = 0 dB
0
0.1
1
10
f - Frequency - MHz
-2
1000
100
0.1
1
10
100
f - Frequency - MHz
Figure 20.
0.1 dB FLATNESS
S-PARAMETERS vs FREQUENCY
10
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
5.9
5.8
5.7
5.6
5.5
Gain
V
= 6 dB
mVPP
O = 100
R
=±
499
WV
VF =
1.65
0
S
S21
-10
RL = 200 W
VO = 100 mVPP
VS = ±1.65 V
S-Parameters - dB
Signal Gain − dB
1000
Figure 21.
7
-20
-30
-40
S11
-50
-60
S22
Gain = 0 dB
RF = 499 W
S12
RL = 200 W
VO = 100 mVPP
VS = ±2.5 V
-70
-80
-90
0.1
1
10
100
f − Frequency − MHz
1000
10000
1
10
100
f - Frequency - MHz
Figure 22.
12
RL = 200 W
VO = 1 VPP
VS = ±1.65 V
14
4
0
-2
G = 20 dB
18
16
14
12
RF = 499 W
20
RL = 200 W
VO = 100 mVPP
VS = ±1.65 V
16
Signal Gain - dB
LARGE-SIGNAL FREQUENCY RESPONSE
22
Figure 23.
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TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
600
V OD − Differential Output V oltage − V
2.5
550
500
Slew Rate - V/ms
Rise
450
Fall
400
350
300
Gain = 6 dB
RF = 499 W
250
RL = 200 W
VS = ±1.65 V
200
2
1.5
1
VOD = 4 VPP
VS = ±1.65 V
Gain = 6 dB
RL = 200 W
-0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.5
1.5
2.5
3
3.5
1
2
VOD - Differential Output Voltage - VPP
4
t − Time − 5 ns/div
Figure 24.
Figure 25.
OUTPUT BALANCE ERROR vs FREQUENCY
-20
1
-30
Balance Error - dB
RF = 499 W
VOD = 2 VPP
VS = ±1.65 V
Gain = 6 dB
RL = 200 W
-0.5
0
-0.5
-1
RL = 200 W
VO = 1 VPP
VS = ±1.65 V
-40
Gain = 0 dB
-50
-60
Gain = 6 dB
-70
-80
-1.5
-90
0.1
t −Time − 5 ns/div
1
10
f - Frequency - MHz
Figure 26.
100
1000
Figure 27.
CM INPUT IMPEDANCE vs FREQUENCY
VOCM - Signal Gain - dB
V OD − Differential Output V oltage − V
TRANSIENT RESPONSE
1.5
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
RF = 499 W
RL = 200 W
Gain = 0 dB
VO = 100 mVPP
VS = ±1.65 V
0.1
1
10
100
1000
f - Frequency - MHz
Figure 28.
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TEST CIRCUITS
The THS4520 is tested with the following test circuits
built on the EVM. For simplicity, power supply
decoupling is not shown – see layout in the
applications section for recommendations.
From
50 W
Source
VIN
RG
RIT
RF
VS+
RO
THS4520
0.22 mF
1:1
ROT
RO
CM
RIT
VOUT
To 50 W
Test
Equipment
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated in test. The column Atten in Table 2
shows the attenuation expected from the resistor
divider. When using a transformer at the output the
signal will have slightly more loss, and the numbers
will be approximate.
Frequency Response
Open
VS-
49.9 W
Note: The total load includes 50-Ω termination by the
test equipment. Components are chosen to achieve
load and 50-Ω line termination through a 1:1
transformer.
RF
Figure 29. General Test Circuit for Device Testing
and Characterization
Depending on the test conditions, component values
are changed per the following tables, or as otherwise
noted. The signal generators used are ac coupled
50-Ω sources and a 0.22-µF capacitor and a 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input to balance the circuit. A split power
supply is used to ease the interface to common test
equipment, but the amplifier can be operated
single-supply as described in the applications section
with no impact on performance.
The general circit shown in Figure 29 is modified as
shown in Figure 30, and is used to measure the
frequency response of the device.
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
The output is probed using a high-impedance
differential probe across the 100-Ω resistor. The gain
is referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
From
50 W
Source
Table 1. Gain Component Values
GAIN
RF
RG
RIT
0 dB
499 Ω
487 Ω
53.6 Ω
6 dB
499 Ω
243 Ω
57.6 Ω
10 dB
499 Ω
147 Ω
63.4 Ω
14 dB
499 Ω
88.7 Ω
71.5 Ω
20 dB
499 Ω
34.8 Ω
115 Ω
Note: The gain setting includes 50-Ω source
impedance. Components are chosen to achieve gain
and 50-Ω input termination.
VIN
14
RO
ROT
RG
0.22 mF
49.9 W
25 Ω
open
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1 kΩ
487 Ω
52.3 Ω
31.8 dB
VS+
THS4520
CM
R IT
VS−
49.9 W
100 W
Output Measured
Here With High
Impedance
Differential Probe
Open
0.22 mF
RF
Figure 30. Frequency Response Test Circuit
Atten.
100 Ω
R IT
49.9 W
Table 2. Load Component Values
RL
RF
RG
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S-Parameter, Slew Rate, Transient Response,
Settling Time, Output Voltage
The circuit shown in Figure 31 is used to measure
s-parameters, slew rate, transient response, settling
time, and output voltage swing.
Because S21 is measured single-ended at the load
with 50-Ω double termination, add 12 dB to see the
amplifier’s output as a differential signal.
From V IN
50 Ω
Source
RG
R IT
RF
0.22 mF
49.9 W
The circuit shown in Figure 32 is used to measure
the frequency response of the CM input. Frequency
response is measured single-ended at VOUT+ or
VOUT– with the input injected at VIN, RCM = 0 Ω and
RCMT = 49.9 Ω.
RIT
VOUT–
RG
CM
R IT
VS−
VS+
49.9 W
VS+
THS4520
RF
RG
0.22 mF
49.9 W
49.9 W
RG
CM Input
49.9 W
VOUT+ To 50 W
Test
VOUT− Equipment
Open
0.22 mF
0.22 mF
THS4520
49.9 W
VOUT+
CM
RIT
RCM
VIN
VS–
49.9 W
RF
To
50-W
Test
Equipment
RCMT
From
50-W
Source
Figure 32. CM Input Test Circuit
RF
Figure 31. S-Parameter, SR, Transient Response,
Settling Time, VOUT Swing
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APPLICATION INFORMATION
APPLICATIONS
Single-Ended
Input
VS
The following circuits show application information
for the THS4520. For simplicity, power supply
decoupling capacitors are not shown in these
diagrams. For more detail on the use and operation
of fully differential op amps see application report
Fully-Differential Amplifiers (SLOA054) .
RF
Differential
Input
Differential
Output
VS+
RG
+
V IN+
–
VOUT–
THS4520
VIN–
RG
– +
VOUT+
VS–
RF
Figure 33. Differential Input to Differential Output
Amplifier
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
Single-Ended
Amplifier
Input
to
Differential
Output
The THS4520 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 34 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
16
Differential
Output
+
–
VOUT–
THS4520
RG
–
Differential Input to Differential Output Amplifier
The THS4520 is a fully differential op amp, and can
be used to amplify differential input signals to
differential output signals. A basic block diagram of
the circuit is shown in Figure 33 (CM input not
shown). The gain of the circuit is set by RF divided by
RG.
RF
RG
+
VOUT+
VS
RF
Figure 34. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-model voltage of a fully
differential op amp is the voltage at the '+' and '–'
input pins of the op amp.
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation, the differential voltage
across the input pins is only a few millivolts at most.
So finding the voltage at one input pin determines
the input common-mode voltage of the op amp.
Treating the negative input as a summing node, the
voltage is given by Equation 1:
ö æ
æ
ö
RG
RF
÷ + ç VIN- ´
÷
VIC = çç VOUT + ´
÷
ç
R G + R F ÷ø
R G + RF ø è
è
(1)
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
VOUT+.
As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 0.25-mV offset (typical) from the set
voltage, when set within ±0.5 V of mid-supply. If left
unconnected, the common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source. Figure 35 is
representative of the CM input. The internal CM
circuit has about 230 MHz of bandwidth, which is
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required for best performance, but it is intended to be
a DC bias input pin. Bypass capacitors are
recommended on this pin to reduce noise at the
output. The external current required to overdrive the
internal resistor divider is given by Equation 2:
IEXT =
2VCM - (VS + - VS - )
50 kW
(2)
where VCM is the voltage applied to the CM pin.
VS+
50 kW
I EXT
to internal
CM circuit
CM
50 kW
Single-Supply Operation (3 V to 5 V)
To facilitate testing with common lab equipment, the
THS4520 EVM allows split-supply operation, and the
characterization data presented in this data sheet
was taken with split-supply power inputs. The device
can easily be used with a single-supply power input
without degrading the performance. Figure 36,
Figure 37, and Figure 38 show DC and AC-coupled
single-supply circuits with single-ended inputs. These
configurations all allow the input and output
common-mode voltage to be set to mid-supply
allowing for optimum performance. The information
presented here can also be applied to differential
input sources.
In Figure 36, the source is referenced to the same
voltage as the CM pin (VCM). VCM is set by the
internal circuit to mid-supply. RT along with the input
impedance of the amplifier circuit provides input
termination, which is also referenced to VCM.
Note RS and RT are added to the alternate input from
the signal input to balance the amplifier. Alternately,
one resistor can be used equal to the combined
value RG+ RS||RT on this input. This is also true of
the circuits shown in Figure 37 and Figure 38.
V S–
Figure 35. CM Input Circuit
Powerdown Operation: Device
Enable/Disable Thresholds
The enable/disable thresholds of the THS4520 are
dependent upon the power supplies, and the
thresholds are always referenced to the lower power
supply rail. The device is enabled or disabled for the
following conditions:
• Device enabled: VPD > VS- + 0.8 x (VS+ - VS-)
• Device disabled: VPD < VS- + 0.2 x (VS+ - VS-)
RS
RG
RT
VSignal
RF
VS+
RO
VCM
VBias= VCM
THS4520
RG
RS
RT
RO
VOUTVOUT+
CM
VS–
VCM
If the PD pin is left open, the device will default to the
enabled state.
VCM VCM
RF
Table 3 shows the thresholds for some common
power supply configurations:
Figure 36. THS4520 DC Coupled Single-Supply
with Input Biased to VCM
Table 3. Power Supply Configurations
In Figure 37 the source is referenced to ground and
so is the input termination resistor. RPU is added to
the circuit to avoid violating the VICR of the op amp.
The proper value of resistor to add can be calculated
from Equation 3:
Power
Supply
(VS+, VS-)
Enable
Threshold
(V)
Disable
Threshold
(V)
±2.5 V
1.5
-1.5
Shown in data
table
±1.65 V
1
-1
Shown in data
table
Comment
(4 V , -1 V)
3
0
Split,
unbalanced
supplies
(5 V, gnd)
4
1
Single-sided
supply
(3.3 V, gnd)
2.64
0.66
Single-sided
supply
0.6
Single-sided
supply
(3 V, gnd)
2.4
R PU =
(VIC - VS+ )
æ 1
VCM çç
è RF
æ 1
ö
1
÷÷ - VIC çç
+
è R IN R F
ø
ö
÷÷
ø
(3)
VIC is the desired input common-mode voltage,
VCM = CM, and RIN = RG+ RS||RT. To set to
mid-supply, make the value of RPU = RG+ RS||RT.
Table 4 is a modification of Table 1 to add the proper
values with RPU assuming a 50-Ω source impedance
and setting the input and output common-mode
voltage to mid-supply.
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There are two drawbacks to this configuration. One
is it requires additional current from the power
supply. Using the values shown for a gain of 0 dB
requires 10 mA more current with 5-V supply, and
6.5 mA more current with 3.3-V supply.
The other drawback is this configuration also
increases the noise gain of the circuit. In the 10-dB
gain case, noise gain increases by a factor of 1.7.
Table 4. RPU Values for Various Gains
Gain
RF
RG
RIT
RPU
0 dB
499 Ω
487 Ω
54.9 Ω
511 Ω
6 dB
499 Ω
243 Ω
59 Ω
270 Ω
10 dB
499 Ω
150 Ω
68.1 Ω
178 Ω
14 dB
499 Ω
93.1 Ω
82.5 Ω
124 Ω
20 dB
499 Ω
40.2 Ω
221 Ω
80.6 Ω
V S+
R PU
RS
RF
RG
RT
V Signal
V S+
V S+
RO
V OUT-
R PU
THS4520
RG
RO
V OUT+
RS
CM
V S-
RT
1. Signal routing should be direct and as short as
possible into and out of the op amp circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed
from directly under the amplifier’s input and
output pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-µF and two 0.1-µF power-supply
decoupling capacitors should be placed as near
to the power-supply pins as possible.
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be
placed to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4520 recommended PCB footprint is
shown in Figure 39.
RF
0.144
Figure 37. THS4520 DC Coupled Single-Supply
with RPU Used to Set VIC
Figure 38 shows AC coupling to the source. Using
capacitors in series with the termination resistors
allows the amplifier to self-bias both input and output
to mid-supply.
C
RS
V Signal
0.012
Pin 1
0.015
0.144
0.0195 0.0705
V S+ = 3 V to 5 V
0.010
vias
0.032
RO
C
V OUTTHS4520
RG
0.030
RO
V OUT+
RS
RT
C
C
0.0245
CM
V S-
Top View
Figure 39. QFN Etch and Via Pattern
RF
Figure 38. THS4520 AC Coupled Single-Supply
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
18
0.0095
RF
RG
RT
0.049
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THS4520 EVM
Figure 40 is the THS4520 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 41, and
Table 5 is the bill of material for the EVM as supplied from TI.
GND
VS−
J4
VS+
J5
J6
VEE
0.1 mF
TP1
C9
C10
0.1 mF
VCC
10 mF
C4
10 mF
C15
R12
12
2
3
VO+
−
U1 11
0.22 mF
+
J2
R4
487 W
R2
53.6 W
VO−
PwrPad 10
4
R9
open
7
PD
487 W
R7
86.6 W
R8
86.6 W
15 13
14 16 VEE
R6
J3
T1
R11
69.8 W
6
5
4
R10
open
3
C14
0.1 mF
C8
open
C7
open
C2
open
J7
499 W
TP3
TP2
C1
open
1
XFMR_ADT1−1WT
Vocm
9
C13
VEE
C11
0.1 mF
6481529
Figure 40. THS4520 EVAL1 EVM Schematic
THS4520RGT
49.9 W
5
0.1 mF
C12
VCC
VCC
8
6
R3
0.1 mF
C5
J8
499 W
R1
53.6 W
10 mF
C3
R5
J1
10 mF
C6
Figure 41. THS4520 EVAL1 EVM Layer 1 through 4
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Table 5. THS4520 EVAL1 EVM Bill of Materials
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
CAP, 10.0 µF, Ceramic, X5R, 6.3V
0805
C3, C4, C5, C6
4
(AVX) 08056D106KAT2A
2
CAP, 0.1 µF, Ceramic, X5R, 10V
0402
C9, C10, C11, C12, C13, C14
6
(AVX) 0402ZD104KAT2A
3
CAP, 0.22 ΩF, Ceramic, X5R, 6.3V
0402
C15
1
(AVX) 04026D224KAT2A
4
OPEN
0402
C1, C2, C7, C8
4
5
OPEN
0402
R9, R10
2
6
Resistor, 49.9 Ω, 1/16W, 1%
0402
R12
1
(KOA) RK73H1ETTP49R9F
7
Resistor, 53.6 Ω, 1/16W, 1%
0402
R1, R2
2
(KOA) RK73H1ETTP53R6F
8
Resistor, 69.8 Ω, 1/16W, 1%
0402
R11
1
(KOA) RK73H1ETTP69R8F
9
Resistor, 86.6 Ω, 1/16W, 1%
0402
R7, R8
2
(KOA) RK73H1ETTP86R6F
10
Resistor, 487 Ω, 1/16W, 1%
0402
R3, R4
2
(KOA) RK73H1ETTP4870F
11
Resistor, 499 Ω, 1/16W, 1%
0402
R5, R6
2
(KOA) RK73H1ETTP4990F
12
Transformer, RF
T1
1
(MINI-CIRCUITS) ADT1-1WT
13
Jack, banana receptance, 0.25" diameter
hole
J4, J5, J6
3
(HH SMITH) 101
14
OPEN
J1, J7, J8
3
15
Connector, edge, SMA PCB Jack
J2, J3
2
(JOHNSON) 142-0701-801
16
Test point, Red
TP1, TP2, TP3
3
(KEYSTONE) 5000
17
IC, THS4520
U1
1
(TI) THS4520RGT
18
Standoff, 4-40 HEX, 0.625" length
4
(KEYSTONE) 1808
19
SCREW, PHILLIPS, 4-40, 0.250"
4
SHR-0440-016-SN
20
Printed circuit board
1
(TI) EDGE# 6481529
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of
3 V to 5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
If there are questions concerning the input range, please contact a TI field representative prior to connecting
the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM
output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM
is designed to operate properly with certain components above 85°C as long as the input and output ranges
are maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
20
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4520RGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4520RGTRG4
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4520RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4520RGTTG4
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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